Searched defs:pll_con1 (Results 1 – 2 of 2) sorted by relevance
| /openbmc/u-boot/drivers/clk/exynos/ |
| H A D | clk-pll.c | 21 unsigned long pll_con1 = readl(con1); in pll145x_get_rate() local
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| /openbmc/linux/drivers/clk/samsung/ |
| H A D | clk-pll.c | 327 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; in samsung_pll36xx_recalc_rate() local
346 const struct samsung_pll_rate_table *rate, u32 pll_con0, u32 pll_con1) in samsung_pll36xx_mpk_change()
362 u32 pll_con0, pll_con1; in samsung_pll36xx_set_rate() local
637 static bool samsung_pll45xx_mp_change(u32 pll_con0, u32 pll_con1, in samsung_pll45xx_mp_change()
753 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift; in samsung_pll46xx_recalc_rate() local
774 static bool samsung_pll46xx_mpk_change(u32 pll_con0, u32 pll_con1, in samsung_pll46xx_mpk_change()
922 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; in samsung_pll6553_recalc_rate() local
1102 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; in samsung_pll2650x_recalc_rate() local
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