xref: /openbmc/linux/include/ufs/ufshcd.h (revision 8d1af5c6)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Universal Flash Storage Host controller driver
4  * Copyright (C) 2011-2013 Samsung India Software Operations
5  * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6  *
7  * Authors:
8  *	Santosh Yaraganavi <santosh.sy@samsung.com>
9  *	Vinayak Holikatti <h.vinayak@samsung.com>
10  */
11 
12 #ifndef _UFSHCD_H
13 #define _UFSHCD_H
14 
15 #include <linux/bitfield.h>
16 #include <linux/blk-crypto-profile.h>
17 #include <linux/blk-mq.h>
18 #include <linux/devfreq.h>
19 #include <linux/msi.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/dma-direction.h>
22 #include <scsi/scsi_device.h>
23 #include <scsi/scsi_host.h>
24 #include <ufs/unipro.h>
25 #include <ufs/ufs.h>
26 #include <ufs/ufs_quirks.h>
27 #include <ufs/ufshci.h>
28 
29 #define UFSHCD "ufshcd"
30 
31 struct ufs_hba;
32 
33 enum dev_cmd_type {
34 	DEV_CMD_TYPE_NOP		= 0x0,
35 	DEV_CMD_TYPE_QUERY		= 0x1,
36 	DEV_CMD_TYPE_RPMB		= 0x2,
37 };
38 
39 enum ufs_event_type {
40 	/* uic specific errors */
41 	UFS_EVT_PA_ERR = 0,
42 	UFS_EVT_DL_ERR,
43 	UFS_EVT_NL_ERR,
44 	UFS_EVT_TL_ERR,
45 	UFS_EVT_DME_ERR,
46 
47 	/* fatal errors */
48 	UFS_EVT_AUTO_HIBERN8_ERR,
49 	UFS_EVT_FATAL_ERR,
50 	UFS_EVT_LINK_STARTUP_FAIL,
51 	UFS_EVT_RESUME_ERR,
52 	UFS_EVT_SUSPEND_ERR,
53 	UFS_EVT_WL_SUSP_ERR,
54 	UFS_EVT_WL_RES_ERR,
55 
56 	/* abnormal events */
57 	UFS_EVT_DEV_RESET,
58 	UFS_EVT_HOST_RESET,
59 	UFS_EVT_ABORT,
60 
61 	UFS_EVT_CNT,
62 };
63 
64 /**
65  * struct uic_command - UIC command structure
66  * @command: UIC command
67  * @argument1: UIC command argument 1
68  * @argument2: UIC command argument 2
69  * @argument3: UIC command argument 3
70  * @cmd_active: Indicate if UIC command is outstanding
71  * @done: UIC command completion
72  */
73 struct uic_command {
74 	u32 command;
75 	u32 argument1;
76 	u32 argument2;
77 	u32 argument3;
78 	int cmd_active;
79 	struct completion done;
80 };
81 
82 /* Used to differentiate the power management options */
83 enum ufs_pm_op {
84 	UFS_RUNTIME_PM,
85 	UFS_SYSTEM_PM,
86 	UFS_SHUTDOWN_PM,
87 };
88 
89 /* Host <-> Device UniPro Link state */
90 enum uic_link_state {
91 	UIC_LINK_OFF_STATE	= 0, /* Link powered down or disabled */
92 	UIC_LINK_ACTIVE_STATE	= 1, /* Link is in Fast/Slow/Sleep state */
93 	UIC_LINK_HIBERN8_STATE	= 2, /* Link is in Hibernate state */
94 	UIC_LINK_BROKEN_STATE	= 3, /* Link is in broken state */
95 };
96 
97 #define ufshcd_is_link_off(hba) ((hba)->uic_link_state == UIC_LINK_OFF_STATE)
98 #define ufshcd_is_link_active(hba) ((hba)->uic_link_state == \
99 				    UIC_LINK_ACTIVE_STATE)
100 #define ufshcd_is_link_hibern8(hba) ((hba)->uic_link_state == \
101 				    UIC_LINK_HIBERN8_STATE)
102 #define ufshcd_is_link_broken(hba) ((hba)->uic_link_state == \
103 				   UIC_LINK_BROKEN_STATE)
104 #define ufshcd_set_link_off(hba) ((hba)->uic_link_state = UIC_LINK_OFF_STATE)
105 #define ufshcd_set_link_active(hba) ((hba)->uic_link_state = \
106 				    UIC_LINK_ACTIVE_STATE)
107 #define ufshcd_set_link_hibern8(hba) ((hba)->uic_link_state = \
108 				    UIC_LINK_HIBERN8_STATE)
109 #define ufshcd_set_link_broken(hba) ((hba)->uic_link_state = \
110 				    UIC_LINK_BROKEN_STATE)
111 
112 #define ufshcd_set_ufs_dev_active(h) \
113 	((h)->curr_dev_pwr_mode = UFS_ACTIVE_PWR_MODE)
114 #define ufshcd_set_ufs_dev_sleep(h) \
115 	((h)->curr_dev_pwr_mode = UFS_SLEEP_PWR_MODE)
116 #define ufshcd_set_ufs_dev_poweroff(h) \
117 	((h)->curr_dev_pwr_mode = UFS_POWERDOWN_PWR_MODE)
118 #define ufshcd_set_ufs_dev_deepsleep(h) \
119 	((h)->curr_dev_pwr_mode = UFS_DEEPSLEEP_PWR_MODE)
120 #define ufshcd_is_ufs_dev_active(h) \
121 	((h)->curr_dev_pwr_mode == UFS_ACTIVE_PWR_MODE)
122 #define ufshcd_is_ufs_dev_sleep(h) \
123 	((h)->curr_dev_pwr_mode == UFS_SLEEP_PWR_MODE)
124 #define ufshcd_is_ufs_dev_poweroff(h) \
125 	((h)->curr_dev_pwr_mode == UFS_POWERDOWN_PWR_MODE)
126 #define ufshcd_is_ufs_dev_deepsleep(h) \
127 	((h)->curr_dev_pwr_mode == UFS_DEEPSLEEP_PWR_MODE)
128 
129 /*
130  * UFS Power management levels.
131  * Each level is in increasing order of power savings, except DeepSleep
132  * which is lower than PowerDown with power on but not PowerDown with
133  * power off.
134  */
135 enum ufs_pm_level {
136 	UFS_PM_LVL_0,
137 	UFS_PM_LVL_1,
138 	UFS_PM_LVL_2,
139 	UFS_PM_LVL_3,
140 	UFS_PM_LVL_4,
141 	UFS_PM_LVL_5,
142 	UFS_PM_LVL_6,
143 	UFS_PM_LVL_MAX
144 };
145 
146 struct ufs_pm_lvl_states {
147 	enum ufs_dev_pwr_mode dev_state;
148 	enum uic_link_state link_state;
149 };
150 
151 /**
152  * struct ufshcd_lrb - local reference block
153  * @utr_descriptor_ptr: UTRD address of the command
154  * @ucd_req_ptr: UCD address of the command
155  * @ucd_rsp_ptr: Response UPIU address for this command
156  * @ucd_prdt_ptr: PRDT address of the command
157  * @utrd_dma_addr: UTRD dma address for debug
158  * @ucd_prdt_dma_addr: PRDT dma address for debug
159  * @ucd_rsp_dma_addr: UPIU response dma address for debug
160  * @ucd_req_dma_addr: UPIU request dma address for debug
161  * @cmd: pointer to SCSI command
162  * @scsi_status: SCSI status of the command
163  * @command_type: SCSI, UFS, Query.
164  * @task_tag: Task tag of the command
165  * @lun: LUN of the command
166  * @intr_cmd: Interrupt command (doesn't participate in interrupt aggregation)
167  * @issue_time_stamp: time stamp for debug purposes (CLOCK_MONOTONIC)
168  * @issue_time_stamp_local_clock: time stamp for debug purposes (local_clock)
169  * @compl_time_stamp: time stamp for statistics (CLOCK_MONOTONIC)
170  * @compl_time_stamp_local_clock: time stamp for debug purposes (local_clock)
171  * @crypto_key_slot: the key slot to use for inline crypto (-1 if none)
172  * @data_unit_num: the data unit number for the first block for inline crypto
173  * @req_abort_skip: skip request abort task flag
174  */
175 struct ufshcd_lrb {
176 	struct utp_transfer_req_desc *utr_descriptor_ptr;
177 	struct utp_upiu_req *ucd_req_ptr;
178 	struct utp_upiu_rsp *ucd_rsp_ptr;
179 	struct ufshcd_sg_entry *ucd_prdt_ptr;
180 
181 	dma_addr_t utrd_dma_addr;
182 	dma_addr_t ucd_req_dma_addr;
183 	dma_addr_t ucd_rsp_dma_addr;
184 	dma_addr_t ucd_prdt_dma_addr;
185 
186 	struct scsi_cmnd *cmd;
187 	int scsi_status;
188 
189 	int command_type;
190 	int task_tag;
191 	u8 lun; /* UPIU LUN id field is only 8-bit wide */
192 	bool intr_cmd;
193 	ktime_t issue_time_stamp;
194 	u64 issue_time_stamp_local_clock;
195 	ktime_t compl_time_stamp;
196 	u64 compl_time_stamp_local_clock;
197 #ifdef CONFIG_SCSI_UFS_CRYPTO
198 	int crypto_key_slot;
199 	u64 data_unit_num;
200 #endif
201 
202 	bool req_abort_skip;
203 };
204 
205 /**
206  * struct ufs_query_req - parameters for building a query request
207  * @query_func: UPIU header query function
208  * @upiu_req: the query request data
209  */
210 struct ufs_query_req {
211 	u8 query_func;
212 	struct utp_upiu_query upiu_req;
213 };
214 
215 /**
216  * struct ufs_query_resp - UPIU QUERY
217  * @response: device response code
218  * @upiu_res: query response data
219  */
220 struct ufs_query_res {
221 	struct utp_upiu_query upiu_res;
222 };
223 
224 /**
225  * struct ufs_query - holds relevant data structures for query request
226  * @request: request upiu and function
227  * @descriptor: buffer for sending/receiving descriptor
228  * @response: response upiu and response
229  */
230 struct ufs_query {
231 	struct ufs_query_req request;
232 	u8 *descriptor;
233 	struct ufs_query_res response;
234 };
235 
236 /**
237  * struct ufs_dev_cmd - all assosiated fields with device management commands
238  * @type: device management command type - Query, NOP OUT
239  * @lock: lock to allow one command at a time
240  * @complete: internal commands completion
241  * @query: Device management query information
242  */
243 struct ufs_dev_cmd {
244 	enum dev_cmd_type type;
245 	struct mutex lock;
246 	struct completion *complete;
247 	struct ufs_query query;
248 };
249 
250 /**
251  * struct ufs_clk_info - UFS clock related info
252  * @list: list headed by hba->clk_list_head
253  * @clk: clock node
254  * @name: clock name
255  * @max_freq: maximum frequency supported by the clock
256  * @min_freq: min frequency that can be used for clock scaling
257  * @curr_freq: indicates the current frequency that it is set to
258  * @keep_link_active: indicates that the clk should not be disabled if
259  *		      link is active
260  * @enabled: variable to check against multiple enable/disable
261  */
262 struct ufs_clk_info {
263 	struct list_head list;
264 	struct clk *clk;
265 	const char *name;
266 	u32 max_freq;
267 	u32 min_freq;
268 	u32 curr_freq;
269 	bool keep_link_active;
270 	bool enabled;
271 };
272 
273 enum ufs_notify_change_status {
274 	PRE_CHANGE,
275 	POST_CHANGE,
276 };
277 
278 struct ufs_pa_layer_attr {
279 	u32 gear_rx;
280 	u32 gear_tx;
281 	u32 lane_rx;
282 	u32 lane_tx;
283 	u32 pwr_rx;
284 	u32 pwr_tx;
285 	u32 hs_rate;
286 };
287 
288 struct ufs_pwr_mode_info {
289 	bool is_valid;
290 	struct ufs_pa_layer_attr info;
291 };
292 
293 /**
294  * struct ufs_hba_variant_ops - variant specific callbacks
295  * @name: variant name
296  * @init: called when the driver is initialized
297  * @exit: called to cleanup everything done in init
298  * @get_ufs_hci_version: called to get UFS HCI version
299  * @clk_scale_notify: notifies that clks are scaled up/down
300  * @setup_clocks: called before touching any of the controller registers
301  * @hce_enable_notify: called before and after HCE enable bit is set to allow
302  *                     variant specific Uni-Pro initialization.
303  * @link_startup_notify: called before and after Link startup is carried out
304  *                       to allow variant specific Uni-Pro initialization.
305  * @pwr_change_notify: called before and after a power mode change
306  *			is carried out to allow vendor spesific capabilities
307  *			to be set.
308  * @setup_xfer_req: called before any transfer request is issued
309  *                  to set some things
310  * @setup_task_mgmt: called before any task management request is issued
311  *                  to set some things
312  * @hibern8_notify: called around hibern8 enter/exit
313  * @apply_dev_quirks: called to apply device specific quirks
314  * @fixup_dev_quirks: called to modify device specific quirks
315  * @suspend: called during host controller PM callback
316  * @resume: called during host controller PM callback
317  * @dbg_register_dump: used to dump controller debug information
318  * @phy_initialization: used to initialize phys
319  * @device_reset: called to issue a reset pulse on the UFS device
320  * @config_scaling_param: called to configure clock scaling parameters
321  * @program_key: program or evict an inline encryption key
322  * @event_notify: called to notify important events
323  * @reinit_notify: called to notify reinit of UFSHCD during max gear switch
324  * @mcq_config_resource: called to configure MCQ platform resources
325  * @get_hba_mac: called to get vendor specific mac value, mandatory for mcq mode
326  * @op_runtime_config: called to config Operation and runtime regs Pointers
327  * @get_outstanding_cqs: called to get outstanding completion queues
328  * @config_esi: called to config Event Specific Interrupt
329  */
330 struct ufs_hba_variant_ops {
331 	const char *name;
332 	int	(*init)(struct ufs_hba *);
333 	void    (*exit)(struct ufs_hba *);
334 	u32	(*get_ufs_hci_version)(struct ufs_hba *);
335 	int	(*clk_scale_notify)(struct ufs_hba *, bool,
336 				    enum ufs_notify_change_status);
337 	int	(*setup_clocks)(struct ufs_hba *, bool,
338 				enum ufs_notify_change_status);
339 	int	(*hce_enable_notify)(struct ufs_hba *,
340 				     enum ufs_notify_change_status);
341 	int	(*link_startup_notify)(struct ufs_hba *,
342 				       enum ufs_notify_change_status);
343 	int	(*pwr_change_notify)(struct ufs_hba *,
344 					enum ufs_notify_change_status status,
345 					struct ufs_pa_layer_attr *,
346 					struct ufs_pa_layer_attr *);
347 	void	(*setup_xfer_req)(struct ufs_hba *hba, int tag,
348 				  bool is_scsi_cmd);
349 	void	(*setup_task_mgmt)(struct ufs_hba *, int, u8);
350 	void    (*hibern8_notify)(struct ufs_hba *, enum uic_cmd_dme,
351 					enum ufs_notify_change_status);
352 	int	(*apply_dev_quirks)(struct ufs_hba *hba);
353 	void	(*fixup_dev_quirks)(struct ufs_hba *hba);
354 	int     (*suspend)(struct ufs_hba *, enum ufs_pm_op,
355 					enum ufs_notify_change_status);
356 	int     (*resume)(struct ufs_hba *, enum ufs_pm_op);
357 	void	(*dbg_register_dump)(struct ufs_hba *hba);
358 	int	(*phy_initialization)(struct ufs_hba *);
359 	int	(*device_reset)(struct ufs_hba *hba);
360 	void	(*config_scaling_param)(struct ufs_hba *hba,
361 				struct devfreq_dev_profile *profile,
362 				struct devfreq_simple_ondemand_data *data);
363 	int	(*program_key)(struct ufs_hba *hba,
364 			       const union ufs_crypto_cfg_entry *cfg, int slot);
365 	void	(*event_notify)(struct ufs_hba *hba,
366 				enum ufs_event_type evt, void *data);
367 	void	(*reinit_notify)(struct ufs_hba *);
368 	int	(*mcq_config_resource)(struct ufs_hba *hba);
369 	int	(*get_hba_mac)(struct ufs_hba *hba);
370 	int	(*op_runtime_config)(struct ufs_hba *hba);
371 	int	(*get_outstanding_cqs)(struct ufs_hba *hba,
372 				       unsigned long *ocqs);
373 	int	(*config_esi)(struct ufs_hba *hba);
374 };
375 
376 /* clock gating state  */
377 enum clk_gating_state {
378 	CLKS_OFF,
379 	CLKS_ON,
380 	REQ_CLKS_OFF,
381 	REQ_CLKS_ON,
382 };
383 
384 /**
385  * struct ufs_clk_gating - UFS clock gating related info
386  * @gate_work: worker to turn off clocks after some delay as specified in
387  * delay_ms
388  * @ungate_work: worker to turn on clocks that will be used in case of
389  * interrupt context
390  * @state: the current clocks state
391  * @delay_ms: gating delay in ms
392  * @is_suspended: clk gating is suspended when set to 1 which can be used
393  * during suspend/resume
394  * @delay_attr: sysfs attribute to control delay_attr
395  * @enable_attr: sysfs attribute to enable/disable clock gating
396  * @is_enabled: Indicates the current status of clock gating
397  * @is_initialized: Indicates whether clock gating is initialized or not
398  * @active_reqs: number of requests that are pending and should be waited for
399  * completion before gating clocks.
400  * @clk_gating_workq: workqueue for clock gating work.
401  */
402 struct ufs_clk_gating {
403 	struct delayed_work gate_work;
404 	struct work_struct ungate_work;
405 	enum clk_gating_state state;
406 	unsigned long delay_ms;
407 	bool is_suspended;
408 	struct device_attribute delay_attr;
409 	struct device_attribute enable_attr;
410 	bool is_enabled;
411 	bool is_initialized;
412 	int active_reqs;
413 	struct workqueue_struct *clk_gating_workq;
414 };
415 
416 /**
417  * struct ufs_clk_scaling - UFS clock scaling related data
418  * @active_reqs: number of requests that are pending. If this is zero when
419  * devfreq ->target() function is called then schedule "suspend_work" to
420  * suspend devfreq.
421  * @tot_busy_t: Total busy time in current polling window
422  * @window_start_t: Start time (in jiffies) of the current polling window
423  * @busy_start_t: Start time of current busy period
424  * @enable_attr: sysfs attribute to enable/disable clock scaling
425  * @saved_pwr_info: UFS power mode may also be changed during scaling and this
426  * one keeps track of previous power mode.
427  * @workq: workqueue to schedule devfreq suspend/resume work
428  * @suspend_work: worker to suspend devfreq
429  * @resume_work: worker to resume devfreq
430  * @min_gear: lowest HS gear to scale down to
431  * @is_enabled: tracks if scaling is currently enabled or not, controlled by
432  *		clkscale_enable sysfs node
433  * @is_allowed: tracks if scaling is currently allowed or not, used to block
434  *		clock scaling which is not invoked from devfreq governor
435  * @is_initialized: Indicates whether clock scaling is initialized or not
436  * @is_busy_started: tracks if busy period has started or not
437  * @is_suspended: tracks if devfreq is suspended or not
438  */
439 struct ufs_clk_scaling {
440 	int active_reqs;
441 	unsigned long tot_busy_t;
442 	ktime_t window_start_t;
443 	ktime_t busy_start_t;
444 	struct device_attribute enable_attr;
445 	struct ufs_pa_layer_attr saved_pwr_info;
446 	struct workqueue_struct *workq;
447 	struct work_struct suspend_work;
448 	struct work_struct resume_work;
449 	u32 min_gear;
450 	bool is_enabled;
451 	bool is_allowed;
452 	bool is_initialized;
453 	bool is_busy_started;
454 	bool is_suspended;
455 };
456 
457 #define UFS_EVENT_HIST_LENGTH 8
458 /**
459  * struct ufs_event_hist - keeps history of errors
460  * @pos: index to indicate cyclic buffer position
461  * @val: cyclic buffer for registers value
462  * @tstamp: cyclic buffer for time stamp
463  * @cnt: error counter
464  */
465 struct ufs_event_hist {
466 	int pos;
467 	u32 val[UFS_EVENT_HIST_LENGTH];
468 	u64 tstamp[UFS_EVENT_HIST_LENGTH];
469 	unsigned long long cnt;
470 };
471 
472 /**
473  * struct ufs_stats - keeps usage/err statistics
474  * @last_intr_status: record the last interrupt status.
475  * @last_intr_ts: record the last interrupt timestamp.
476  * @hibern8_exit_cnt: Counter to keep track of number of exits,
477  *		reset this after link-startup.
478  * @last_hibern8_exit_tstamp: Set time after the hibern8 exit.
479  *		Clear after the first successful command completion.
480  * @event: array with event history.
481  */
482 struct ufs_stats {
483 	u32 last_intr_status;
484 	u64 last_intr_ts;
485 
486 	u32 hibern8_exit_cnt;
487 	u64 last_hibern8_exit_tstamp;
488 	struct ufs_event_hist event[UFS_EVT_CNT];
489 };
490 
491 /**
492  * enum ufshcd_state - UFS host controller state
493  * @UFSHCD_STATE_RESET: Link is not operational. Postpone SCSI command
494  *	processing.
495  * @UFSHCD_STATE_OPERATIONAL: The host controller is operational and can process
496  *	SCSI commands.
497  * @UFSHCD_STATE_EH_SCHEDULED_NON_FATAL: The error handler has been scheduled.
498  *	SCSI commands may be submitted to the controller.
499  * @UFSHCD_STATE_EH_SCHEDULED_FATAL: The error handler has been scheduled. Fail
500  *	newly submitted SCSI commands with error code DID_BAD_TARGET.
501  * @UFSHCD_STATE_ERROR: An unrecoverable error occurred, e.g. link recovery
502  *	failed. Fail all SCSI commands with error code DID_ERROR.
503  */
504 enum ufshcd_state {
505 	UFSHCD_STATE_RESET,
506 	UFSHCD_STATE_OPERATIONAL,
507 	UFSHCD_STATE_EH_SCHEDULED_NON_FATAL,
508 	UFSHCD_STATE_EH_SCHEDULED_FATAL,
509 	UFSHCD_STATE_ERROR,
510 };
511 
512 enum ufshcd_quirks {
513 	/* Interrupt aggregation support is broken */
514 	UFSHCD_QUIRK_BROKEN_INTR_AGGR			= 1 << 0,
515 
516 	/*
517 	 * delay before each dme command is required as the unipro
518 	 * layer has shown instabilities
519 	 */
520 	UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS		= 1 << 1,
521 
522 	/*
523 	 * If UFS host controller is having issue in processing LCC (Line
524 	 * Control Command) coming from device then enable this quirk.
525 	 * When this quirk is enabled, host controller driver should disable
526 	 * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
527 	 * attribute of device to 0).
528 	 */
529 	UFSHCD_QUIRK_BROKEN_LCC				= 1 << 2,
530 
531 	/*
532 	 * The attribute PA_RXHSUNTERMCAP specifies whether or not the
533 	 * inbound Link supports unterminated line in HS mode. Setting this
534 	 * attribute to 1 fixes moving to HS gear.
535 	 */
536 	UFSHCD_QUIRK_BROKEN_PA_RXHSUNTERMCAP		= 1 << 3,
537 
538 	/*
539 	 * This quirk needs to be enabled if the host controller only allows
540 	 * accessing the peer dme attributes in AUTO mode (FAST AUTO or
541 	 * SLOW AUTO).
542 	 */
543 	UFSHCD_QUIRK_DME_PEER_ACCESS_AUTO_MODE		= 1 << 4,
544 
545 	/*
546 	 * This quirk needs to be enabled if the host controller doesn't
547 	 * advertise the correct version in UFS_VER register. If this quirk
548 	 * is enabled, standard UFS host driver will call the vendor specific
549 	 * ops (get_ufs_hci_version) to get the correct version.
550 	 */
551 	UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION		= 1 << 5,
552 
553 	/*
554 	 * Clear handling for transfer/task request list is just opposite.
555 	 */
556 	UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR		= 1 << 6,
557 
558 	/*
559 	 * This quirk needs to be enabled if host controller doesn't allow
560 	 * that the interrupt aggregation timer and counter are reset by s/w.
561 	 */
562 	UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR		= 1 << 7,
563 
564 	/*
565 	 * This quirks needs to be enabled if host controller cannot be
566 	 * enabled via HCE register.
567 	 */
568 	UFSHCI_QUIRK_BROKEN_HCE				= 1 << 8,
569 
570 	/*
571 	 * This quirk needs to be enabled if the host controller regards
572 	 * resolution of the values of PRDTO and PRDTL in UTRD as byte.
573 	 */
574 	UFSHCD_QUIRK_PRDT_BYTE_GRAN			= 1 << 9,
575 
576 	/*
577 	 * This quirk needs to be enabled if the host controller reports
578 	 * OCS FATAL ERROR with device error through sense data
579 	 */
580 	UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR		= 1 << 10,
581 
582 	/*
583 	 * This quirk needs to be enabled if the host controller has
584 	 * auto-hibernate capability but it doesn't work.
585 	 */
586 	UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8		= 1 << 11,
587 
588 	/*
589 	 * This quirk needs to disable manual flush for write booster
590 	 */
591 	UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL		= 1 << 12,
592 
593 	/*
594 	 * This quirk needs to disable unipro timeout values
595 	 * before power mode change
596 	 */
597 	UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING = 1 << 13,
598 
599 	/*
600 	 * Align DMA SG entries on a 4 KiB boundary.
601 	 */
602 	UFSHCD_QUIRK_4KB_DMA_ALIGNMENT			= 1 << 14,
603 
604 	/*
605 	 * This quirk needs to be enabled if the host controller does not
606 	 * support UIC command
607 	 */
608 	UFSHCD_QUIRK_BROKEN_UIC_CMD			= 1 << 15,
609 
610 	/*
611 	 * This quirk needs to be enabled if the host controller cannot
612 	 * support physical host configuration.
613 	 */
614 	UFSHCD_QUIRK_SKIP_PH_CONFIGURATION		= 1 << 16,
615 
616 	/*
617 	 * This quirk needs to be enabled if the host controller has
618 	 * 64-bit addressing supported capability but it doesn't work.
619 	 */
620 	UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS		= 1 << 17,
621 
622 	/*
623 	 * This quirk needs to be enabled if the host controller has
624 	 * auto-hibernate capability but it's FASTAUTO only.
625 	 */
626 	UFSHCD_QUIRK_HIBERN_FASTAUTO			= 1 << 18,
627 
628 	/*
629 	 * This quirk needs to be enabled if the host controller needs
630 	 * to reinit the device after switching to maximum gear.
631 	 */
632 	UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH       = 1 << 19,
633 
634 	/*
635 	 * Some host raises interrupt (per queue) in addition to
636 	 * CQES (traditional) when ESI is disabled.
637 	 * Enable this quirk will disable CQES and use per queue interrupt.
638 	 */
639 	UFSHCD_QUIRK_MCQ_BROKEN_INTR			= 1 << 20,
640 
641 	/*
642 	 * Some host does not implement SQ Run Time Command (SQRTC) register
643 	 * thus need this quirk to skip related flow.
644 	 */
645 	UFSHCD_QUIRK_MCQ_BROKEN_RTC			= 1 << 21,
646 };
647 
648 enum ufshcd_caps {
649 	/* Allow dynamic clk gating */
650 	UFSHCD_CAP_CLK_GATING				= 1 << 0,
651 
652 	/* Allow hiberb8 with clk gating */
653 	UFSHCD_CAP_HIBERN8_WITH_CLK_GATING		= 1 << 1,
654 
655 	/* Allow dynamic clk scaling */
656 	UFSHCD_CAP_CLK_SCALING				= 1 << 2,
657 
658 	/* Allow auto bkops to enabled during runtime suspend */
659 	UFSHCD_CAP_AUTO_BKOPS_SUSPEND			= 1 << 3,
660 
661 	/*
662 	 * This capability allows host controller driver to use the UFS HCI's
663 	 * interrupt aggregation capability.
664 	 * CAUTION: Enabling this might reduce overall UFS throughput.
665 	 */
666 	UFSHCD_CAP_INTR_AGGR				= 1 << 4,
667 
668 	/*
669 	 * This capability allows the device auto-bkops to be always enabled
670 	 * except during suspend (both runtime and suspend).
671 	 * Enabling this capability means that device will always be allowed
672 	 * to do background operation when it's active but it might degrade
673 	 * the performance of ongoing read/write operations.
674 	 */
675 	UFSHCD_CAP_KEEP_AUTO_BKOPS_ENABLED_EXCEPT_SUSPEND = 1 << 5,
676 
677 	/*
678 	 * This capability allows host controller driver to automatically
679 	 * enable runtime power management by itself instead of waiting
680 	 * for userspace to control the power management.
681 	 */
682 	UFSHCD_CAP_RPM_AUTOSUSPEND			= 1 << 6,
683 
684 	/*
685 	 * This capability allows the host controller driver to turn-on
686 	 * WriteBooster, if the underlying device supports it and is
687 	 * provisioned to be used. This would increase the write performance.
688 	 */
689 	UFSHCD_CAP_WB_EN				= 1 << 7,
690 
691 	/*
692 	 * This capability allows the host controller driver to use the
693 	 * inline crypto engine, if it is present
694 	 */
695 	UFSHCD_CAP_CRYPTO				= 1 << 8,
696 
697 	/*
698 	 * This capability allows the controller regulators to be put into
699 	 * lpm mode aggressively during clock gating.
700 	 * This would increase power savings.
701 	 */
702 	UFSHCD_CAP_AGGR_POWER_COLLAPSE			= 1 << 9,
703 
704 	/*
705 	 * This capability allows the host controller driver to use DeepSleep,
706 	 * if it is supported by the UFS device. The host controller driver must
707 	 * support device hardware reset via the hba->device_reset() callback,
708 	 * in order to exit DeepSleep state.
709 	 */
710 	UFSHCD_CAP_DEEPSLEEP				= 1 << 10,
711 
712 	/*
713 	 * This capability allows the host controller driver to use temperature
714 	 * notification if it is supported by the UFS device.
715 	 */
716 	UFSHCD_CAP_TEMP_NOTIF				= 1 << 11,
717 
718 	/*
719 	 * Enable WriteBooster when scaling up the clock and disable
720 	 * WriteBooster when scaling the clock down.
721 	 */
722 	UFSHCD_CAP_WB_WITH_CLK_SCALING			= 1 << 12,
723 };
724 
725 struct ufs_hba_variant_params {
726 	struct devfreq_dev_profile devfreq_profile;
727 	struct devfreq_simple_ondemand_data ondemand_data;
728 	u16 hba_enable_delay_us;
729 	u32 wb_flush_threshold;
730 };
731 
732 struct ufs_hba_monitor {
733 	unsigned long chunk_size;
734 
735 	unsigned long nr_sec_rw[2];
736 	ktime_t total_busy[2];
737 
738 	unsigned long nr_req[2];
739 	/* latencies*/
740 	ktime_t lat_sum[2];
741 	ktime_t lat_max[2];
742 	ktime_t lat_min[2];
743 
744 	u32 nr_queued[2];
745 	ktime_t busy_start_ts[2];
746 
747 	ktime_t enabled_ts;
748 	bool enabled;
749 };
750 
751 /**
752  * struct ufshcd_res_info_t - MCQ related resource regions
753  *
754  * @name: resource name
755  * @resource: pointer to resource region
756  * @base: register base address
757  */
758 struct ufshcd_res_info {
759 	const char *name;
760 	struct resource *resource;
761 	void __iomem *base;
762 };
763 
764 enum ufshcd_res {
765 	RES_UFS,
766 	RES_MCQ,
767 	RES_MCQ_SQD,
768 	RES_MCQ_SQIS,
769 	RES_MCQ_CQD,
770 	RES_MCQ_CQIS,
771 	RES_MCQ_VS,
772 	RES_MAX,
773 };
774 
775 /**
776  * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers
777  *
778  * @offset: Doorbell Address Offset
779  * @stride: Steps proportional to queue [0...31]
780  * @base: base address
781  */
782 struct ufshcd_mcq_opr_info_t {
783 	unsigned long offset;
784 	unsigned long stride;
785 	void __iomem *base;
786 };
787 
788 enum ufshcd_mcq_opr {
789 	OPR_SQD,
790 	OPR_SQIS,
791 	OPR_CQD,
792 	OPR_CQIS,
793 	OPR_MAX,
794 };
795 
796 /**
797  * struct ufs_hba - per adapter private structure
798  * @mmio_base: UFSHCI base register address
799  * @ucdl_base_addr: UFS Command Descriptor base address
800  * @utrdl_base_addr: UTP Transfer Request Descriptor base address
801  * @utmrdl_base_addr: UTP Task Management Descriptor base address
802  * @ucdl_dma_addr: UFS Command Descriptor DMA address
803  * @utrdl_dma_addr: UTRDL DMA address
804  * @utmrdl_dma_addr: UTMRDL DMA address
805  * @host: Scsi_Host instance of the driver
806  * @dev: device handle
807  * @ufs_device_wlun: WLUN that controls the entire UFS device.
808  * @hwmon_device: device instance registered with the hwmon core.
809  * @curr_dev_pwr_mode: active UFS device power mode.
810  * @uic_link_state: active state of the link to the UFS device.
811  * @rpm_lvl: desired UFS power management level during runtime PM.
812  * @spm_lvl: desired UFS power management level during system PM.
813  * @pm_op_in_progress: whether or not a PM operation is in progress.
814  * @ahit: value of Auto-Hibernate Idle Timer register.
815  * @lrb: local reference block
816  * @outstanding_tasks: Bits representing outstanding task requests
817  * @outstanding_lock: Protects @outstanding_reqs.
818  * @outstanding_reqs: Bits representing outstanding transfer requests
819  * @capabilities: UFS Controller Capabilities
820  * @mcq_capabilities: UFS Multi Circular Queue capabilities
821  * @nutrs: Transfer Request Queue depth supported by controller
822  * @nutmrs: Task Management Queue depth supported by controller
823  * @reserved_slot: Used to submit device commands. Protected by @dev_cmd.lock.
824  * @ufs_version: UFS Version to which controller complies
825  * @vops: pointer to variant specific operations
826  * @vps: pointer to variant specific parameters
827  * @priv: pointer to variant specific private data
828  * @sg_entry_size: size of struct ufshcd_sg_entry (may include variant fields)
829  * @irq: Irq number of the controller
830  * @is_irq_enabled: whether or not the UFS controller interrupt is enabled.
831  * @dev_ref_clk_freq: reference clock frequency
832  * @quirks: bitmask with information about deviations from the UFSHCI standard.
833  * @dev_quirks: bitmask with information about deviations from the UFS standard.
834  * @tmf_tag_set: TMF tag set.
835  * @tmf_queue: Used to allocate TMF tags.
836  * @tmf_rqs: array with pointers to TMF requests while these are in progress.
837  * @active_uic_cmd: handle of active UIC command
838  * @uic_cmd_mutex: mutex for UIC command
839  * @uic_async_done: completion used during UIC processing
840  * @ufshcd_state: UFSHCD state
841  * @eh_flags: Error handling flags
842  * @intr_mask: Interrupt Mask Bits
843  * @ee_ctrl_mask: Exception event control mask
844  * @ee_drv_mask: Exception event mask for driver
845  * @ee_usr_mask: Exception event mask for user (set via debugfs)
846  * @ee_ctrl_mutex: Used to serialize exception event information.
847  * @is_powered: flag to check if HBA is powered
848  * @shutting_down: flag to check if shutdown has been invoked
849  * @host_sem: semaphore used to serialize concurrent contexts
850  * @eh_wq: Workqueue that eh_work works on
851  * @eh_work: Worker to handle UFS errors that require s/w attention
852  * @eeh_work: Worker to handle exception events
853  * @errors: HBA errors
854  * @uic_error: UFS interconnect layer error status
855  * @saved_err: sticky error mask
856  * @saved_uic_err: sticky UIC error mask
857  * @ufs_stats: various error counters
858  * @force_reset: flag to force eh_work perform a full reset
859  * @force_pmc: flag to force a power mode change
860  * @silence_err_logs: flag to silence error logs
861  * @dev_cmd: ufs device management command information
862  * @last_dme_cmd_tstamp: time stamp of the last completed DME command
863  * @nop_out_timeout: NOP OUT timeout value
864  * @dev_info: information about the UFS device
865  * @auto_bkops_enabled: to track whether bkops is enabled in device
866  * @vreg_info: UFS device voltage regulator information
867  * @clk_list_head: UFS host controller clocks list node head
868  * @req_abort_count: number of times ufshcd_abort() has been called
869  * @lanes_per_direction: number of lanes per data direction between the UFS
870  *	controller and the UFS device.
871  * @pwr_info: holds current power mode
872  * @max_pwr_info: keeps the device max valid pwm
873  * @clk_gating: information related to clock gating
874  * @caps: bitmask with information about UFS controller capabilities
875  * @devfreq: frequency scaling information owned by the devfreq core
876  * @clk_scaling: frequency scaling information owned by the UFS driver
877  * @system_suspending: system suspend has been started and system resume has
878  *	not yet finished.
879  * @is_sys_suspended: UFS device has been suspended because of system suspend
880  * @urgent_bkops_lvl: keeps track of urgent bkops level for device
881  * @is_urgent_bkops_lvl_checked: keeps track if the urgent bkops level for
882  *  device is known or not.
883  * @wb_mutex: used to serialize devfreq and sysfs write booster toggling
884  * @clk_scaling_lock: used to serialize device commands and clock scaling
885  * @desc_size: descriptor sizes reported by device
886  * @scsi_block_reqs_cnt: reference counting for scsi block requests
887  * @bsg_dev: struct device associated with the BSG queue
888  * @bsg_queue: BSG queue associated with the UFS controller
889  * @rpm_dev_flush_recheck_work: used to suspend from RPM (runtime power
890  *	management) after the UFS device has finished a WriteBooster buffer
891  *	flush or auto BKOP.
892  * @monitor: statistics about UFS commands
893  * @crypto_capabilities: Content of crypto capabilities register (0x100)
894  * @crypto_cap_array: Array of crypto capabilities
895  * @crypto_cfg_register: Start of the crypto cfg array
896  * @crypto_profile: the crypto profile of this hba (if applicable)
897  * @debugfs_root: UFS controller debugfs root directory
898  * @debugfs_ee_work: used to restore ee_ctrl_mask after a delay
899  * @debugfs_ee_rate_limit_ms: user configurable delay after which to restore
900  *	ee_ctrl_mask
901  * @luns_avail: number of regular and well known LUNs supported by the UFS
902  *	device
903  * @nr_hw_queues: number of hardware queues configured
904  * @nr_queues: number of Queues of different queue types
905  * @complete_put: whether or not to call ufshcd_rpm_put() from inside
906  *	ufshcd_resume_complete()
907  * @ext_iid_sup: is EXT_IID is supported by UFSHC
908  * @mcq_sup: is mcq supported by UFSHC
909  * @mcq_enabled: is mcq ready to accept requests
910  * @res: array of resource info of MCQ registers
911  * @mcq_base: Multi circular queue registers base address
912  * @uhq: array of supported hardware queues
913  * @dev_cmd_queue: Queue for issuing device management commands
914  */
915 struct ufs_hba {
916 	void __iomem *mmio_base;
917 
918 	/* Virtual memory reference */
919 	struct utp_transfer_cmd_desc *ucdl_base_addr;
920 	struct utp_transfer_req_desc *utrdl_base_addr;
921 	struct utp_task_req_desc *utmrdl_base_addr;
922 
923 	/* DMA memory reference */
924 	dma_addr_t ucdl_dma_addr;
925 	dma_addr_t utrdl_dma_addr;
926 	dma_addr_t utmrdl_dma_addr;
927 
928 	struct Scsi_Host *host;
929 	struct device *dev;
930 	struct scsi_device *ufs_device_wlun;
931 
932 #ifdef CONFIG_SCSI_UFS_HWMON
933 	struct device *hwmon_device;
934 #endif
935 
936 	enum ufs_dev_pwr_mode curr_dev_pwr_mode;
937 	enum uic_link_state uic_link_state;
938 	/* Desired UFS power management level during runtime PM */
939 	enum ufs_pm_level rpm_lvl;
940 	/* Desired UFS power management level during system PM */
941 	enum ufs_pm_level spm_lvl;
942 	int pm_op_in_progress;
943 
944 	/* Auto-Hibernate Idle Timer register value */
945 	u32 ahit;
946 
947 	struct ufshcd_lrb *lrb;
948 
949 	unsigned long outstanding_tasks;
950 	spinlock_t outstanding_lock;
951 	unsigned long outstanding_reqs;
952 
953 	u32 capabilities;
954 	int nutrs;
955 	u32 mcq_capabilities;
956 	int nutmrs;
957 	u32 reserved_slot;
958 	u32 ufs_version;
959 	const struct ufs_hba_variant_ops *vops;
960 	struct ufs_hba_variant_params *vps;
961 	void *priv;
962 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
963 	size_t sg_entry_size;
964 #endif
965 	unsigned int irq;
966 	bool is_irq_enabled;
967 	enum ufs_ref_clk_freq dev_ref_clk_freq;
968 
969 	unsigned int quirks;	/* Deviations from standard UFSHCI spec. */
970 
971 	/* Device deviations from standard UFS device spec. */
972 	unsigned int dev_quirks;
973 
974 	struct blk_mq_tag_set tmf_tag_set;
975 	struct request_queue *tmf_queue;
976 	struct request **tmf_rqs;
977 
978 	struct uic_command *active_uic_cmd;
979 	struct mutex uic_cmd_mutex;
980 	struct completion *uic_async_done;
981 
982 	enum ufshcd_state ufshcd_state;
983 	u32 eh_flags;
984 	u32 intr_mask;
985 	u16 ee_ctrl_mask;
986 	u16 ee_drv_mask;
987 	u16 ee_usr_mask;
988 	struct mutex ee_ctrl_mutex;
989 	bool is_powered;
990 	bool shutting_down;
991 	struct semaphore host_sem;
992 
993 	/* Work Queues */
994 	struct workqueue_struct *eh_wq;
995 	struct work_struct eh_work;
996 	struct work_struct eeh_work;
997 
998 	/* HBA Errors */
999 	u32 errors;
1000 	u32 uic_error;
1001 	u32 saved_err;
1002 	u32 saved_uic_err;
1003 	struct ufs_stats ufs_stats;
1004 	bool force_reset;
1005 	bool force_pmc;
1006 	bool silence_err_logs;
1007 
1008 	/* Device management request data */
1009 	struct ufs_dev_cmd dev_cmd;
1010 	ktime_t last_dme_cmd_tstamp;
1011 	int nop_out_timeout;
1012 
1013 	/* Keeps information of the UFS device connected to this host */
1014 	struct ufs_dev_info dev_info;
1015 	bool auto_bkops_enabled;
1016 	struct ufs_vreg_info vreg_info;
1017 	struct list_head clk_list_head;
1018 
1019 	/* Number of requests aborts */
1020 	int req_abort_count;
1021 
1022 	/* Number of lanes available (1 or 2) for Rx/Tx */
1023 	u32 lanes_per_direction;
1024 	struct ufs_pa_layer_attr pwr_info;
1025 	struct ufs_pwr_mode_info max_pwr_info;
1026 
1027 	struct ufs_clk_gating clk_gating;
1028 	/* Control to enable/disable host capabilities */
1029 	u32 caps;
1030 
1031 	struct devfreq *devfreq;
1032 	struct ufs_clk_scaling clk_scaling;
1033 	bool system_suspending;
1034 	bool is_sys_suspended;
1035 
1036 	enum bkops_status urgent_bkops_lvl;
1037 	bool is_urgent_bkops_lvl_checked;
1038 
1039 	struct mutex wb_mutex;
1040 	struct rw_semaphore clk_scaling_lock;
1041 	atomic_t scsi_block_reqs_cnt;
1042 
1043 	struct device		bsg_dev;
1044 	struct request_queue	*bsg_queue;
1045 	struct delayed_work rpm_dev_flush_recheck_work;
1046 
1047 	struct ufs_hba_monitor	monitor;
1048 
1049 #ifdef CONFIG_SCSI_UFS_CRYPTO
1050 	union ufs_crypto_capabilities crypto_capabilities;
1051 	union ufs_crypto_cap_entry *crypto_cap_array;
1052 	u32 crypto_cfg_register;
1053 	struct blk_crypto_profile crypto_profile;
1054 #endif
1055 #ifdef CONFIG_DEBUG_FS
1056 	struct dentry *debugfs_root;
1057 	struct delayed_work debugfs_ee_work;
1058 	u32 debugfs_ee_rate_limit_ms;
1059 #endif
1060 	u32 luns_avail;
1061 	unsigned int nr_hw_queues;
1062 	unsigned int nr_queues[HCTX_MAX_TYPES];
1063 	bool complete_put;
1064 	bool ext_iid_sup;
1065 	bool scsi_host_added;
1066 	bool mcq_sup;
1067 	bool lsdb_sup;
1068 	bool mcq_enabled;
1069 	struct ufshcd_res_info res[RES_MAX];
1070 	void __iomem *mcq_base;
1071 	struct ufs_hw_queue *uhq;
1072 	struct ufs_hw_queue *dev_cmd_queue;
1073 	struct ufshcd_mcq_opr_info_t mcq_opr[OPR_MAX];
1074 };
1075 
1076 /**
1077  * struct ufs_hw_queue - per hardware queue structure
1078  * @mcq_sq_head: base address of submission queue head pointer
1079  * @mcq_sq_tail: base address of submission queue tail pointer
1080  * @mcq_cq_head: base address of completion queue head pointer
1081  * @mcq_cq_tail: base address of completion queue tail pointer
1082  * @sqe_base_addr: submission queue entry base address
1083  * @sqe_dma_addr: submission queue dma address
1084  * @cqe_base_addr: completion queue base address
1085  * @cqe_dma_addr: completion queue dma address
1086  * @max_entries: max number of slots in this hardware queue
1087  * @id: hardware queue ID
1088  * @sq_tp_slot: current slot to which SQ tail pointer is pointing
1089  * @sq_lock: serialize submission queue access
1090  * @cq_tail_slot: current slot to which CQ tail pointer is pointing
1091  * @cq_head_slot: current slot to which CQ head pointer is pointing
1092  * @cq_lock: Synchronize between multiple polling instances
1093  * @sq_mutex: prevent submission queue concurrent access
1094  */
1095 struct ufs_hw_queue {
1096 	void __iomem *mcq_sq_head;
1097 	void __iomem *mcq_sq_tail;
1098 	void __iomem *mcq_cq_head;
1099 	void __iomem *mcq_cq_tail;
1100 
1101 	struct utp_transfer_req_desc *sqe_base_addr;
1102 	dma_addr_t sqe_dma_addr;
1103 	struct cq_entry *cqe_base_addr;
1104 	dma_addr_t cqe_dma_addr;
1105 	u32 max_entries;
1106 	u32 id;
1107 	u32 sq_tail_slot;
1108 	spinlock_t sq_lock;
1109 	u32 cq_tail_slot;
1110 	u32 cq_head_slot;
1111 	spinlock_t cq_lock;
1112 	/* prevent concurrent access to submission queue */
1113 	struct mutex sq_mutex;
1114 };
1115 
is_mcq_enabled(struct ufs_hba * hba)1116 static inline bool is_mcq_enabled(struct ufs_hba *hba)
1117 {
1118 	return hba->mcq_enabled;
1119 }
1120 
ufshcd_mcq_opr_offset(struct ufs_hba * hba,enum ufshcd_mcq_opr opr,int idx)1121 static inline unsigned int ufshcd_mcq_opr_offset(struct ufs_hba *hba,
1122 		enum ufshcd_mcq_opr opr, int idx)
1123 {
1124 	return hba->mcq_opr[opr].offset + hba->mcq_opr[opr].stride * idx;
1125 }
1126 
1127 #ifdef CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE
ufshcd_sg_entry_size(const struct ufs_hba * hba)1128 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1129 {
1130 	return hba->sg_entry_size;
1131 }
1132 
ufshcd_set_sg_entry_size(struct ufs_hba * hba,size_t sg_entry_size)1133 static inline void ufshcd_set_sg_entry_size(struct ufs_hba *hba, size_t sg_entry_size)
1134 {
1135 	WARN_ON_ONCE(sg_entry_size < sizeof(struct ufshcd_sg_entry));
1136 	hba->sg_entry_size = sg_entry_size;
1137 }
1138 #else
ufshcd_sg_entry_size(const struct ufs_hba * hba)1139 static inline size_t ufshcd_sg_entry_size(const struct ufs_hba *hba)
1140 {
1141 	return sizeof(struct ufshcd_sg_entry);
1142 }
1143 
1144 #define ufshcd_set_sg_entry_size(hba, sg_entry_size)                   \
1145 	({ (void)(hba); BUILD_BUG_ON(sg_entry_size != sizeof(struct ufshcd_sg_entry)); })
1146 #endif
1147 
ufshcd_get_ucd_size(const struct ufs_hba * hba)1148 static inline size_t ufshcd_get_ucd_size(const struct ufs_hba *hba)
1149 {
1150 	return sizeof(struct utp_transfer_cmd_desc) + SG_ALL * ufshcd_sg_entry_size(hba);
1151 }
1152 
1153 /* Returns true if clocks can be gated. Otherwise false */
ufshcd_is_clkgating_allowed(struct ufs_hba * hba)1154 static inline bool ufshcd_is_clkgating_allowed(struct ufs_hba *hba)
1155 {
1156 	return hba->caps & UFSHCD_CAP_CLK_GATING;
1157 }
ufshcd_can_hibern8_during_gating(struct ufs_hba * hba)1158 static inline bool ufshcd_can_hibern8_during_gating(struct ufs_hba *hba)
1159 {
1160 	return hba->caps & UFSHCD_CAP_HIBERN8_WITH_CLK_GATING;
1161 }
ufshcd_is_clkscaling_supported(struct ufs_hba * hba)1162 static inline int ufshcd_is_clkscaling_supported(struct ufs_hba *hba)
1163 {
1164 	return hba->caps & UFSHCD_CAP_CLK_SCALING;
1165 }
ufshcd_can_autobkops_during_suspend(struct ufs_hba * hba)1166 static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
1167 {
1168 	return hba->caps & UFSHCD_CAP_AUTO_BKOPS_SUSPEND;
1169 }
ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba * hba)1170 static inline bool ufshcd_is_rpm_autosuspend_allowed(struct ufs_hba *hba)
1171 {
1172 	return hba->caps & UFSHCD_CAP_RPM_AUTOSUSPEND;
1173 }
1174 
ufshcd_is_intr_aggr_allowed(struct ufs_hba * hba)1175 static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
1176 {
1177 	return (hba->caps & UFSHCD_CAP_INTR_AGGR) &&
1178 		!(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR);
1179 }
1180 
ufshcd_can_aggressive_pc(struct ufs_hba * hba)1181 static inline bool ufshcd_can_aggressive_pc(struct ufs_hba *hba)
1182 {
1183 	return !!(ufshcd_is_link_hibern8(hba) &&
1184 		  (hba->caps & UFSHCD_CAP_AGGR_POWER_COLLAPSE));
1185 }
1186 
ufshcd_is_auto_hibern8_supported(struct ufs_hba * hba)1187 static inline bool ufshcd_is_auto_hibern8_supported(struct ufs_hba *hba)
1188 {
1189 	return (hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT) &&
1190 		!(hba->quirks & UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8);
1191 }
1192 
ufshcd_is_auto_hibern8_enabled(struct ufs_hba * hba)1193 static inline bool ufshcd_is_auto_hibern8_enabled(struct ufs_hba *hba)
1194 {
1195 	return FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK, hba->ahit);
1196 }
1197 
ufshcd_is_wb_allowed(struct ufs_hba * hba)1198 static inline bool ufshcd_is_wb_allowed(struct ufs_hba *hba)
1199 {
1200 	return hba->caps & UFSHCD_CAP_WB_EN;
1201 }
1202 
ufshcd_enable_wb_if_scaling_up(struct ufs_hba * hba)1203 static inline bool ufshcd_enable_wb_if_scaling_up(struct ufs_hba *hba)
1204 {
1205 	return hba->caps & UFSHCD_CAP_WB_WITH_CLK_SCALING;
1206 }
1207 
1208 #define ufsmcq_writel(hba, val, reg)	\
1209 	writel((val), (hba)->mcq_base + (reg))
1210 #define ufsmcq_readl(hba, reg)	\
1211 	readl((hba)->mcq_base + (reg))
1212 
1213 #define ufsmcq_writelx(hba, val, reg)	\
1214 	writel_relaxed((val), (hba)->mcq_base + (reg))
1215 #define ufsmcq_readlx(hba, reg)	\
1216 	readl_relaxed((hba)->mcq_base + (reg))
1217 
1218 #define ufshcd_writel(hba, val, reg)	\
1219 	writel((val), (hba)->mmio_base + (reg))
1220 #define ufshcd_readl(hba, reg)	\
1221 	readl((hba)->mmio_base + (reg))
1222 
1223 /**
1224  * ufshcd_rmwl - perform read/modify/write for a controller register
1225  * @hba: per adapter instance
1226  * @mask: mask to apply on read value
1227  * @val: actual value to write
1228  * @reg: register address
1229  */
ufshcd_rmwl(struct ufs_hba * hba,u32 mask,u32 val,u32 reg)1230 static inline void ufshcd_rmwl(struct ufs_hba *hba, u32 mask, u32 val, u32 reg)
1231 {
1232 	u32 tmp;
1233 
1234 	tmp = ufshcd_readl(hba, reg);
1235 	tmp &= ~mask;
1236 	tmp |= (val & mask);
1237 	ufshcd_writel(hba, tmp, reg);
1238 }
1239 
1240 int ufshcd_alloc_host(struct device *, struct ufs_hba **);
1241 void ufshcd_dealloc_host(struct ufs_hba *);
1242 int ufshcd_hba_enable(struct ufs_hba *hba);
1243 int ufshcd_init(struct ufs_hba *, void __iomem *, unsigned int);
1244 int ufshcd_link_recovery(struct ufs_hba *hba);
1245 int ufshcd_make_hba_operational(struct ufs_hba *hba);
1246 void ufshcd_remove(struct ufs_hba *);
1247 int ufshcd_uic_hibern8_enter(struct ufs_hba *hba);
1248 int ufshcd_uic_hibern8_exit(struct ufs_hba *hba);
1249 void ufshcd_delay_us(unsigned long us, unsigned long tolerance);
1250 void ufshcd_parse_dev_ref_clk_freq(struct ufs_hba *hba, struct clk *refclk);
1251 void ufshcd_update_evt_hist(struct ufs_hba *hba, u32 id, u32 val);
1252 void ufshcd_hba_stop(struct ufs_hba *hba);
1253 void ufshcd_schedule_eh_work(struct ufs_hba *hba);
1254 void ufshcd_mcq_config_mac(struct ufs_hba *hba, u32 max_active_cmds);
1255 u32 ufshcd_mcq_read_cqis(struct ufs_hba *hba, int i);
1256 void ufshcd_mcq_write_cqis(struct ufs_hba *hba, u32 val, int i);
1257 unsigned long ufshcd_mcq_poll_cqe_lock(struct ufs_hba *hba,
1258 					 struct ufs_hw_queue *hwq);
1259 void ufshcd_mcq_make_queues_operational(struct ufs_hba *hba);
1260 void ufshcd_mcq_enable_esi(struct ufs_hba *hba);
1261 void ufshcd_mcq_config_esi(struct ufs_hba *hba, struct msi_msg *msg);
1262 
1263 /**
1264  * ufshcd_set_variant - set variant specific data to the hba
1265  * @hba: per adapter instance
1266  * @variant: pointer to variant specific data
1267  */
ufshcd_set_variant(struct ufs_hba * hba,void * variant)1268 static inline void ufshcd_set_variant(struct ufs_hba *hba, void *variant)
1269 {
1270 	BUG_ON(!hba);
1271 	hba->priv = variant;
1272 }
1273 
1274 /**
1275  * ufshcd_get_variant - get variant specific data from the hba
1276  * @hba: per adapter instance
1277  */
ufshcd_get_variant(struct ufs_hba * hba)1278 static inline void *ufshcd_get_variant(struct ufs_hba *hba)
1279 {
1280 	BUG_ON(!hba);
1281 	return hba->priv;
1282 }
1283 
1284 #ifdef CONFIG_PM
1285 extern int ufshcd_runtime_suspend(struct device *dev);
1286 extern int ufshcd_runtime_resume(struct device *dev);
1287 #endif
1288 #ifdef CONFIG_PM_SLEEP
1289 extern int ufshcd_system_suspend(struct device *dev);
1290 extern int ufshcd_system_resume(struct device *dev);
1291 extern int ufshcd_system_freeze(struct device *dev);
1292 extern int ufshcd_system_thaw(struct device *dev);
1293 extern int ufshcd_system_restore(struct device *dev);
1294 #endif
1295 
1296 extern int ufshcd_dme_configure_adapt(struct ufs_hba *hba,
1297 				      int agreed_gear,
1298 				      int adapt_val);
1299 extern int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
1300 			       u8 attr_set, u32 mib_val, u8 peer);
1301 extern int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
1302 			       u32 *mib_val, u8 peer);
1303 extern int ufshcd_config_pwr_mode(struct ufs_hba *hba,
1304 			struct ufs_pa_layer_attr *desired_pwr_mode);
1305 extern int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode);
1306 
1307 /* UIC command interfaces for DME primitives */
1308 #define DME_LOCAL	0
1309 #define DME_PEER	1
1310 #define ATTR_SET_NOR	0	/* NORMAL */
1311 #define ATTR_SET_ST	1	/* STATIC */
1312 
ufshcd_dme_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1313 static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
1314 				 u32 mib_val)
1315 {
1316 	return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1317 				   mib_val, DME_LOCAL);
1318 }
1319 
ufshcd_dme_st_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1320 static inline int ufshcd_dme_st_set(struct ufs_hba *hba, u32 attr_sel,
1321 				    u32 mib_val)
1322 {
1323 	return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1324 				   mib_val, DME_LOCAL);
1325 }
1326 
ufshcd_dme_peer_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1327 static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
1328 				      u32 mib_val)
1329 {
1330 	return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
1331 				   mib_val, DME_PEER);
1332 }
1333 
ufshcd_dme_peer_st_set(struct ufs_hba * hba,u32 attr_sel,u32 mib_val)1334 static inline int ufshcd_dme_peer_st_set(struct ufs_hba *hba, u32 attr_sel,
1335 					 u32 mib_val)
1336 {
1337 	return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_ST,
1338 				   mib_val, DME_PEER);
1339 }
1340 
ufshcd_dme_get(struct ufs_hba * hba,u32 attr_sel,u32 * mib_val)1341 static inline int ufshcd_dme_get(struct ufs_hba *hba,
1342 				 u32 attr_sel, u32 *mib_val)
1343 {
1344 	return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
1345 }
1346 
ufshcd_dme_peer_get(struct ufs_hba * hba,u32 attr_sel,u32 * mib_val)1347 static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
1348 				      u32 attr_sel, u32 *mib_val)
1349 {
1350 	return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
1351 }
1352 
ufshcd_is_hs_mode(struct ufs_pa_layer_attr * pwr_info)1353 static inline bool ufshcd_is_hs_mode(struct ufs_pa_layer_attr *pwr_info)
1354 {
1355 	return (pwr_info->pwr_rx == FAST_MODE ||
1356 		pwr_info->pwr_rx == FASTAUTO_MODE) &&
1357 		(pwr_info->pwr_tx == FAST_MODE ||
1358 		pwr_info->pwr_tx == FASTAUTO_MODE);
1359 }
1360 
ufshcd_disable_host_tx_lcc(struct ufs_hba * hba)1361 static inline int ufshcd_disable_host_tx_lcc(struct ufs_hba *hba)
1362 {
1363 	return ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0);
1364 }
1365 
1366 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba);
1367 void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
1368 void ufshcd_fixup_dev_quirks(struct ufs_hba *hba,
1369 			     const struct ufs_dev_quirk *fixups);
1370 #define SD_ASCII_STD true
1371 #define SD_RAW false
1372 int ufshcd_read_string_desc(struct ufs_hba *hba, u8 desc_index,
1373 			    u8 **buf, bool ascii);
1374 
1375 void ufshcd_hold(struct ufs_hba *hba);
1376 void ufshcd_release(struct ufs_hba *hba);
1377 
1378 void ufshcd_clkgate_delay_set(struct device *dev, unsigned long value);
1379 
1380 u32 ufshcd_get_local_unipro_ver(struct ufs_hba *hba);
1381 
1382 int ufshcd_get_vreg(struct device *dev, struct ufs_vreg *vreg);
1383 
1384 int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd);
1385 
1386 int ufshcd_advanced_rpmb_req_handler(struct ufs_hba *hba, struct utp_upiu_req *req_upiu,
1387 				     struct utp_upiu_req *rsp_upiu, struct ufs_ehs *ehs_req,
1388 				     struct ufs_ehs *ehs_rsp, int sg_cnt,
1389 				     struct scatterlist *sg_list, enum dma_data_direction dir);
1390 int ufshcd_wb_toggle(struct ufs_hba *hba, bool enable);
1391 int ufshcd_wb_toggle_buf_flush(struct ufs_hba *hba, bool enable);
1392 int ufshcd_suspend_prepare(struct device *dev);
1393 int __ufshcd_suspend_prepare(struct device *dev, bool rpm_ok_for_spm);
1394 void ufshcd_resume_complete(struct device *dev);
1395 bool ufshcd_is_hba_active(struct ufs_hba *hba);
1396 
1397 /* Wrapper functions for safely calling variant operations */
ufshcd_vops_init(struct ufs_hba * hba)1398 static inline int ufshcd_vops_init(struct ufs_hba *hba)
1399 {
1400 	if (hba->vops && hba->vops->init)
1401 		return hba->vops->init(hba);
1402 
1403 	return 0;
1404 }
1405 
ufshcd_vops_phy_initialization(struct ufs_hba * hba)1406 static inline int ufshcd_vops_phy_initialization(struct ufs_hba *hba)
1407 {
1408 	if (hba->vops && hba->vops->phy_initialization)
1409 		return hba->vops->phy_initialization(hba);
1410 
1411 	return 0;
1412 }
1413 
1414 extern const struct ufs_pm_lvl_states ufs_pm_lvl_states[];
1415 
1416 int ufshcd_dump_regs(struct ufs_hba *hba, size_t offset, size_t len,
1417 		     const char *prefix);
1418 
1419 int __ufshcd_write_ee_control(struct ufs_hba *hba, u32 ee_ctrl_mask);
1420 int ufshcd_write_ee_control(struct ufs_hba *hba);
1421 int ufshcd_update_ee_control(struct ufs_hba *hba, u16 *mask,
1422 			     const u16 *other_mask, u16 set, u16 clr);
1423 
1424 #endif /* End of Header */
1425