Home
last modified time | relevance | path

Searched defs:inst_idx (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c80 static int vcn_v4_0_3_fw_shared_init(struct amdgpu_device *adev, int inst_idx) in vcn_v4_0_3_fw_shared_init()
344 static void vcn_v4_0_3_mc_resume(struct amdgpu_device *adev, int inst_idx) in vcn_v4_0_3_mc_resume()
419 static void vcn_v4_0_3_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v4_0_3_mc_resume_dpg_mode()
532 static void vcn_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) in vcn_v4_0_3_disable_clock_gating()
628 int inst_idx, uint8_t indirect) in vcn_v4_0_3_disable_clock_gating_dpg_mode()
676 static void vcn_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) in vcn_v4_0_3_enable_clock_gating()
728 static int vcn_v4_0_3_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v4_0_3_start_dpg_mode()
1233 static int vcn_v4_0_3_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) in vcn_v4_0_3_stop_dpg_mode()
1352 static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, in vcn_v4_0_3_pause_dpg_mode()
1762 int inst_idx, bool indirect) in vcn_v4_0_3_enable_ras()
H A Dvcn_v2_5.c469 static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v2_5_mc_resume_dpg_mode()
683 uint8_t sram_sel, int inst_idx, uint8_t indirect) in vcn_v2_5_clock_gating_dpg_mode()
792 static void vcn_v2_6_enable_ras(struct amdgpu_device *adev, int inst_idx, in vcn_v2_6_enable_ras()
819 static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v2_5_start_dpg_mode()
1352 static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) in vcn_v2_5_stop_dpg_mode()
1449 int inst_idx, struct dpg_pause_state *new_state) in vcn_v2_5_pause_dpg_mode()
H A Dvcn_v4_0.c436 static void vcn_v4_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v4_0_mc_resume_dpg_mode()
776 int inst_idx, uint8_t indirect) in vcn_v4_0_disable_clock_gating_dpg_mode()
883 static void vcn_v4_0_enable_ras(struct amdgpu_device *adev, int inst_idx, in vcn_v4_0_enable_ras()
914 static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v4_0_start_dpg_mode()
1429 static void vcn_v4_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) in vcn_v4_0_stop_dpg_mode()
1543 static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx, in vcn_v4_0_pause_dpg_mode()
H A Dvcn_v3_0.c498 static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v3_0_mc_resume_dpg_mode()
827 uint8_t sram_sel, int inst_idx, uint8_t indirect) in vcn_v3_0_clock_gating_dpg_mode()
942 static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in vcn_v3_0_start_dpg_mode()
1491 static int vcn_v3_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx) in vcn_v3_0_stop_dpg_mode()
1598 int inst_idx, struct dpg_pause_state *new_state) in vcn_v3_0_pause_dpg_mode()
H A Damdgpu_vcn.h81 #define RREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, mask, sram_sel) \ argument
91 #define WREG32_SOC15_DPG_MODE_1_0(ip, inst_idx, reg, value, mask, sram_sel) \ argument
102 #define SOC15_DPG_MODE_OFFSET(ip, inst_idx, reg) \ argument
135 #define RREG32_SOC15_DPG_MODE(inst_idx, offset, mask_en) \ argument
144 #define WREG32_SOC15_DPG_MODE(inst_idx, offset, value, mask_en, indirect) \ argument
H A Djpeg_v4_0_3.c414 static void jpeg_v4_0_3_disable_clock_gating(struct amdgpu_device *adev, int inst_idx) in jpeg_v4_0_3_disable_clock_gating()
439 static void jpeg_v4_0_3_enable_clock_gating(struct amdgpu_device *adev, int inst_idx) in jpeg_v4_0_3_enable_clock_gating()
H A Daqua_vanjaram.c70 uint32_t inst_idx, struct amdgpu_ring *ring) in aqua_vanjaram_set_xcp_id()
H A Dvcn_v2_0.c1202 int inst_idx, struct dpg_pause_state *new_state) in vcn_v2_0_pause_dpg_mode()
H A Dvcn_v1_0.c1212 int inst_idx, struct dpg_pause_state *new_state) in vcn_v1_0_pause_dpg_mode()
H A Damdgpu_vcn.c1249 int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, in amdgpu_vcn_psp_update_sram()