1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
7
8 #include <linux/debugfs.h>
9
10 #include <drm/drm_framebuffer.h>
11 #include <drm/drm_managed.h>
12
13 #include "dpu_encoder_phys.h"
14 #include "dpu_formats.h"
15 #include "dpu_hw_top.h"
16 #include "dpu_hw_wb.h"
17 #include "dpu_hw_lm.h"
18 #include "dpu_hw_merge3d.h"
19 #include "dpu_hw_interrupts.h"
20 #include "dpu_core_irq.h"
21 #include "dpu_vbif.h"
22 #include "dpu_crtc.h"
23 #include "disp/msm_disp_snapshot.h"
24
25 #define to_dpu_encoder_phys_wb(x) \
26 container_of(x, struct dpu_encoder_phys_wb, base)
27
28 /**
29 * dpu_encoder_phys_wb_is_master - report wb always as master encoder
30 * @phys_enc: Pointer to physical encoder
31 */
dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys * phys_enc)32 static bool dpu_encoder_phys_wb_is_master(struct dpu_encoder_phys *phys_enc)
33 {
34 /* there is only one physical enc for dpu_writeback */
35 return true;
36 }
37
38 /**
39 * dpu_encoder_phys_wb_set_ot_limit - set OT limit for writeback interface
40 * @phys_enc: Pointer to physical encoder
41 */
dpu_encoder_phys_wb_set_ot_limit(struct dpu_encoder_phys * phys_enc)42 static void dpu_encoder_phys_wb_set_ot_limit(
43 struct dpu_encoder_phys *phys_enc)
44 {
45 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
46 struct dpu_vbif_set_ot_params ot_params;
47
48 memset(&ot_params, 0, sizeof(ot_params));
49 ot_params.xin_id = hw_wb->caps->xin_id;
50 ot_params.num = hw_wb->idx - WB_0;
51 ot_params.width = phys_enc->cached_mode.hdisplay;
52 ot_params.height = phys_enc->cached_mode.vdisplay;
53 ot_params.is_wfd = true;
54 ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode);
55 ot_params.vbif_idx = hw_wb->caps->vbif_idx;
56 ot_params.clk_ctrl = hw_wb->caps->clk_ctrl;
57 ot_params.rd = false;
58
59 dpu_vbif_set_ot_limit(phys_enc->dpu_kms, &ot_params);
60 }
61
62 /**
63 * dpu_encoder_phys_wb_set_qos_remap - set QoS remapper for writeback
64 * @phys_enc: Pointer to physical encoder
65 */
dpu_encoder_phys_wb_set_qos_remap(struct dpu_encoder_phys * phys_enc)66 static void dpu_encoder_phys_wb_set_qos_remap(
67 struct dpu_encoder_phys *phys_enc)
68 {
69 struct dpu_hw_wb *hw_wb;
70 struct dpu_vbif_set_qos_params qos_params;
71
72 if (!phys_enc || !phys_enc->parent || !phys_enc->parent->crtc) {
73 DPU_ERROR("invalid arguments\n");
74 return;
75 }
76
77 if (!phys_enc->hw_wb || !phys_enc->hw_wb->caps) {
78 DPU_ERROR("invalid writeback hardware\n");
79 return;
80 }
81
82 hw_wb = phys_enc->hw_wb;
83
84 memset(&qos_params, 0, sizeof(qos_params));
85 qos_params.vbif_idx = hw_wb->caps->vbif_idx;
86 qos_params.xin_id = hw_wb->caps->xin_id;
87 qos_params.clk_ctrl = hw_wb->caps->clk_ctrl;
88 qos_params.num = hw_wb->idx - WB_0;
89 qos_params.is_rt = false;
90
91 DPU_DEBUG("[qos_remap] wb:%d vbif:%d xin:%d is_rt:%d\n",
92 qos_params.num,
93 qos_params.vbif_idx,
94 qos_params.xin_id, qos_params.is_rt);
95
96 dpu_vbif_set_qos_remap(phys_enc->dpu_kms, &qos_params);
97 }
98
99 /**
100 * dpu_encoder_phys_wb_set_qos - set QoS/danger/safe LUTs for writeback
101 * @phys_enc: Pointer to physical encoder
102 */
dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys * phys_enc)103 static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc)
104 {
105 struct dpu_hw_wb *hw_wb;
106 struct dpu_hw_qos_cfg qos_cfg;
107 const struct dpu_mdss_cfg *catalog;
108 const struct dpu_qos_lut_tbl *qos_lut_tb;
109
110 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
111 DPU_ERROR("invalid parameter(s)\n");
112 return;
113 }
114
115 catalog = phys_enc->dpu_kms->catalog;
116
117 hw_wb = phys_enc->hw_wb;
118
119 memset(&qos_cfg, 0, sizeof(struct dpu_hw_qos_cfg));
120 qos_cfg.danger_safe_en = true;
121 qos_cfg.danger_lut =
122 catalog->perf->danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
123
124 qos_cfg.safe_lut = catalog->perf->safe_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
125
126 qos_lut_tb = &catalog->perf->qos_lut_tbl[DPU_QOS_LUT_USAGE_NRT];
127 qos_cfg.creq_lut = _dpu_hw_get_qos_lut(qos_lut_tb, 0);
128
129 if (hw_wb->ops.setup_qos_lut)
130 hw_wb->ops.setup_qos_lut(hw_wb, &qos_cfg);
131 }
132
133 /**
134 * dpu_encoder_phys_wb_setup_fb - setup output framebuffer
135 * @phys_enc: Pointer to physical encoder
136 * @fb: Pointer to output framebuffer
137 */
dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys * phys_enc,struct drm_framebuffer * fb)138 static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc,
139 struct drm_framebuffer *fb)
140 {
141 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
142 struct dpu_hw_wb *hw_wb;
143 struct dpu_hw_wb_cfg *wb_cfg;
144
145 if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) {
146 DPU_ERROR("invalid encoder\n");
147 return;
148 }
149
150 hw_wb = phys_enc->hw_wb;
151 wb_cfg = &wb_enc->wb_cfg;
152
153 wb_cfg->intf_mode = phys_enc->intf_mode;
154 wb_cfg->roi.x1 = 0;
155 wb_cfg->roi.x2 = phys_enc->cached_mode.hdisplay;
156 wb_cfg->roi.y1 = 0;
157 wb_cfg->roi.y2 = phys_enc->cached_mode.vdisplay;
158
159 if (hw_wb->ops.setup_roi)
160 hw_wb->ops.setup_roi(hw_wb, wb_cfg);
161
162 if (hw_wb->ops.setup_outformat)
163 hw_wb->ops.setup_outformat(hw_wb, wb_cfg);
164
165 if (hw_wb->ops.setup_cdp) {
166 const struct dpu_perf_cfg *perf = phys_enc->dpu_kms->catalog->perf;
167
168 hw_wb->ops.setup_cdp(hw_wb, wb_cfg->dest.format,
169 perf->cdp_cfg[DPU_PERF_CDP_USAGE_NRT].wr_enable);
170 }
171
172 if (hw_wb->ops.setup_outaddress)
173 hw_wb->ops.setup_outaddress(hw_wb, wb_cfg);
174 }
175
176 /**
177 * dpu_encoder_phys_wb_setup_cdp - setup chroma down prefetch block
178 * @phys_enc:Pointer to physical encoder
179 */
dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys * phys_enc)180 static void dpu_encoder_phys_wb_setup_cdp(struct dpu_encoder_phys *phys_enc)
181 {
182 struct dpu_hw_wb *hw_wb;
183 struct dpu_hw_ctl *ctl;
184
185 if (!phys_enc) {
186 DPU_ERROR("invalid encoder\n");
187 return;
188 }
189
190 hw_wb = phys_enc->hw_wb;
191 ctl = phys_enc->hw_ctl;
192
193 if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) &&
194 (phys_enc->hw_ctl &&
195 phys_enc->hw_ctl->ops.setup_intf_cfg)) {
196 struct dpu_hw_intf_cfg intf_cfg = {0};
197 struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp;
198 enum dpu_3d_blend_mode mode_3d;
199
200 mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
201
202 intf_cfg.intf = DPU_NONE;
203 intf_cfg.wb = hw_wb->idx;
204
205 if (mode_3d && hw_pp && hw_pp->merge_3d)
206 intf_cfg.merge_3d = hw_pp->merge_3d->idx;
207
208 if (phys_enc->hw_pp->merge_3d && phys_enc->hw_pp->merge_3d->ops.setup_3d_mode)
209 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d,
210 mode_3d);
211
212 /* setup which pp blk will connect to this wb */
213 if (hw_pp && phys_enc->hw_wb->ops.bind_pingpong_blk)
214 phys_enc->hw_wb->ops.bind_pingpong_blk(phys_enc->hw_wb,
215 phys_enc->hw_pp->idx);
216
217 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
218 } else if (phys_enc->hw_ctl && phys_enc->hw_ctl->ops.setup_intf_cfg) {
219 struct dpu_hw_intf_cfg intf_cfg = {0};
220
221 intf_cfg.intf = DPU_NONE;
222 intf_cfg.wb = hw_wb->idx;
223 intf_cfg.mode_3d =
224 dpu_encoder_helper_get_3d_blend_mode(phys_enc);
225 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg);
226 }
227 }
228
229 /**
230 * dpu_encoder_phys_wb_atomic_check - verify and fixup given atomic states
231 * @phys_enc: Pointer to physical encoder
232 * @crtc_state: Pointer to CRTC atomic state
233 * @conn_state: Pointer to connector atomic state
234 */
dpu_encoder_phys_wb_atomic_check(struct dpu_encoder_phys * phys_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)235 static int dpu_encoder_phys_wb_atomic_check(
236 struct dpu_encoder_phys *phys_enc,
237 struct drm_crtc_state *crtc_state,
238 struct drm_connector_state *conn_state)
239 {
240 struct drm_framebuffer *fb;
241 const struct drm_display_mode *mode = &crtc_state->mode;
242
243 DPU_DEBUG("[atomic_check:%d, \"%s\",%d,%d]\n",
244 phys_enc->hw_wb->idx, mode->name, mode->hdisplay, mode->vdisplay);
245
246 if (!conn_state || !conn_state->connector) {
247 DPU_ERROR("invalid connector state\n");
248 return -EINVAL;
249 } else if (conn_state->connector->status !=
250 connector_status_connected) {
251 DPU_ERROR("connector not connected %d\n",
252 conn_state->connector->status);
253 return -EINVAL;
254 }
255
256 if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
257 return 0;
258
259 fb = conn_state->writeback_job->fb;
260
261 DPU_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id,
262 fb->width, fb->height);
263
264 if (fb->width != mode->hdisplay) {
265 DPU_ERROR("invalid fb w=%d, mode w=%d\n", fb->width,
266 mode->hdisplay);
267 return -EINVAL;
268 } else if (fb->height != mode->vdisplay) {
269 DPU_ERROR("invalid fb h=%d, mode h=%d\n", fb->height,
270 mode->vdisplay);
271 return -EINVAL;
272 } else if (fb->width > phys_enc->hw_wb->caps->maxlinewidth) {
273 DPU_ERROR("invalid fb w=%d, maxlinewidth=%u\n",
274 fb->width, phys_enc->hw_wb->caps->maxlinewidth);
275 return -EINVAL;
276 }
277
278 return 0;
279 }
280
281
282 /**
283 * _dpu_encoder_phys_wb_update_flush - flush hardware update
284 * @phys_enc: Pointer to physical encoder
285 */
_dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys * phys_enc)286 static void _dpu_encoder_phys_wb_update_flush(struct dpu_encoder_phys *phys_enc)
287 {
288 struct dpu_hw_wb *hw_wb;
289 struct dpu_hw_ctl *hw_ctl;
290 struct dpu_hw_pingpong *hw_pp;
291 u32 pending_flush = 0;
292
293 if (!phys_enc)
294 return;
295
296 hw_wb = phys_enc->hw_wb;
297 hw_pp = phys_enc->hw_pp;
298 hw_ctl = phys_enc->hw_ctl;
299
300 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
301
302 if (!hw_ctl) {
303 DPU_DEBUG("[wb:%d] no ctl assigned\n", hw_wb->idx - WB_0);
304 return;
305 }
306
307 if (hw_ctl->ops.update_pending_flush_wb)
308 hw_ctl->ops.update_pending_flush_wb(hw_ctl, hw_wb->idx);
309
310 if (hw_ctl->ops.update_pending_flush_merge_3d && hw_pp && hw_pp->merge_3d)
311 hw_ctl->ops.update_pending_flush_merge_3d(hw_ctl,
312 hw_pp->merge_3d->idx);
313
314 if (hw_ctl->ops.get_pending_flush)
315 pending_flush = hw_ctl->ops.get_pending_flush(hw_ctl);
316
317 DPU_DEBUG("Pending flush mask for CTL_%d is 0x%x, WB %d\n",
318 hw_ctl->idx - CTL_0, pending_flush,
319 hw_wb->idx - WB_0);
320 }
321
322 /**
323 * dpu_encoder_phys_wb_setup - setup writeback encoder
324 * @phys_enc: Pointer to physical encoder
325 */
dpu_encoder_phys_wb_setup(struct dpu_encoder_phys * phys_enc)326 static void dpu_encoder_phys_wb_setup(
327 struct dpu_encoder_phys *phys_enc)
328 {
329 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
330 struct drm_display_mode mode = phys_enc->cached_mode;
331 struct drm_framebuffer *fb = NULL;
332
333 DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n",
334 hw_wb->idx - WB_0, mode.name,
335 mode.hdisplay, mode.vdisplay);
336
337 dpu_encoder_phys_wb_set_ot_limit(phys_enc);
338
339 dpu_encoder_phys_wb_set_qos_remap(phys_enc);
340
341 dpu_encoder_phys_wb_set_qos(phys_enc);
342
343 dpu_encoder_phys_wb_setup_fb(phys_enc, fb);
344
345 dpu_encoder_phys_wb_setup_cdp(phys_enc);
346
347 }
348
349 /**
350 * dpu_encoder_phys_wb_done_irq - writeback interrupt handler
351 * @arg: Pointer to writeback encoder
352 */
dpu_encoder_phys_wb_done_irq(void * arg)353 static void dpu_encoder_phys_wb_done_irq(void *arg)
354 {
355 struct dpu_encoder_phys *phys_enc = arg;
356 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
357
358 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
359 unsigned long lock_flags;
360 u32 event = DPU_ENCODER_FRAME_EVENT_DONE;
361
362 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
363
364 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, event);
365
366 dpu_encoder_vblank_callback(phys_enc->parent, phys_enc);
367
368 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags);
369 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
370 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags);
371
372 if (wb_enc->wb_conn)
373 drm_writeback_signal_completion(wb_enc->wb_conn, 0);
374
375 /* Signal any waiting atomic commit thread */
376 wake_up_all(&phys_enc->pending_kickoff_wq);
377 }
378
379 /**
380 * dpu_encoder_phys_wb_irq_ctrl - irq control of WB
381 * @phys: Pointer to physical encoder
382 * @enable: indicates enable or disable interrupts
383 */
dpu_encoder_phys_wb_irq_ctrl(struct dpu_encoder_phys * phys,bool enable)384 static void dpu_encoder_phys_wb_irq_ctrl(
385 struct dpu_encoder_phys *phys, bool enable)
386 {
387
388 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys);
389
390 if (enable && atomic_inc_return(&wb_enc->wbirq_refcount) == 1)
391 dpu_core_irq_register_callback(phys->dpu_kms,
392 phys->irq[INTR_IDX_WB_DONE], dpu_encoder_phys_wb_done_irq, phys);
393 else if (!enable &&
394 atomic_dec_return(&wb_enc->wbirq_refcount) == 0)
395 dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]);
396 }
397
dpu_encoder_phys_wb_atomic_mode_set(struct dpu_encoder_phys * phys_enc,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)398 static void dpu_encoder_phys_wb_atomic_mode_set(
399 struct dpu_encoder_phys *phys_enc,
400 struct drm_crtc_state *crtc_state,
401 struct drm_connector_state *conn_state)
402 {
403
404 phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done;
405 }
406
_dpu_encoder_phys_wb_handle_wbdone_timeout(struct dpu_encoder_phys * phys_enc)407 static void _dpu_encoder_phys_wb_handle_wbdone_timeout(
408 struct dpu_encoder_phys *phys_enc)
409 {
410 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
411 u32 frame_event = DPU_ENCODER_FRAME_EVENT_ERROR;
412
413 wb_enc->wb_done_timeout_cnt++;
414
415 if (wb_enc->wb_done_timeout_cnt == 1)
416 msm_disp_snapshot_state(phys_enc->parent->dev);
417
418 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0);
419
420 /* request a ctl reset before the next kickoff */
421 phys_enc->enable_state = DPU_ENC_ERR_NEEDS_HW_RESET;
422
423 if (wb_enc->wb_conn)
424 drm_writeback_signal_completion(wb_enc->wb_conn, 0);
425
426 dpu_encoder_frame_done_callback(phys_enc->parent, phys_enc, frame_event);
427 }
428
429 /**
430 * dpu_encoder_phys_wb_wait_for_commit_done - wait until request is committed
431 * @phys_enc: Pointer to physical encoder
432 */
dpu_encoder_phys_wb_wait_for_commit_done(struct dpu_encoder_phys * phys_enc)433 static int dpu_encoder_phys_wb_wait_for_commit_done(
434 struct dpu_encoder_phys *phys_enc)
435 {
436 unsigned long ret;
437 struct dpu_encoder_wait_info wait_info;
438 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
439
440 wait_info.wq = &phys_enc->pending_kickoff_wq;
441 wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
442 wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
443
444 ret = dpu_encoder_helper_wait_for_irq(phys_enc,
445 phys_enc->irq[INTR_IDX_WB_DONE],
446 dpu_encoder_phys_wb_done_irq, &wait_info);
447 if (ret == -ETIMEDOUT)
448 _dpu_encoder_phys_wb_handle_wbdone_timeout(phys_enc);
449 else if (!ret)
450 wb_enc->wb_done_timeout_cnt = 0;
451
452 return ret;
453 }
454
455 /**
456 * dpu_encoder_phys_wb_prepare_for_kickoff - pre-kickoff processing
457 * @phys_enc: Pointer to physical encoder
458 * Returns: Zero on success
459 */
dpu_encoder_phys_wb_prepare_for_kickoff(struct dpu_encoder_phys * phys_enc)460 static void dpu_encoder_phys_wb_prepare_for_kickoff(
461 struct dpu_encoder_phys *phys_enc)
462 {
463 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
464 struct drm_connector *drm_conn;
465 struct drm_connector_state *state;
466
467 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
468
469 if (!wb_enc->wb_conn || !wb_enc->wb_job) {
470 DPU_ERROR("invalid wb_conn or wb_job\n");
471 return;
472 }
473
474 drm_conn = &wb_enc->wb_conn->base;
475 state = drm_conn->state;
476
477 if (wb_enc->wb_conn && wb_enc->wb_job)
478 drm_writeback_queue_job(wb_enc->wb_conn, state);
479
480 dpu_encoder_phys_wb_setup(phys_enc);
481
482 _dpu_encoder_phys_wb_update_flush(phys_enc);
483 }
484
485 /**
486 * dpu_encoder_phys_wb_needs_single_flush - trigger flush processing
487 * @phys_enc: Pointer to physical encoder
488 */
dpu_encoder_phys_wb_needs_single_flush(struct dpu_encoder_phys * phys_enc)489 static bool dpu_encoder_phys_wb_needs_single_flush(struct dpu_encoder_phys *phys_enc)
490 {
491 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
492 return false;
493 }
494
495 /**
496 * dpu_encoder_phys_wb_handle_post_kickoff - post-kickoff processing
497 * @phys_enc: Pointer to physical encoder
498 */
dpu_encoder_phys_wb_handle_post_kickoff(struct dpu_encoder_phys * phys_enc)499 static void dpu_encoder_phys_wb_handle_post_kickoff(
500 struct dpu_encoder_phys *phys_enc)
501 {
502 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
503
504 }
505
506 /**
507 * dpu_encoder_phys_wb_enable - enable writeback encoder
508 * @phys_enc: Pointer to physical encoder
509 */
dpu_encoder_phys_wb_enable(struct dpu_encoder_phys * phys_enc)510 static void dpu_encoder_phys_wb_enable(struct dpu_encoder_phys *phys_enc)
511 {
512 DPU_DEBUG("[wb:%d]\n", phys_enc->hw_wb->idx - WB_0);
513 phys_enc->enable_state = DPU_ENC_ENABLED;
514 }
515 /**
516 * dpu_encoder_phys_wb_disable - disable writeback encoder
517 * @phys_enc: Pointer to physical encoder
518 */
dpu_encoder_phys_wb_disable(struct dpu_encoder_phys * phys_enc)519 static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc)
520 {
521 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
522 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
523
524 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
525
526 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
527 DPU_ERROR("encoder is already disabled\n");
528 return;
529 }
530
531 /* reset h/w before final flush */
532 phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);
533
534 /*
535 * New CTL reset sequence from 5.0 MDP onwards.
536 * If has_3d_merge_reset is not set, legacy reset
537 * sequence is executed.
538 *
539 * Legacy reset sequence has not been implemented yet.
540 * Any target earlier than SM8150 will need it and when
541 * WB support is added to those targets will need to add
542 * the legacy teardown sequence as well.
543 */
544 if (hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG))
545 dpu_encoder_helper_phys_cleanup(phys_enc);
546
547 phys_enc->enable_state = DPU_ENC_DISABLED;
548 }
549
dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys * phys_enc,struct drm_writeback_job * job)550 static void dpu_encoder_phys_wb_prepare_wb_job(struct dpu_encoder_phys *phys_enc,
551 struct drm_writeback_job *job)
552 {
553 const struct msm_format *format;
554 struct msm_gem_address_space *aspace;
555 struct dpu_hw_wb_cfg *wb_cfg;
556 int ret;
557 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
558
559 if (!job->fb)
560 return;
561
562 wb_enc->wb_job = job;
563 wb_enc->wb_conn = job->connector;
564 aspace = phys_enc->dpu_kms->base.aspace;
565
566 wb_cfg = &wb_enc->wb_cfg;
567
568 memset(wb_cfg, 0, sizeof(struct dpu_hw_wb_cfg));
569
570 ret = msm_framebuffer_prepare(job->fb, aspace, false);
571 if (ret) {
572 DPU_ERROR("prep fb failed, %d\n", ret);
573 return;
574 }
575
576 format = msm_framebuffer_format(job->fb);
577
578 wb_cfg->dest.format = dpu_get_dpu_format_ext(
579 format->pixel_format, job->fb->modifier);
580 if (!wb_cfg->dest.format) {
581 /* this error should be detected during atomic_check */
582 DPU_ERROR("failed to get format %x\n", format->pixel_format);
583 return;
584 }
585
586 ret = dpu_format_populate_layout(aspace, job->fb, &wb_cfg->dest);
587 if (ret) {
588 DPU_DEBUG("failed to populate layout %d\n", ret);
589 return;
590 }
591
592 wb_cfg->dest.width = job->fb->width;
593 wb_cfg->dest.height = job->fb->height;
594 wb_cfg->dest.num_planes = wb_cfg->dest.format->num_planes;
595
596 if ((wb_cfg->dest.format->fetch_planes == DPU_PLANE_PLANAR) &&
597 (wb_cfg->dest.format->element[0] == C1_B_Cb))
598 swap(wb_cfg->dest.plane_addr[1], wb_cfg->dest.plane_addr[2]);
599
600 DPU_DEBUG("[fb_offset:%8.8x,%8.8x,%8.8x,%8.8x]\n",
601 wb_cfg->dest.plane_addr[0], wb_cfg->dest.plane_addr[1],
602 wb_cfg->dest.plane_addr[2], wb_cfg->dest.plane_addr[3]);
603
604 DPU_DEBUG("[fb_stride:%8.8x,%8.8x,%8.8x,%8.8x]\n",
605 wb_cfg->dest.plane_pitch[0], wb_cfg->dest.plane_pitch[1],
606 wb_cfg->dest.plane_pitch[2], wb_cfg->dest.plane_pitch[3]);
607 }
608
dpu_encoder_phys_wb_cleanup_wb_job(struct dpu_encoder_phys * phys_enc,struct drm_writeback_job * job)609 static void dpu_encoder_phys_wb_cleanup_wb_job(struct dpu_encoder_phys *phys_enc,
610 struct drm_writeback_job *job)
611 {
612 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
613 struct msm_gem_address_space *aspace;
614
615 if (!job->fb)
616 return;
617
618 aspace = phys_enc->dpu_kms->base.aspace;
619
620 msm_framebuffer_cleanup(job->fb, aspace, false);
621 wb_enc->wb_job = NULL;
622 wb_enc->wb_conn = NULL;
623 }
624
dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys * phys_enc)625 static bool dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys *phys_enc)
626 {
627 struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc);
628
629 if (wb_enc->wb_job)
630 return true;
631 else
632 return false;
633 }
634
635 /**
636 * dpu_encoder_phys_wb_init_ops - initialize writeback operations
637 * @ops: Pointer to encoder operation table
638 */
dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops * ops)639 static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops)
640 {
641 ops->is_master = dpu_encoder_phys_wb_is_master;
642 ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set;
643 ops->enable = dpu_encoder_phys_wb_enable;
644 ops->disable = dpu_encoder_phys_wb_disable;
645 ops->atomic_check = dpu_encoder_phys_wb_atomic_check;
646 ops->wait_for_commit_done = dpu_encoder_phys_wb_wait_for_commit_done;
647 ops->prepare_for_kickoff = dpu_encoder_phys_wb_prepare_for_kickoff;
648 ops->handle_post_kickoff = dpu_encoder_phys_wb_handle_post_kickoff;
649 ops->needs_single_flush = dpu_encoder_phys_wb_needs_single_flush;
650 ops->trigger_start = dpu_encoder_helper_trigger_start;
651 ops->prepare_wb_job = dpu_encoder_phys_wb_prepare_wb_job;
652 ops->cleanup_wb_job = dpu_encoder_phys_wb_cleanup_wb_job;
653 ops->irq_control = dpu_encoder_phys_wb_irq_ctrl;
654 ops->is_valid_for_commit = dpu_encoder_phys_wb_is_valid_for_commit;
655
656 }
657
658 /**
659 * dpu_encoder_phys_wb_init - initialize writeback encoder
660 * @dev: Corresponding device for devres management
661 * @p: Pointer to init info structure with initialization params
662 */
dpu_encoder_phys_wb_init(struct drm_device * dev,struct dpu_enc_phys_init_params * p)663 struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev,
664 struct dpu_enc_phys_init_params *p)
665 {
666 struct dpu_encoder_phys *phys_enc = NULL;
667 struct dpu_encoder_phys_wb *wb_enc = NULL;
668
669 DPU_DEBUG("\n");
670
671 if (!p || !p->parent) {
672 DPU_ERROR("invalid params\n");
673 return ERR_PTR(-EINVAL);
674 }
675
676 wb_enc = drmm_kzalloc(dev, sizeof(*wb_enc), GFP_KERNEL);
677 if (!wb_enc) {
678 DPU_ERROR("failed to allocate wb phys_enc enc\n");
679 return ERR_PTR(-ENOMEM);
680 }
681
682 phys_enc = &wb_enc->base;
683
684 dpu_encoder_phys_init(phys_enc, p);
685
686 dpu_encoder_phys_wb_init_ops(&phys_enc->ops);
687 phys_enc->intf_mode = INTF_MODE_WB_LINE;
688
689 atomic_set(&wb_enc->wbirq_refcount, 0);
690
691 wb_enc->wb_done_timeout_cnt = 0;
692
693 DPU_DEBUG("Created dpu_encoder_phys for wb %d\n", phys_enc->hw_wb->idx);
694
695 return phys_enc;
696 }
697