1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/slab.h> 21 #include <linux/usb/typec.h> 22 #include <linux/usb/typec_mux.h> 23 24 #include <drm/drm_bridge.h> 25 26 #include <dt-bindings/phy/phy-qcom-qmp.h> 27 28 #include "phy-qcom-qmp.h" 29 #include "phy-qcom-qmp-pcs-misc-v3.h" 30 #include "phy-qcom-qmp-pcs-usb-v4.h" 31 #include "phy-qcom-qmp-pcs-usb-v5.h" 32 #include "phy-qcom-qmp-pcs-usb-v6.h" 33 34 /* QPHY_SW_RESET bit */ 35 #define SW_RESET BIT(0) 36 /* QPHY_POWER_DOWN_CONTROL */ 37 #define SW_PWRDN BIT(0) 38 /* QPHY_START_CONTROL bits */ 39 #define SERDES_START BIT(0) 40 #define PCS_START BIT(1) 41 /* QPHY_PCS_STATUS bit */ 42 #define PHYSTATUS BIT(6) 43 44 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 45 /* DP PHY soft reset */ 46 #define SW_DPPHY_RESET BIT(0) 47 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 48 #define SW_DPPHY_RESET_MUX BIT(1) 49 /* USB3 PHY soft reset */ 50 #define SW_USB3PHY_RESET BIT(2) 51 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 52 #define SW_USB3PHY_RESET_MUX BIT(3) 53 54 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 55 #define USB3_MODE BIT(0) /* enables USB3 mode */ 56 #define DP_MODE BIT(1) /* enables DP mode */ 57 58 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 59 #define ARCVR_DTCT_EN BIT(0) 60 #define ALFPS_DTCT_EN BIT(1) 61 #define ARCVR_DTCT_EVENT_SEL BIT(4) 62 63 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 64 #define IRQ_CLEAR BIT(0) 65 66 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 67 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 68 69 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */ 70 #define SW_PORTSELECT_VAL BIT(0) 71 #define SW_PORTSELECT_MUX BIT(1) 72 73 #define PHY_INIT_COMPLETE_TIMEOUT 10000 74 75 struct qmp_phy_init_tbl { 76 unsigned int offset; 77 unsigned int val; 78 /* 79 * mask of lanes for which this register is written 80 * for cases when second lane needs different values 81 */ 82 u8 lane_mask; 83 }; 84 85 #define QMP_PHY_INIT_CFG(o, v) \ 86 { \ 87 .offset = o, \ 88 .val = v, \ 89 .lane_mask = 0xff, \ 90 } 91 92 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 93 { \ 94 .offset = o, \ 95 .val = v, \ 96 .lane_mask = l, \ 97 } 98 99 /* set of registers with offsets different per-PHY */ 100 enum qphy_reg_layout { 101 /* PCS registers */ 102 QPHY_SW_RESET, 103 QPHY_START_CTRL, 104 QPHY_PCS_STATUS, 105 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 106 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 107 QPHY_PCS_POWER_DOWN_CONTROL, 108 109 QPHY_COM_RESETSM_CNTRL, 110 QPHY_COM_C_READY_STATUS, 111 QPHY_COM_CMN_STATUS, 112 QPHY_COM_BIAS_EN_CLKBUFLR_EN, 113 114 QPHY_DP_PHY_STATUS, 115 QPHY_DP_PHY_VCO_DIV, 116 117 QPHY_TX_TX_POL_INV, 118 QPHY_TX_TX_DRV_LVL, 119 QPHY_TX_TX_EMP_POST1_LVL, 120 QPHY_TX_HIGHZ_DRVR_EN, 121 QPHY_TX_TRANSCEIVER_BIAS_EN, 122 123 /* Keep last to ensure regs_layout arrays are properly initialized */ 124 QPHY_LAYOUT_SIZE 125 }; 126 127 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 128 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 129 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 130 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 131 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 132 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 133 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 134 135 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V3_COM_RESETSM_CNTRL, 136 [QPHY_COM_C_READY_STATUS] = QSERDES_V3_COM_C_READY_STATUS, 137 [QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS, 138 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 139 140 [QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS, 141 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V3_DP_PHY_VCO_DIV, 142 143 [QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV, 144 [QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL, 145 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL, 146 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V3_TX_HIGHZ_DRVR_EN, 147 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 148 }; 149 150 static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 151 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 152 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 153 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 154 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 155 156 /* In PCS_USB */ 157 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 158 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 159 160 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V4_COM_RESETSM_CNTRL, 161 [QPHY_COM_C_READY_STATUS] = QSERDES_V4_COM_C_READY_STATUS, 162 [QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS, 163 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 164 165 [QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS, 166 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V4_DP_PHY_VCO_DIV, 167 168 [QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV, 169 [QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL, 170 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL, 171 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V4_TX_HIGHZ_DRVR_EN, 172 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN, 173 }; 174 175 static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 176 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 177 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 178 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 179 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 180 181 /* In PCS_USB */ 182 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 183 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 184 185 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL, 186 [QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS, 187 [QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS, 188 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 189 190 [QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS, 191 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V5_DP_PHY_VCO_DIV, 192 193 [QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV, 194 [QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL, 195 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL, 196 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN, 197 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 198 }; 199 200 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 201 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 202 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 203 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 204 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 205 206 /* In PCS_USB */ 207 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 208 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 209 210 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL, 211 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS, 212 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS, 213 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 214 215 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS, 216 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV, 217 218 [QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV, 219 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL, 220 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL, 221 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_TX_HIGHZ_DRVR_EN, 222 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN, 223 }; 224 225 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 226 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 227 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 228 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 229 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 230 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 231 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 232 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 233 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 234 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 235 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 236 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 237 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 238 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 239 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 240 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 241 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 242 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 243 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 244 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 245 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 246 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 247 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 248 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 252 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 254 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 255 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 257 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 258 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 259 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 260 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 261 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 262 }; 263 264 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 265 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 266 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 267 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 268 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 269 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 270 }; 271 272 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = { 273 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37), 275 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 276 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e), 277 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06), 278 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 279 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02), 280 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00), 281 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 282 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 283 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 284 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 285 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 286 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 287 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 288 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), 289 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f), 290 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 291 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 294 }; 295 296 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = { 297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c), 298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 299 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 300 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 301 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f), 302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08), 303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 304 }; 305 306 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = { 307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04), 308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 309 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 310 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 311 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f), 312 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e), 313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 314 }; 315 316 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = { 317 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 318 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c), 319 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00), 320 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a), 321 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f), 322 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c), 323 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00), 324 }; 325 326 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = { 327 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03), 328 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69), 329 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80), 330 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07), 331 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f), 332 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a), 333 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08), 334 }; 335 336 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = { 337 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), 338 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), 339 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 340 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), 341 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), 342 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), 343 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), 344 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 345 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), 346 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), 347 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a), 348 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38), 349 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20), 350 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 351 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 352 }; 353 354 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 355 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 356 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 357 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 358 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 359 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 360 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 361 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 362 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 363 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 364 }; 365 366 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 367 /* FLL settings */ 368 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 369 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 372 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 373 374 /* Lock Det settings */ 375 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 376 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 377 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 378 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 379 380 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 381 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 382 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 383 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 384 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 385 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 386 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 387 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 388 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 389 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 390 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 391 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 392 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 393 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 394 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 395 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 396 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 397 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 398 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 399 400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 401 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 402 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 403 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 404 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 405 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 406 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 407 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 408 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 409 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 410 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 411 }; 412 413 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = { 414 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 415 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 416 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 417 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 418 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 419 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 420 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 421 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 422 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 423 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 424 }; 425 426 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = { 427 /* FLL settings */ 428 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 429 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 430 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 431 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 432 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 433 434 /* Lock Det settings */ 435 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 436 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 437 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 438 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 439 440 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc), 441 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 442 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 443 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 444 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 445 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 446 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 447 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 448 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 449 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 450 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 453 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 454 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 459 460 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 461 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 462 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 467 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04), 472 473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 474 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 475 }; 476 477 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 478 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 479 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 480 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 481 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 482 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 483 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 484 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 485 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 486 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 487 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 488 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 489 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 490 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 491 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 492 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 493 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 494 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 495 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 496 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 497 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 498 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 499 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 500 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 501 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 502 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 503 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 504 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 505 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 506 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 507 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 508 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 509 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 510 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 511 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 512 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 513 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 514 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 515 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 516 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 517 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 518 }; 519 520 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 521 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 522 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 523 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 524 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 525 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 526 }; 527 528 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 529 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 530 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 531 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 532 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 533 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 534 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 535 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 536 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 537 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 538 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 539 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 540 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 541 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 542 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 543 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 544 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 545 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 546 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 547 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 548 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 549 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 550 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 551 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 552 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 553 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 554 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 555 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 556 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 557 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 558 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 559 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 560 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 561 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 562 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 563 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 564 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 565 }; 566 567 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 568 /* Lock Det settings */ 569 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 570 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 571 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 572 573 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 574 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 575 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 576 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 577 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 578 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 579 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 580 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 581 }; 582 583 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 584 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 585 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 586 }; 587 588 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 589 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 590 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 591 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 592 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 593 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 594 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 595 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 596 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 597 }; 598 599 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 602 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 603 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 604 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 605 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 606 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 607 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 608 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 609 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 610 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 611 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 612 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 613 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 614 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 615 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 616 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 617 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 618 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 619 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 620 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 621 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 622 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 623 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 624 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 625 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 626 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 627 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 628 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 629 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 630 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 631 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 632 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 633 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 634 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 635 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 636 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 637 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 638 }; 639 640 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 641 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 642 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 643 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 644 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 645 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 646 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 647 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 648 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 649 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 650 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 651 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 652 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 653 }; 654 655 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 656 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 657 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 658 }; 659 660 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { 661 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), 662 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), 663 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 664 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 665 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), 666 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 667 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), 668 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), 669 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), 670 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 671 }; 672 673 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { 674 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 675 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 676 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 677 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 678 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 679 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 680 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 681 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 682 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 683 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 684 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 685 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 686 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 687 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 688 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 689 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 690 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 691 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 692 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 693 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 694 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 695 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), 696 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), 697 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), 698 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), 699 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), 700 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 701 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 702 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 703 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), 704 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), 705 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 706 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), 707 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 708 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 709 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 710 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 711 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), 712 }; 713 714 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { 715 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 716 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 717 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 718 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 719 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 720 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 721 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 722 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 723 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 724 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 725 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 726 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 727 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 728 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 729 }; 730 731 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = { 732 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 733 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 734 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 735 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 736 }; 737 738 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = { 739 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0), 740 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01), 741 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02), 742 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16), 743 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36), 744 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04), 745 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16), 746 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41), 747 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41), 748 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00), 749 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55), 750 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75), 751 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01), 752 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 753 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25), 754 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02), 755 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c), 756 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f), 757 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c), 758 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f), 759 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0), 760 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01), 761 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02), 762 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 763 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 764 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08), 765 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a), 766 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 767 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00), 768 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55), 769 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75), 770 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01), 771 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25), 772 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02), 773 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 774 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01), 775 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62), 776 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02), 777 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c), 778 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a), 779 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14), 780 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 781 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20), 782 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 783 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6), 784 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b), 785 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37), 786 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c), 787 }; 788 789 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = { 790 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00), 791 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00), 792 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 793 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 794 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5), 795 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f), 796 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f), 797 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f), 798 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12), 799 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1), 800 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2), 801 }; 802 803 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = { 804 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a), 805 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06), 806 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 807 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 808 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 809 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 810 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99), 811 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08), 812 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08), 813 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00), 814 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a), 815 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 816 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54), 817 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f), 818 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13), 819 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 820 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 821 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 822 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07), 823 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 824 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 825 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04), 826 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 827 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc), 828 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c), 829 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c), 830 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d), 831 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09), 832 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04), 833 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 834 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c), 835 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10), 836 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14), 837 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08), 838 839 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1), 840 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1), 841 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1), 842 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1), 843 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1), 844 845 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2), 846 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2), 847 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2), 848 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2), 849 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2), 850 }; 851 852 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = { 853 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4), 854 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG2, 0x89), 855 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG3, 0x20), 856 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_LOCK_DETECT_CONFIG6, 0x13), 857 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_REFGEN_REQ_CONFIG1, 0x21), 858 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RX_SIGDET_LVL, 0x99), 859 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 860 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 861 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_CDR_RESET_TIME, 0x0a), 862 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88), 863 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13), 864 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_PCS_TX_RX_CONFIG, 0x0c), 865 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG1, 0x4b), 866 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_EQ_CONFIG5, 0x10), 867 }; 868 869 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = { 870 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68), 871 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 872 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 873 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 874 QMP_PHY_INIT_CFG(QPHY_USB_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 875 }; 876 877 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = { 878 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 879 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 880 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 881 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 882 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 883 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 884 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 885 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 886 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 887 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 888 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 889 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 890 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 891 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00), 892 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 893 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 894 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 895 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 896 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 897 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 898 }; 899 900 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = { 901 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05), 902 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 903 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 904 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 905 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f), 906 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08), 907 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 908 }; 909 910 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = { 911 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03), 912 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 913 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 914 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 915 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f), 916 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e), 917 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 918 }; 919 920 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = { 921 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 922 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c), 923 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00), 924 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a), 925 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f), 926 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c), 927 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 928 }; 929 930 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = { 931 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00), 932 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69), 933 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80), 934 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07), 935 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f), 936 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a), 937 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08), 938 }; 939 940 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = { 941 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40), 942 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 943 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b), 944 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f), 945 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03), 946 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f), 947 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 948 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00), 949 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 950 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 951 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4), 952 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a), 953 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a), 954 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20), 955 }; 956 957 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = { 958 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05), 959 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b), 960 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02), 961 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c), 962 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06), 963 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30), 964 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 965 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 966 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 967 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 968 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 969 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 970 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 971 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02), 972 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 973 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 974 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 975 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00), 976 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a), 977 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a), 978 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00), 979 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17), 980 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f), 981 }; 982 983 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = { 984 QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40), 985 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 986 QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b), 987 QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f), 988 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03), 989 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f), 990 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 991 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00), 992 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 993 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 994 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04), 995 }; 996 997 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = { 998 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51), 999 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a), 1000 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40), 1001 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0), 1002 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff), 1003 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f), 1004 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03), 1005 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf), 1006 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1007 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 1008 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11), 1009 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01), 1010 }; 1011 1012 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = { 1013 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15), 1014 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b), 1015 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02), 1016 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c), 1017 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06), 1018 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30), 1019 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 1020 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36), 1021 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16), 1022 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 1023 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00), 1024 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12), 1025 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 1026 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1027 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00), 1028 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a), 1029 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14), 1030 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00), 1031 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17), 1032 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f), 1033 }; 1034 1035 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = { 1036 QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40), 1037 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30), 1038 QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b), 1039 QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f), 1040 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03), 1041 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f), 1042 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), 1043 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00), 1044 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c), 1045 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c), 1046 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4), 1047 }; 1048 1049 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = { 1050 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05), 1051 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1052 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1053 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1054 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37), 1055 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04), 1056 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04), 1057 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1058 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1059 }; 1060 1061 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = { 1062 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03), 1063 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1064 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1065 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1066 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07), 1067 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), 1068 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1069 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1070 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1071 }; 1072 1073 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = { 1074 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01), 1075 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46), 1076 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00), 1077 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05), 1078 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f), 1079 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e), 1080 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1081 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97), 1082 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10), 1083 }; 1084 1085 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = { 1086 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00), 1087 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34), 1088 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0), 1089 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b), 1090 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17), 1091 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15), 1092 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08), 1093 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71), 1094 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c), 1095 }; 1096 1097 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = { 1098 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1100 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1101 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd), 1102 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d), 1103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd), 1104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d), 1105 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1106 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02), 1107 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02), 1108 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1109 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1110 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1111 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1112 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1113 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1115 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1117 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1118 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04), 1119 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01), 1120 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04), 1121 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01), 1122 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55), 1123 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5), 1124 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05), 1125 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55), 1126 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5), 1127 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05), 1128 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1129 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4), 1130 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00), 1131 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4), 1132 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00), 1133 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13), 1134 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 1135 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a), 1136 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04), 1137 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60), 1138 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76), 1139 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff), 1140 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20), 1141 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20), 1142 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 1143 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01), 1144 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a), 1145 }; 1146 1147 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = { 1148 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05), 1149 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2), 1150 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10), 1151 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a), 1153 }; 1154 1155 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = { 1156 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04), 1157 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1158 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2), 1161 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb), 1162 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21), 1163 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f), 1164 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80), 1165 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45), 1166 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00), 1167 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b), 1168 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63), 1169 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6), 1170 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23), 1171 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35), 1172 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30), 1173 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e), 1174 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00), 1175 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00), 1176 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80), 1177 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b), 1178 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1179 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15), 1180 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a), 1181 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c), 1182 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00), 1183 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d), 1184 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00), 1185 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45), 1186 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09), 1187 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09), 1188 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05), 1189 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f), 1190 }; 1191 1192 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = { 1193 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1194 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1195 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1196 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1197 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1198 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1199 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1200 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1201 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a), 1202 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1203 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1204 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1205 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1206 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1207 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1208 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1209 }; 1210 1211 /* list of regulators */ 1212 struct qmp_regulator_data { 1213 const char *name; 1214 unsigned int enable_load; 1215 }; 1216 1217 static struct qmp_regulator_data qmp_phy_vreg_l[] = { 1218 { .name = "vdda-phy", .enable_load = 21800 }, 1219 { .name = "vdda-pll", .enable_load = 36000 }, 1220 }; 1221 1222 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = { 1223 { 0x00, 0x0c, 0x15, 0x1a }, 1224 { 0x02, 0x0e, 0x16, 0xff }, 1225 { 0x02, 0x11, 0xff, 0xff }, 1226 { 0x04, 0xff, 0xff, 0xff } 1227 }; 1228 1229 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = { 1230 { 0x02, 0x12, 0x16, 0x1a }, 1231 { 0x09, 0x19, 0x1f, 0xff }, 1232 { 0x10, 0x1f, 0xff, 0xff }, 1233 { 0x1f, 0xff, 0xff, 0xff } 1234 }; 1235 1236 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = { 1237 { 0x00, 0x0c, 0x14, 0x19 }, 1238 { 0x00, 0x0b, 0x12, 0xff }, 1239 { 0x00, 0x0b, 0xff, 0xff }, 1240 { 0x04, 0xff, 0xff, 0xff } 1241 }; 1242 1243 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = { 1244 { 0x08, 0x0f, 0x16, 0x1f }, 1245 { 0x11, 0x1e, 0x1f, 0xff }, 1246 { 0x19, 0x1f, 0xff, 0xff }, 1247 { 0x1f, 0xff, 0xff, 0xff } 1248 }; 1249 1250 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = { 1251 { 0x00, 0x0c, 0x15, 0x1b }, 1252 { 0x02, 0x0e, 0x16, 0xff }, 1253 { 0x02, 0x11, 0xff, 0xff }, 1254 { 0x04, 0xff, 0xff, 0xff } 1255 }; 1256 1257 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = { 1258 { 0x00, 0x0d, 0x14, 0x1a }, 1259 { 0x00, 0x0e, 0x15, 0xff }, 1260 { 0x00, 0x0d, 0xff, 0xff }, 1261 { 0x03, 0xff, 0xff, 0xff } 1262 }; 1263 1264 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = { 1265 { 0x08, 0x0f, 0x16, 0x1f }, 1266 { 0x11, 0x1e, 0x1f, 0xff }, 1267 { 0x16, 0x1f, 0xff, 0xff }, 1268 { 0x1f, 0xff, 0xff, 0xff } 1269 }; 1270 1271 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = { 1272 { 0x20, 0x2c, 0x35, 0x3b }, 1273 { 0x22, 0x2e, 0x36, 0xff }, 1274 { 0x22, 0x31, 0xff, 0xff }, 1275 { 0x24, 0xff, 0xff, 0xff } 1276 }; 1277 1278 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = { 1279 { 0x22, 0x32, 0x36, 0x3a }, 1280 { 0x29, 0x39, 0x3f, 0xff }, 1281 { 0x30, 0x3f, 0xff, 0xff }, 1282 { 0x3f, 0xff, 0xff, 0xff } 1283 }; 1284 1285 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = { 1286 { 0x20, 0x2d, 0x34, 0x3a }, 1287 { 0x20, 0x2e, 0x35, 0xff }, 1288 { 0x20, 0x2e, 0xff, 0xff }, 1289 { 0x24, 0xff, 0xff, 0xff } 1290 }; 1291 1292 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = { 1293 { 0x28, 0x2f, 0x36, 0x3f }, 1294 { 0x31, 0x3e, 0x3f, 0xff }, 1295 { 0x36, 0x3f, 0xff, 0xff }, 1296 { 0x3f, 0xff, 0xff, 0xff } 1297 }; 1298 1299 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = { 1300 { 0x20, 0x2d, 0x34, 0x3a }, 1301 { 0x20, 0x2e, 0x35, 0xff }, 1302 { 0x20, 0x2e, 0xff, 0xff }, 1303 { 0x22, 0xff, 0xff, 0xff } 1304 }; 1305 1306 struct qmp_combo; 1307 1308 struct qmp_combo_offsets { 1309 u16 com; 1310 u16 txa; 1311 u16 rxa; 1312 u16 txb; 1313 u16 rxb; 1314 u16 usb3_serdes; 1315 u16 usb3_pcs_misc; 1316 u16 usb3_pcs; 1317 u16 usb3_pcs_usb; 1318 u16 dp_serdes; 1319 u16 dp_txa; 1320 u16 dp_txb; 1321 u16 dp_dp_phy; 1322 }; 1323 1324 struct qmp_phy_cfg { 1325 const struct qmp_combo_offsets *offsets; 1326 1327 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1328 const struct qmp_phy_init_tbl *serdes_tbl; 1329 int serdes_tbl_num; 1330 const struct qmp_phy_init_tbl *tx_tbl; 1331 int tx_tbl_num; 1332 const struct qmp_phy_init_tbl *rx_tbl; 1333 int rx_tbl_num; 1334 const struct qmp_phy_init_tbl *pcs_tbl; 1335 int pcs_tbl_num; 1336 const struct qmp_phy_init_tbl *pcs_usb_tbl; 1337 int pcs_usb_tbl_num; 1338 1339 const struct qmp_phy_init_tbl *dp_serdes_tbl; 1340 int dp_serdes_tbl_num; 1341 const struct qmp_phy_init_tbl *dp_tx_tbl; 1342 int dp_tx_tbl_num; 1343 1344 /* Init sequence for DP PHY block link rates */ 1345 const struct qmp_phy_init_tbl *serdes_tbl_rbr; 1346 int serdes_tbl_rbr_num; 1347 const struct qmp_phy_init_tbl *serdes_tbl_hbr; 1348 int serdes_tbl_hbr_num; 1349 const struct qmp_phy_init_tbl *serdes_tbl_hbr2; 1350 int serdes_tbl_hbr2_num; 1351 const struct qmp_phy_init_tbl *serdes_tbl_hbr3; 1352 int serdes_tbl_hbr3_num; 1353 1354 /* DP PHY swing and pre_emphasis tables */ 1355 const u8 (*swing_hbr_rbr)[4][4]; 1356 const u8 (*swing_hbr3_hbr2)[4][4]; 1357 const u8 (*pre_emphasis_hbr_rbr)[4][4]; 1358 const u8 (*pre_emphasis_hbr3_hbr2)[4][4]; 1359 1360 /* DP PHY callbacks */ 1361 int (*configure_dp_phy)(struct qmp_combo *qmp); 1362 void (*configure_dp_tx)(struct qmp_combo *qmp); 1363 int (*calibrate_dp_phy)(struct qmp_combo *qmp); 1364 void (*dp_aux_init)(struct qmp_combo *qmp); 1365 1366 /* resets to be requested */ 1367 const char * const *reset_list; 1368 int num_resets; 1369 /* regulators to be requested */ 1370 const struct qmp_regulator_data *vreg_list; 1371 int num_vregs; 1372 1373 /* array of registers with different offsets */ 1374 const unsigned int *regs; 1375 1376 /* true, if PHY needs delay after POWER_DOWN */ 1377 bool has_pwrdn_delay; 1378 1379 /* Offset from PCS to PCS_USB region */ 1380 unsigned int pcs_usb_offset; 1381 1382 }; 1383 1384 struct qmp_combo { 1385 struct device *dev; 1386 1387 const struct qmp_phy_cfg *cfg; 1388 1389 void __iomem *com; 1390 1391 void __iomem *serdes; 1392 void __iomem *tx; 1393 void __iomem *rx; 1394 void __iomem *pcs; 1395 void __iomem *tx2; 1396 void __iomem *rx2; 1397 void __iomem *pcs_misc; 1398 void __iomem *pcs_usb; 1399 1400 void __iomem *dp_serdes; 1401 void __iomem *dp_tx; 1402 void __iomem *dp_tx2; 1403 void __iomem *dp_dp_phy; 1404 1405 struct clk *pipe_clk; 1406 struct clk_bulk_data *clks; 1407 int num_clks; 1408 struct reset_control_bulk_data *resets; 1409 struct regulator_bulk_data *vregs; 1410 1411 struct mutex phy_mutex; 1412 int init_count; 1413 1414 struct phy *usb_phy; 1415 enum phy_mode mode; 1416 unsigned int usb_init_count; 1417 1418 struct phy *dp_phy; 1419 unsigned int dp_aux_cfg; 1420 struct phy_configure_opts_dp dp_opts; 1421 unsigned int dp_init_count; 1422 1423 struct clk_fixed_rate pipe_clk_fixed; 1424 struct clk_hw dp_link_hw; 1425 struct clk_hw dp_pixel_hw; 1426 1427 struct drm_bridge bridge; 1428 1429 struct typec_switch_dev *sw; 1430 enum typec_orientation orientation; 1431 }; 1432 1433 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp); 1434 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp); 1435 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp); 1436 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp); 1437 1438 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp); 1439 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp); 1440 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp); 1441 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp); 1442 qphy_setbits(void __iomem * base,u32 offset,u32 val)1443 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1444 { 1445 u32 reg; 1446 1447 reg = readl(base + offset); 1448 reg |= val; 1449 writel(reg, base + offset); 1450 1451 /* ensure that above write is through */ 1452 readl(base + offset); 1453 } 1454 qphy_clrbits(void __iomem * base,u32 offset,u32 val)1455 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1456 { 1457 u32 reg; 1458 1459 reg = readl(base + offset); 1460 reg &= ~val; 1461 writel(reg, base + offset); 1462 1463 /* ensure that above write is through */ 1464 readl(base + offset); 1465 } 1466 1467 /* list of clocks required by phy */ 1468 static const char * const qmp_combo_phy_clk_l[] = { 1469 "aux", "cfg_ahb", "ref", "com_aux", 1470 }; 1471 1472 /* list of resets */ 1473 static const char * const msm8996_usb3phy_reset_l[] = { 1474 "phy", "common", 1475 }; 1476 1477 static const char * const sc7180_usb3phy_reset_l[] = { 1478 "phy", 1479 }; 1480 1481 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = { 1482 .com = 0x0000, 1483 .txa = 0x1200, 1484 .rxa = 0x1400, 1485 .txb = 0x1600, 1486 .rxb = 0x1800, 1487 .usb3_serdes = 0x1000, 1488 .usb3_pcs_misc = 0x1a00, 1489 .usb3_pcs = 0x1c00, 1490 .usb3_pcs_usb = 0x1f00, 1491 .dp_serdes = 0x2000, 1492 .dp_txa = 0x2200, 1493 .dp_txb = 0x2600, 1494 .dp_dp_phy = 0x2a00, 1495 }; 1496 1497 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = { 1498 .com = 0x0000, 1499 .txa = 0x0400, 1500 .rxa = 0x0600, 1501 .txb = 0x0a00, 1502 .rxb = 0x0c00, 1503 .usb3_serdes = 0x1000, 1504 .usb3_pcs_misc = 0x1200, 1505 .usb3_pcs = 0x1400, 1506 .usb3_pcs_usb = 0x1700, 1507 .dp_serdes = 0x2000, 1508 .dp_dp_phy = 0x2200, 1509 }; 1510 1511 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = { 1512 .offsets = &qmp_combo_offsets_v3, 1513 1514 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1515 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1516 .tx_tbl = qmp_v3_usb3_tx_tbl, 1517 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1518 .rx_tbl = qmp_v3_usb3_rx_tbl, 1519 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1520 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1521 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1522 1523 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1524 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1525 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1526 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1527 1528 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1529 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1530 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1531 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1532 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1533 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1534 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1535 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1536 1537 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1538 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1539 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1540 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1541 1542 .dp_aux_init = qmp_v3_dp_aux_init, 1543 .configure_dp_tx = qmp_v3_configure_dp_tx, 1544 .configure_dp_phy = qmp_v3_configure_dp_phy, 1545 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1546 1547 .reset_list = sc7180_usb3phy_reset_l, 1548 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1549 .vreg_list = qmp_phy_vreg_l, 1550 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1551 .regs = qmp_v3_usb3phy_regs_layout, 1552 1553 .has_pwrdn_delay = true, 1554 }; 1555 1556 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = { 1557 .offsets = &qmp_combo_offsets_v3, 1558 1559 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1560 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1561 .tx_tbl = qmp_v3_usb3_tx_tbl, 1562 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1563 .rx_tbl = qmp_v3_usb3_rx_tbl, 1564 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1565 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1566 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1567 1568 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1569 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1570 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1571 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1572 1573 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1574 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1575 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1576 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1577 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1578 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1579 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1580 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1581 1582 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1583 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1584 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1585 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1586 1587 .dp_aux_init = qmp_v3_dp_aux_init, 1588 .configure_dp_tx = qmp_v3_configure_dp_tx, 1589 .configure_dp_phy = qmp_v3_configure_dp_phy, 1590 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1591 1592 .reset_list = msm8996_usb3phy_reset_l, 1593 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1594 .vreg_list = qmp_phy_vreg_l, 1595 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1596 .regs = qmp_v3_usb3phy_regs_layout, 1597 1598 .has_pwrdn_delay = true, 1599 }; 1600 1601 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = { 1602 .offsets = &qmp_combo_offsets_v3, 1603 1604 .serdes_tbl = sm8150_usb3_serdes_tbl, 1605 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1606 .tx_tbl = sm8150_usb3_tx_tbl, 1607 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 1608 .rx_tbl = sm8150_usb3_rx_tbl, 1609 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 1610 .pcs_tbl = sm8150_usb3_pcs_tbl, 1611 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1612 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 1613 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 1614 1615 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1616 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1617 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1618 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1619 1620 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1621 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1622 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1623 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1624 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1625 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1626 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1627 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1628 1629 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1630 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1631 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1632 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1633 1634 .dp_aux_init = qmp_v4_dp_aux_init, 1635 .configure_dp_tx = qmp_v4_configure_dp_tx, 1636 .configure_dp_phy = qmp_v4_configure_dp_phy, 1637 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1638 1639 .reset_list = msm8996_usb3phy_reset_l, 1640 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1641 .vreg_list = qmp_phy_vreg_l, 1642 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1643 .regs = qmp_v45_usb3phy_regs_layout, 1644 .pcs_usb_offset = 0x300, 1645 1646 .has_pwrdn_delay = true, 1647 }; 1648 1649 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = { 1650 .offsets = &qmp_combo_offsets_v5, 1651 1652 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl, 1653 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl), 1654 .tx_tbl = sc8280xp_usb43dp_tx_tbl, 1655 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl), 1656 .rx_tbl = sc8280xp_usb43dp_rx_tbl, 1657 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl), 1658 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl, 1659 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl), 1660 1661 .dp_serdes_tbl = qmp_v5_dp_serdes_tbl, 1662 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl), 1663 .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl, 1664 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl), 1665 1666 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1667 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1668 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1669 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1670 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1671 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1672 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1673 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1674 1675 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1676 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr, 1677 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1678 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1679 1680 .dp_aux_init = qmp_v4_dp_aux_init, 1681 .configure_dp_tx = qmp_v4_configure_dp_tx, 1682 .configure_dp_phy = qmp_v4_configure_dp_phy, 1683 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1684 1685 .reset_list = msm8996_usb3phy_reset_l, 1686 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1687 .vreg_list = qmp_phy_vreg_l, 1688 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1689 .regs = qmp_v5_5nm_usb3phy_regs_layout, 1690 }; 1691 1692 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = { 1693 .offsets = &qmp_combo_offsets_v3, 1694 1695 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1696 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1697 .tx_tbl = qmp_v3_usb3_tx_tbl, 1698 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1699 .rx_tbl = sm6350_usb3_rx_tbl, 1700 .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl), 1701 .pcs_tbl = sm6350_usb3_pcs_tbl, 1702 .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl), 1703 1704 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl, 1705 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl), 1706 .dp_tx_tbl = qmp_v3_dp_tx_tbl, 1707 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl), 1708 1709 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr, 1710 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr), 1711 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr, 1712 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr), 1713 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2, 1714 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2), 1715 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3, 1716 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3), 1717 1718 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1719 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1720 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1721 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1722 1723 .dp_aux_init = qmp_v3_dp_aux_init, 1724 .configure_dp_tx = qmp_v3_configure_dp_tx, 1725 .configure_dp_phy = qmp_v3_configure_dp_phy, 1726 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy, 1727 1728 .reset_list = msm8996_usb3phy_reset_l, 1729 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1730 .vreg_list = qmp_phy_vreg_l, 1731 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1732 .regs = qmp_v3_usb3phy_regs_layout, 1733 }; 1734 1735 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = { 1736 .offsets = &qmp_combo_offsets_v3, 1737 1738 .serdes_tbl = sm8150_usb3_serdes_tbl, 1739 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1740 .tx_tbl = sm8250_usb3_tx_tbl, 1741 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 1742 .rx_tbl = sm8250_usb3_rx_tbl, 1743 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 1744 .pcs_tbl = sm8250_usb3_pcs_tbl, 1745 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 1746 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 1747 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 1748 1749 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1750 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1751 .dp_tx_tbl = qmp_v4_dp_tx_tbl, 1752 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl), 1753 1754 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1755 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1756 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1757 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1758 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1759 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1760 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1761 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1762 1763 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr, 1764 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr, 1765 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1766 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2, 1767 1768 .dp_aux_init = qmp_v4_dp_aux_init, 1769 .configure_dp_tx = qmp_v4_configure_dp_tx, 1770 .configure_dp_phy = qmp_v4_configure_dp_phy, 1771 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1772 1773 .reset_list = msm8996_usb3phy_reset_l, 1774 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1775 .vreg_list = qmp_phy_vreg_l, 1776 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1777 .regs = qmp_v45_usb3phy_regs_layout, 1778 .pcs_usb_offset = 0x300, 1779 1780 .has_pwrdn_delay = true, 1781 }; 1782 1783 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = { 1784 .offsets = &qmp_combo_offsets_v3, 1785 1786 .serdes_tbl = sm8150_usb3_serdes_tbl, 1787 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1788 .tx_tbl = sm8350_usb3_tx_tbl, 1789 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), 1790 .rx_tbl = sm8350_usb3_rx_tbl, 1791 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), 1792 .pcs_tbl = sm8350_usb3_pcs_tbl, 1793 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), 1794 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl, 1795 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), 1796 1797 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl, 1798 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl), 1799 .dp_tx_tbl = qmp_v5_dp_tx_tbl, 1800 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl), 1801 1802 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr, 1803 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr), 1804 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr, 1805 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr), 1806 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2, 1807 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2), 1808 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3, 1809 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3), 1810 1811 .swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr, 1812 .pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr, 1813 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2, 1814 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2, 1815 1816 .dp_aux_init = qmp_v4_dp_aux_init, 1817 .configure_dp_tx = qmp_v4_configure_dp_tx, 1818 .configure_dp_phy = qmp_v4_configure_dp_phy, 1819 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1820 1821 .reset_list = msm8996_usb3phy_reset_l, 1822 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1823 .vreg_list = qmp_phy_vreg_l, 1824 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1825 .regs = qmp_v45_usb3phy_regs_layout, 1826 1827 .has_pwrdn_delay = true, 1828 }; 1829 1830 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = { 1831 .offsets = &qmp_combo_offsets_v3, 1832 1833 .serdes_tbl = sm8550_usb3_serdes_tbl, 1834 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl), 1835 .tx_tbl = sm8550_usb3_tx_tbl, 1836 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl), 1837 .rx_tbl = sm8550_usb3_rx_tbl, 1838 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl), 1839 .pcs_tbl = sm8550_usb3_pcs_tbl, 1840 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl), 1841 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl, 1842 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl), 1843 1844 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl, 1845 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl), 1846 .dp_tx_tbl = qmp_v6_dp_tx_tbl, 1847 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl), 1848 1849 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr, 1850 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr), 1851 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr, 1852 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr), 1853 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2, 1854 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2), 1855 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3, 1856 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3), 1857 1858 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr, 1859 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr, 1860 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2, 1861 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2, 1862 1863 .dp_aux_init = qmp_v4_dp_aux_init, 1864 .configure_dp_tx = qmp_v4_configure_dp_tx, 1865 .configure_dp_phy = qmp_v4_configure_dp_phy, 1866 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy, 1867 1868 .regs = qmp_v6_usb3phy_regs_layout, 1869 .reset_list = msm8996_usb3phy_reset_l, 1870 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1871 .vreg_list = qmp_phy_vreg_l, 1872 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1873 }; 1874 qmp_combo_configure_lane(void __iomem * base,const struct qmp_phy_init_tbl tbl[],int num,u8 lane_mask)1875 static void qmp_combo_configure_lane(void __iomem *base, 1876 const struct qmp_phy_init_tbl tbl[], 1877 int num, 1878 u8 lane_mask) 1879 { 1880 int i; 1881 const struct qmp_phy_init_tbl *t = tbl; 1882 1883 if (!t) 1884 return; 1885 1886 for (i = 0; i < num; i++, t++) { 1887 if (!(t->lane_mask & lane_mask)) 1888 continue; 1889 1890 writel(t->val, base + t->offset); 1891 } 1892 } 1893 qmp_combo_configure(void __iomem * base,const struct qmp_phy_init_tbl tbl[],int num)1894 static void qmp_combo_configure(void __iomem *base, 1895 const struct qmp_phy_init_tbl tbl[], 1896 int num) 1897 { 1898 qmp_combo_configure_lane(base, tbl, num, 0xff); 1899 } 1900 qmp_combo_dp_serdes_init(struct qmp_combo * qmp)1901 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp) 1902 { 1903 const struct qmp_phy_cfg *cfg = qmp->cfg; 1904 void __iomem *serdes = qmp->dp_serdes; 1905 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1906 1907 qmp_combo_configure(serdes, cfg->dp_serdes_tbl, cfg->dp_serdes_tbl_num); 1908 1909 switch (dp_opts->link_rate) { 1910 case 1620: 1911 qmp_combo_configure(serdes, cfg->serdes_tbl_rbr, 1912 cfg->serdes_tbl_rbr_num); 1913 break; 1914 case 2700: 1915 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr, 1916 cfg->serdes_tbl_hbr_num); 1917 break; 1918 case 5400: 1919 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr2, 1920 cfg->serdes_tbl_hbr2_num); 1921 break; 1922 case 8100: 1923 qmp_combo_configure(serdes, cfg->serdes_tbl_hbr3, 1924 cfg->serdes_tbl_hbr3_num); 1925 break; 1926 default: 1927 /* Other link rates aren't supported */ 1928 return -EINVAL; 1929 } 1930 1931 return 0; 1932 } 1933 qmp_v3_dp_aux_init(struct qmp_combo * qmp)1934 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp) 1935 { 1936 const struct qmp_phy_cfg *cfg = qmp->cfg; 1937 1938 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1939 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 1940 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1941 1942 /* Turn on BIAS current for PHY/PLL */ 1943 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX | 1944 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL, 1945 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 1946 1947 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1948 1949 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 1950 DP_PHY_PD_CTL_LANE_0_1_PWRDN | 1951 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN | 1952 DP_PHY_PD_CTL_DP_CLAMP_EN, 1953 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 1954 1955 writel(QSERDES_V3_COM_BIAS_EN | 1956 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN | 1957 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL | 1958 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L, 1959 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 1960 1961 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 1962 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 1963 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 1964 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 1965 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 1966 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 1967 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 1968 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 1969 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 1970 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 1971 qmp->dp_aux_cfg = 0; 1972 1973 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 1974 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 1975 PHY_AUX_REQ_ERR_MASK, 1976 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); 1977 } 1978 qmp_combo_configure_dp_swing(struct qmp_combo * qmp)1979 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp) 1980 { 1981 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 1982 const struct qmp_phy_cfg *cfg = qmp->cfg; 1983 unsigned int v_level = 0, p_level = 0; 1984 u8 voltage_swing_cfg, pre_emphasis_cfg; 1985 int i; 1986 1987 for (i = 0; i < dp_opts->lanes; i++) { 1988 v_level = max(v_level, dp_opts->voltage[i]); 1989 p_level = max(p_level, dp_opts->pre[i]); 1990 } 1991 1992 if (dp_opts->link_rate <= 2700) { 1993 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level]; 1994 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level]; 1995 } else { 1996 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level]; 1997 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level]; 1998 } 1999 2000 /* TODO: Move check to config check */ 2001 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF) 2002 return -EINVAL; 2003 2004 /* Enable MUX to use Cursor values from these registers */ 2005 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN; 2006 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; 2007 2008 writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2009 writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2010 writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2011 writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2012 2013 return 0; 2014 } 2015 qmp_v3_configure_dp_tx(struct qmp_combo * qmp)2016 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp) 2017 { 2018 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2019 u32 bias_en, drvr_en; 2020 2021 if (qmp_combo_configure_dp_swing(qmp) < 0) 2022 return; 2023 2024 if (dp_opts->lanes == 1) { 2025 bias_en = 0x3e; 2026 drvr_en = 0x13; 2027 } else { 2028 bias_en = 0x3f; 2029 drvr_en = 0x10; 2030 } 2031 2032 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2033 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2034 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); 2035 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); 2036 } 2037 qmp_combo_configure_dp_mode(struct qmp_combo * qmp)2038 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) 2039 { 2040 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2041 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2042 u32 val; 2043 2044 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2045 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; 2046 2047 if (dp_opts->lanes == 4 || reverse) 2048 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN; 2049 if (dp_opts->lanes == 4 || !reverse) 2050 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN; 2051 2052 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2053 2054 if (reverse) 2055 writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 2056 else 2057 writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); 2058 2059 return reverse; 2060 } 2061 qmp_combo_configure_dp_clocks(struct qmp_combo * qmp)2062 static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp) 2063 { 2064 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2065 u32 phy_vco_div; 2066 unsigned long pixel_freq; 2067 const struct qmp_phy_cfg *cfg = qmp->cfg; 2068 2069 switch (dp_opts->link_rate) { 2070 case 1620: 2071 phy_vco_div = 0x1; 2072 pixel_freq = 1620000000UL / 2; 2073 break; 2074 case 2700: 2075 phy_vco_div = 0x1; 2076 pixel_freq = 2700000000UL / 2; 2077 break; 2078 case 5400: 2079 phy_vco_div = 0x2; 2080 pixel_freq = 5400000000UL / 4; 2081 break; 2082 case 8100: 2083 phy_vco_div = 0x0; 2084 pixel_freq = 8100000000UL / 6; 2085 break; 2086 default: 2087 /* Other link rates aren't supported */ 2088 return -EINVAL; 2089 } 2090 writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]); 2091 2092 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); 2093 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); 2094 2095 return 0; 2096 } 2097 qmp_v3_configure_dp_phy(struct qmp_combo * qmp)2098 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp) 2099 { 2100 const struct qmp_phy_cfg *cfg = qmp->cfg; 2101 u32 status; 2102 int ret; 2103 2104 qmp_combo_configure_dp_mode(qmp); 2105 2106 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); 2107 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); 2108 2109 ret = qmp_combo_configure_dp_clocks(qmp); 2110 if (ret) 2111 return ret; 2112 2113 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2114 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2115 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2116 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2117 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2118 2119 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2120 2121 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2122 status, 2123 ((status & BIT(0)) > 0), 2124 500, 2125 10000)) 2126 return -ETIMEDOUT; 2127 2128 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2129 2130 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2131 status, 2132 ((status & BIT(1)) > 0), 2133 500, 2134 10000)) 2135 return -ETIMEDOUT; 2136 2137 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2138 udelay(2000); 2139 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2140 2141 return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2142 status, 2143 ((status & BIT(1)) > 0), 2144 500, 2145 10000); 2146 } 2147 2148 /* 2149 * We need to calibrate the aux setting here as many times 2150 * as the caller tries 2151 */ qmp_v3_calibrate_dp_phy(struct qmp_combo * qmp)2152 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp) 2153 { 2154 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d }; 2155 u8 val; 2156 2157 qmp->dp_aux_cfg++; 2158 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2159 val = cfg1_settings[qmp->dp_aux_cfg]; 2160 2161 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2162 2163 return 0; 2164 } 2165 qmp_v4_dp_aux_init(struct qmp_combo * qmp)2166 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp) 2167 { 2168 const struct qmp_phy_cfg *cfg = qmp->cfg; 2169 2170 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | 2171 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, 2172 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2173 2174 /* Turn on BIAS current for PHY/PLL */ 2175 writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]); 2176 2177 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); 2178 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2179 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2180 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); 2181 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); 2182 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); 2183 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); 2184 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); 2185 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); 2186 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); 2187 qmp->dp_aux_cfg = 0; 2188 2189 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | 2190 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | 2191 PHY_AUX_REQ_ERR_MASK, 2192 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK); 2193 } 2194 qmp_v4_configure_dp_tx(struct qmp_combo * qmp)2195 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp) 2196 { 2197 const struct qmp_phy_cfg *cfg = qmp->cfg; 2198 2199 /* Program default values before writing proper values */ 2200 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2201 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2202 2203 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2204 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2205 2206 qmp_combo_configure_dp_swing(qmp); 2207 } 2208 qmp_v456_configure_dp_phy(struct qmp_combo * qmp)2209 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp) 2210 { 2211 const struct qmp_phy_cfg *cfg = qmp->cfg; 2212 u32 status; 2213 int ret; 2214 2215 writel(0x0f, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_CFG_1); 2216 2217 qmp_combo_configure_dp_mode(qmp); 2218 2219 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2220 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); 2221 2222 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL); 2223 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL); 2224 2225 ret = qmp_combo_configure_dp_clocks(qmp); 2226 if (ret) 2227 return ret; 2228 2229 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2230 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2231 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2232 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2233 2234 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]); 2235 2236 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS], 2237 status, 2238 ((status & BIT(0)) > 0), 2239 500, 2240 10000)) 2241 return -ETIMEDOUT; 2242 2243 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2244 status, 2245 ((status & BIT(0)) > 0), 2246 500, 2247 10000)) 2248 return -ETIMEDOUT; 2249 2250 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS], 2251 status, 2252 ((status & BIT(1)) > 0), 2253 500, 2254 10000)) 2255 return -ETIMEDOUT; 2256 2257 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2258 2259 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2260 status, 2261 ((status & BIT(0)) > 0), 2262 500, 2263 10000)) 2264 return -ETIMEDOUT; 2265 2266 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2267 status, 2268 ((status & BIT(1)) > 0), 2269 500, 2270 10000)) 2271 return -ETIMEDOUT; 2272 2273 return 0; 2274 } 2275 qmp_v4_configure_dp_phy(struct qmp_combo * qmp)2276 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp) 2277 { 2278 const struct qmp_phy_cfg *cfg = qmp->cfg; 2279 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE); 2280 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; 2281 u32 bias0_en, drvr0_en, bias1_en, drvr1_en; 2282 u32 status; 2283 int ret; 2284 2285 ret = qmp_v456_configure_dp_phy(qmp); 2286 if (ret < 0) 2287 return ret; 2288 2289 /* 2290 * At least for 7nm DP PHY this has to be done after enabling link 2291 * clock. 2292 */ 2293 2294 if (dp_opts->lanes == 1) { 2295 bias0_en = reverse ? 0x3e : 0x15; 2296 bias1_en = reverse ? 0x15 : 0x3e; 2297 drvr0_en = reverse ? 0x13 : 0x10; 2298 drvr1_en = reverse ? 0x10 : 0x13; 2299 } else if (dp_opts->lanes == 2) { 2300 bias0_en = reverse ? 0x3f : 0x15; 2301 bias1_en = reverse ? 0x15 : 0x3f; 2302 drvr0_en = 0x10; 2303 drvr1_en = 0x10; 2304 } else { 2305 bias0_en = 0x3f; 2306 bias1_en = 0x3f; 2307 drvr0_en = 0x10; 2308 drvr1_en = 0x10; 2309 } 2310 2311 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2312 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2313 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]); 2314 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]); 2315 2316 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2317 udelay(2000); 2318 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); 2319 2320 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS], 2321 status, 2322 ((status & BIT(1)) > 0), 2323 500, 2324 10000)) 2325 return -ETIMEDOUT; 2326 2327 writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]); 2328 writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]); 2329 2330 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2331 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]); 2332 2333 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2334 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]); 2335 2336 return 0; 2337 } 2338 2339 /* 2340 * We need to calibrate the aux setting here as many times 2341 * as the caller tries 2342 */ qmp_v4_calibrate_dp_phy(struct qmp_combo * qmp)2343 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp) 2344 { 2345 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d }; 2346 u8 val; 2347 2348 qmp->dp_aux_cfg++; 2349 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings); 2350 val = cfg1_settings[qmp->dp_aux_cfg]; 2351 2352 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); 2353 2354 return 0; 2355 } 2356 qmp_combo_dp_configure(struct phy * phy,union phy_configure_opts * opts)2357 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts) 2358 { 2359 const struct phy_configure_opts_dp *dp_opts = &opts->dp; 2360 struct qmp_combo *qmp = phy_get_drvdata(phy); 2361 const struct qmp_phy_cfg *cfg = qmp->cfg; 2362 2363 mutex_lock(&qmp->phy_mutex); 2364 2365 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); 2366 if (qmp->dp_opts.set_voltages) { 2367 cfg->configure_dp_tx(qmp); 2368 qmp->dp_opts.set_voltages = 0; 2369 } 2370 2371 mutex_unlock(&qmp->phy_mutex); 2372 2373 return 0; 2374 } 2375 qmp_combo_dp_calibrate(struct phy * phy)2376 static int qmp_combo_dp_calibrate(struct phy *phy) 2377 { 2378 struct qmp_combo *qmp = phy_get_drvdata(phy); 2379 const struct qmp_phy_cfg *cfg = qmp->cfg; 2380 int ret = 0; 2381 2382 mutex_lock(&qmp->phy_mutex); 2383 2384 if (cfg->calibrate_dp_phy) 2385 ret = cfg->calibrate_dp_phy(qmp); 2386 2387 mutex_unlock(&qmp->phy_mutex); 2388 2389 return ret; 2390 } 2391 qmp_combo_com_init(struct qmp_combo * qmp,bool force)2392 static int qmp_combo_com_init(struct qmp_combo *qmp, bool force) 2393 { 2394 const struct qmp_phy_cfg *cfg = qmp->cfg; 2395 void __iomem *com = qmp->com; 2396 int ret; 2397 u32 val; 2398 2399 if (!force && qmp->init_count++) 2400 return 0; 2401 2402 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2403 if (ret) { 2404 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 2405 goto err_decrement_count; 2406 } 2407 2408 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2409 if (ret) { 2410 dev_err(qmp->dev, "reset assert failed\n"); 2411 goto err_disable_regulators; 2412 } 2413 2414 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2415 if (ret) { 2416 dev_err(qmp->dev, "reset deassert failed\n"); 2417 goto err_disable_regulators; 2418 } 2419 2420 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 2421 if (ret) 2422 goto err_assert_reset; 2423 2424 qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN); 2425 2426 /* override hardware control for reset of qmp phy */ 2427 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2428 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2429 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2430 2431 /* Use software based port select and switch on typec orientation */ 2432 val = SW_PORTSELECT_MUX; 2433 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE) 2434 val |= SW_PORTSELECT_VAL; 2435 writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL); 2436 writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL); 2437 2438 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 2439 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2440 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2441 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2442 2443 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 2444 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 2445 2446 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2447 SW_PWRDN); 2448 2449 return 0; 2450 2451 err_assert_reset: 2452 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2453 err_disable_regulators: 2454 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2455 err_decrement_count: 2456 qmp->init_count--; 2457 2458 return ret; 2459 } 2460 qmp_combo_com_exit(struct qmp_combo * qmp,bool force)2461 static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force) 2462 { 2463 const struct qmp_phy_cfg *cfg = qmp->cfg; 2464 2465 if (!force && --qmp->init_count) 2466 return 0; 2467 2468 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2469 2470 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2471 2472 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2473 2474 return 0; 2475 } 2476 qmp_combo_dp_init(struct phy * phy)2477 static int qmp_combo_dp_init(struct phy *phy) 2478 { 2479 struct qmp_combo *qmp = phy_get_drvdata(phy); 2480 const struct qmp_phy_cfg *cfg = qmp->cfg; 2481 int ret; 2482 2483 mutex_lock(&qmp->phy_mutex); 2484 2485 ret = qmp_combo_com_init(qmp, false); 2486 if (ret) 2487 goto out_unlock; 2488 2489 cfg->dp_aux_init(qmp); 2490 2491 qmp->dp_init_count++; 2492 2493 out_unlock: 2494 mutex_unlock(&qmp->phy_mutex); 2495 return ret; 2496 } 2497 qmp_combo_dp_exit(struct phy * phy)2498 static int qmp_combo_dp_exit(struct phy *phy) 2499 { 2500 struct qmp_combo *qmp = phy_get_drvdata(phy); 2501 2502 mutex_lock(&qmp->phy_mutex); 2503 2504 qmp_combo_com_exit(qmp, false); 2505 2506 qmp->dp_init_count--; 2507 2508 mutex_unlock(&qmp->phy_mutex); 2509 2510 return 0; 2511 } 2512 qmp_combo_dp_power_on(struct phy * phy)2513 static int qmp_combo_dp_power_on(struct phy *phy) 2514 { 2515 struct qmp_combo *qmp = phy_get_drvdata(phy); 2516 const struct qmp_phy_cfg *cfg = qmp->cfg; 2517 void __iomem *tx = qmp->dp_tx; 2518 void __iomem *tx2 = qmp->dp_tx2; 2519 2520 mutex_lock(&qmp->phy_mutex); 2521 2522 qmp_combo_dp_serdes_init(qmp); 2523 2524 qmp_combo_configure_lane(tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); 2525 qmp_combo_configure_lane(tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); 2526 2527 /* Configure special DP tx tunings */ 2528 cfg->configure_dp_tx(qmp); 2529 2530 /* Configure link rate, swing, etc. */ 2531 cfg->configure_dp_phy(qmp); 2532 2533 mutex_unlock(&qmp->phy_mutex); 2534 2535 return 0; 2536 } 2537 qmp_combo_dp_power_off(struct phy * phy)2538 static int qmp_combo_dp_power_off(struct phy *phy) 2539 { 2540 struct qmp_combo *qmp = phy_get_drvdata(phy); 2541 2542 mutex_lock(&qmp->phy_mutex); 2543 2544 /* Assert DP PHY power down */ 2545 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); 2546 2547 mutex_unlock(&qmp->phy_mutex); 2548 2549 return 0; 2550 } 2551 qmp_combo_usb_power_on(struct phy * phy)2552 static int qmp_combo_usb_power_on(struct phy *phy) 2553 { 2554 struct qmp_combo *qmp = phy_get_drvdata(phy); 2555 const struct qmp_phy_cfg *cfg = qmp->cfg; 2556 void __iomem *serdes = qmp->serdes; 2557 void __iomem *tx = qmp->tx; 2558 void __iomem *rx = qmp->rx; 2559 void __iomem *tx2 = qmp->tx2; 2560 void __iomem *rx2 = qmp->rx2; 2561 void __iomem *pcs = qmp->pcs; 2562 void __iomem *pcs_usb = qmp->pcs_usb; 2563 void __iomem *status; 2564 unsigned int val; 2565 int ret; 2566 2567 qmp_combo_configure(serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); 2568 2569 ret = clk_prepare_enable(qmp->pipe_clk); 2570 if (ret) { 2571 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2572 return ret; 2573 } 2574 2575 /* Tx, Rx, and PCS configurations */ 2576 qmp_combo_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2577 qmp_combo_configure_lane(tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 2578 2579 qmp_combo_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2580 qmp_combo_configure_lane(rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 2581 2582 qmp_combo_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2583 2584 if (pcs_usb) 2585 qmp_combo_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num); 2586 2587 if (cfg->has_pwrdn_delay) 2588 usleep_range(10, 20); 2589 2590 /* Pull PHY out of reset state */ 2591 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2592 2593 /* start SerDes and Phy-Coding-Sublayer */ 2594 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2595 2596 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2597 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 2598 PHY_INIT_COMPLETE_TIMEOUT); 2599 if (ret) { 2600 dev_err(qmp->dev, "phy initialization timed-out\n"); 2601 goto err_disable_pipe_clk; 2602 } 2603 2604 return 0; 2605 2606 err_disable_pipe_clk: 2607 clk_disable_unprepare(qmp->pipe_clk); 2608 2609 return ret; 2610 } 2611 qmp_combo_usb_power_off(struct phy * phy)2612 static int qmp_combo_usb_power_off(struct phy *phy) 2613 { 2614 struct qmp_combo *qmp = phy_get_drvdata(phy); 2615 const struct qmp_phy_cfg *cfg = qmp->cfg; 2616 2617 clk_disable_unprepare(qmp->pipe_clk); 2618 2619 /* PHY reset */ 2620 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2621 2622 /* stop SerDes and Phy-Coding-Sublayer */ 2623 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2624 SERDES_START | PCS_START); 2625 2626 /* Put PHY into POWER DOWN state: active low */ 2627 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2628 SW_PWRDN); 2629 2630 return 0; 2631 } 2632 qmp_combo_usb_init(struct phy * phy)2633 static int qmp_combo_usb_init(struct phy *phy) 2634 { 2635 struct qmp_combo *qmp = phy_get_drvdata(phy); 2636 int ret; 2637 2638 mutex_lock(&qmp->phy_mutex); 2639 ret = qmp_combo_com_init(qmp, false); 2640 if (ret) 2641 goto out_unlock; 2642 2643 ret = qmp_combo_usb_power_on(phy); 2644 if (ret) { 2645 qmp_combo_com_exit(qmp, false); 2646 goto out_unlock; 2647 } 2648 2649 qmp->usb_init_count++; 2650 2651 out_unlock: 2652 mutex_unlock(&qmp->phy_mutex); 2653 return ret; 2654 } 2655 qmp_combo_usb_exit(struct phy * phy)2656 static int qmp_combo_usb_exit(struct phy *phy) 2657 { 2658 struct qmp_combo *qmp = phy_get_drvdata(phy); 2659 int ret; 2660 2661 mutex_lock(&qmp->phy_mutex); 2662 ret = qmp_combo_usb_power_off(phy); 2663 if (ret) 2664 goto out_unlock; 2665 2666 ret = qmp_combo_com_exit(qmp, false); 2667 if (ret) 2668 goto out_unlock; 2669 2670 qmp->usb_init_count--; 2671 2672 out_unlock: 2673 mutex_unlock(&qmp->phy_mutex); 2674 return ret; 2675 } 2676 qmp_combo_usb_set_mode(struct phy * phy,enum phy_mode mode,int submode)2677 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2678 { 2679 struct qmp_combo *qmp = phy_get_drvdata(phy); 2680 2681 qmp->mode = mode; 2682 2683 return 0; 2684 } 2685 2686 static const struct phy_ops qmp_combo_usb_phy_ops = { 2687 .init = qmp_combo_usb_init, 2688 .exit = qmp_combo_usb_exit, 2689 .set_mode = qmp_combo_usb_set_mode, 2690 .owner = THIS_MODULE, 2691 }; 2692 2693 static const struct phy_ops qmp_combo_dp_phy_ops = { 2694 .init = qmp_combo_dp_init, 2695 .configure = qmp_combo_dp_configure, 2696 .power_on = qmp_combo_dp_power_on, 2697 .calibrate = qmp_combo_dp_calibrate, 2698 .power_off = qmp_combo_dp_power_off, 2699 .exit = qmp_combo_dp_exit, 2700 .owner = THIS_MODULE, 2701 }; 2702 qmp_combo_enable_autonomous_mode(struct qmp_combo * qmp)2703 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp) 2704 { 2705 const struct qmp_phy_cfg *cfg = qmp->cfg; 2706 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2707 void __iomem *pcs_misc = qmp->pcs_misc; 2708 u32 intr_mask; 2709 2710 if (qmp->mode == PHY_MODE_USB_HOST_SS || 2711 qmp->mode == PHY_MODE_USB_DEVICE_SS) 2712 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2713 else 2714 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 2715 2716 /* Clear any pending interrupts status */ 2717 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2718 /* Writing 1 followed by 0 clears the interrupt */ 2719 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2720 2721 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2722 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 2723 2724 /* Enable required PHY autonomous mode interrupts */ 2725 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 2726 2727 /* Enable i/o clamp_n for autonomous mode */ 2728 if (pcs_misc) 2729 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2730 } 2731 qmp_combo_disable_autonomous_mode(struct qmp_combo * qmp)2732 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp) 2733 { 2734 const struct qmp_phy_cfg *cfg = qmp->cfg; 2735 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2736 void __iomem *pcs_misc = qmp->pcs_misc; 2737 2738 /* Disable i/o clamp_n on resume for normal mode */ 2739 if (pcs_misc) 2740 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2741 2742 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2743 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 2744 2745 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2746 /* Writing 1 followed by 0 clears the interrupt */ 2747 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2748 } 2749 qmp_combo_runtime_suspend(struct device * dev)2750 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev) 2751 { 2752 struct qmp_combo *qmp = dev_get_drvdata(dev); 2753 2754 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 2755 2756 if (!qmp->init_count) { 2757 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2758 return 0; 2759 } 2760 2761 qmp_combo_enable_autonomous_mode(qmp); 2762 2763 clk_disable_unprepare(qmp->pipe_clk); 2764 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2765 2766 return 0; 2767 } 2768 qmp_combo_runtime_resume(struct device * dev)2769 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev) 2770 { 2771 struct qmp_combo *qmp = dev_get_drvdata(dev); 2772 int ret = 0; 2773 2774 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 2775 2776 if (!qmp->init_count) { 2777 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2778 return 0; 2779 } 2780 2781 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 2782 if (ret) 2783 return ret; 2784 2785 ret = clk_prepare_enable(qmp->pipe_clk); 2786 if (ret) { 2787 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2788 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 2789 return ret; 2790 } 2791 2792 qmp_combo_disable_autonomous_mode(qmp); 2793 2794 return 0; 2795 } 2796 2797 static const struct dev_pm_ops qmp_combo_pm_ops = { 2798 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend, 2799 qmp_combo_runtime_resume, NULL) 2800 }; 2801 qmp_combo_vreg_init(struct qmp_combo * qmp)2802 static int qmp_combo_vreg_init(struct qmp_combo *qmp) 2803 { 2804 const struct qmp_phy_cfg *cfg = qmp->cfg; 2805 struct device *dev = qmp->dev; 2806 int num = cfg->num_vregs; 2807 int ret, i; 2808 2809 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2810 if (!qmp->vregs) 2811 return -ENOMEM; 2812 2813 for (i = 0; i < num; i++) 2814 qmp->vregs[i].supply = cfg->vreg_list[i].name; 2815 2816 ret = devm_regulator_bulk_get(dev, num, qmp->vregs); 2817 if (ret) { 2818 dev_err(dev, "failed at devm_regulator_bulk_get\n"); 2819 return ret; 2820 } 2821 2822 for (i = 0; i < num; i++) { 2823 ret = regulator_set_load(qmp->vregs[i].consumer, 2824 cfg->vreg_list[i].enable_load); 2825 if (ret) { 2826 dev_err(dev, "failed to set load at %s\n", 2827 qmp->vregs[i].supply); 2828 return ret; 2829 } 2830 } 2831 2832 return 0; 2833 } 2834 qmp_combo_reset_init(struct qmp_combo * qmp)2835 static int qmp_combo_reset_init(struct qmp_combo *qmp) 2836 { 2837 const struct qmp_phy_cfg *cfg = qmp->cfg; 2838 struct device *dev = qmp->dev; 2839 int i; 2840 int ret; 2841 2842 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2843 sizeof(*qmp->resets), GFP_KERNEL); 2844 if (!qmp->resets) 2845 return -ENOMEM; 2846 2847 for (i = 0; i < cfg->num_resets; i++) 2848 qmp->resets[i].id = cfg->reset_list[i]; 2849 2850 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2851 if (ret) 2852 return dev_err_probe(dev, ret, "failed to get resets\n"); 2853 2854 return 0; 2855 } 2856 qmp_combo_clk_init(struct qmp_combo * qmp)2857 static int qmp_combo_clk_init(struct qmp_combo *qmp) 2858 { 2859 struct device *dev = qmp->dev; 2860 int num = ARRAY_SIZE(qmp_combo_phy_clk_l); 2861 int i; 2862 2863 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2864 if (!qmp->clks) 2865 return -ENOMEM; 2866 2867 for (i = 0; i < num; i++) 2868 qmp->clks[i].id = qmp_combo_phy_clk_l[i]; 2869 2870 qmp->num_clks = num; 2871 2872 return devm_clk_bulk_get_optional(dev, num, qmp->clks); 2873 } 2874 phy_clk_release_provider(void * res)2875 static void phy_clk_release_provider(void *res) 2876 { 2877 of_clk_del_provider(res); 2878 } 2879 2880 /* 2881 * Register a fixed rate pipe clock. 2882 * 2883 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2884 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2885 * by the PHY driver for its operations. 2886 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2887 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2888 * Below picture shows this relationship. 2889 * 2890 * +---------------+ 2891 * | PHY block |<<---------------------------------------+ 2892 * | | | 2893 * | +-------+ | +-----+ | 2894 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2895 * clk | +-------+ | +-----+ 2896 * +---------------+ 2897 */ phy_pipe_clk_register(struct qmp_combo * qmp,struct device_node * np)2898 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np) 2899 { 2900 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2901 struct clk_init_data init = { }; 2902 char name[64]; 2903 2904 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); 2905 init.name = name; 2906 init.ops = &clk_fixed_rate_ops; 2907 2908 /* controllers using QMP phys use 125MHz pipe clock interface */ 2909 fixed->fixed_rate = 125000000; 2910 fixed->hw.init = &init; 2911 2912 return devm_clk_hw_register(qmp->dev, &fixed->hw); 2913 } 2914 2915 /* 2916 * Display Port PLL driver block diagram for branch clocks 2917 * 2918 * +------------------------------+ 2919 * | DP_VCO_CLK | 2920 * | | 2921 * | +-------------------+ | 2922 * | | (DP PLL/VCO) | | 2923 * | +---------+---------+ | 2924 * | v | 2925 * | +----------+-----------+ | 2926 * | | hsclk_divsel_clk_src | | 2927 * | +----------+-----------+ | 2928 * +------------------------------+ 2929 * | 2930 * +---------<---------v------------>----------+ 2931 * | | 2932 * +--------v----------------+ | 2933 * | dp_phy_pll_link_clk | | 2934 * | link_clk | | 2935 * +--------+----------------+ | 2936 * | | 2937 * | | 2938 * v v 2939 * Input to DISPCC block | 2940 * for link clk, crypto clk | 2941 * and interface clock | 2942 * | 2943 * | 2944 * +--------<------------+-----------------+---<---+ 2945 * | | | 2946 * +----v---------+ +--------v-----+ +--------v------+ 2947 * | vco_divided | | vco_divided | | vco_divided | 2948 * | _clk_src | | _clk_src | | _clk_src | 2949 * | | | | | | 2950 * |divsel_six | | divsel_two | | divsel_four | 2951 * +-------+------+ +-----+--------+ +--------+------+ 2952 * | | | 2953 * v---->----------v-------------<------v 2954 * | 2955 * +----------+-----------------+ 2956 * | dp_phy_pll_vco_div_clk | 2957 * +---------+------------------+ 2958 * | 2959 * v 2960 * Input to DISPCC block 2961 * for DP pixel clock 2962 * 2963 */ qmp_dp_pixel_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)2964 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 2965 { 2966 switch (req->rate) { 2967 case 1620000000UL / 2: 2968 case 2700000000UL / 2: 2969 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ 2970 return 0; 2971 default: 2972 return -EINVAL; 2973 } 2974 } 2975 qmp_dp_pixel_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2976 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 2977 { 2978 const struct qmp_combo *qmp; 2979 const struct phy_configure_opts_dp *dp_opts; 2980 2981 qmp = container_of(hw, struct qmp_combo, dp_pixel_hw); 2982 dp_opts = &qmp->dp_opts; 2983 2984 switch (dp_opts->link_rate) { 2985 case 1620: 2986 return 1620000000UL / 2; 2987 case 2700: 2988 return 2700000000UL / 2; 2989 case 5400: 2990 return 5400000000UL / 4; 2991 case 8100: 2992 return 8100000000UL / 6; 2993 default: 2994 return 0; 2995 } 2996 } 2997 2998 static const struct clk_ops qmp_dp_pixel_clk_ops = { 2999 .determine_rate = qmp_dp_pixel_clk_determine_rate, 3000 .recalc_rate = qmp_dp_pixel_clk_recalc_rate, 3001 }; 3002 qmp_dp_link_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)3003 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req) 3004 { 3005 switch (req->rate) { 3006 case 162000000: 3007 case 270000000: 3008 case 540000000: 3009 case 810000000: 3010 return 0; 3011 default: 3012 return -EINVAL; 3013 } 3014 } 3015 qmp_dp_link_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)3016 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 3017 { 3018 const struct qmp_combo *qmp; 3019 const struct phy_configure_opts_dp *dp_opts; 3020 3021 qmp = container_of(hw, struct qmp_combo, dp_link_hw); 3022 dp_opts = &qmp->dp_opts; 3023 3024 switch (dp_opts->link_rate) { 3025 case 1620: 3026 case 2700: 3027 case 5400: 3028 case 8100: 3029 return dp_opts->link_rate * 100000; 3030 default: 3031 return 0; 3032 } 3033 } 3034 3035 static const struct clk_ops qmp_dp_link_clk_ops = { 3036 .determine_rate = qmp_dp_link_clk_determine_rate, 3037 .recalc_rate = qmp_dp_link_clk_recalc_rate, 3038 }; 3039 qmp_dp_clks_hw_get(struct of_phandle_args * clkspec,void * data)3040 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data) 3041 { 3042 struct qmp_combo *qmp = data; 3043 unsigned int idx = clkspec->args[0]; 3044 3045 if (idx >= 2) { 3046 pr_err("%s: invalid index %u\n", __func__, idx); 3047 return ERR_PTR(-EINVAL); 3048 } 3049 3050 if (idx == 0) 3051 return &qmp->dp_link_hw; 3052 3053 return &qmp->dp_pixel_hw; 3054 } 3055 phy_dp_clks_register(struct qmp_combo * qmp,struct device_node * np)3056 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np) 3057 { 3058 struct clk_init_data init = { }; 3059 char name[64]; 3060 int ret; 3061 3062 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); 3063 init.ops = &qmp_dp_link_clk_ops; 3064 init.name = name; 3065 qmp->dp_link_hw.init = &init; 3066 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); 3067 if (ret) 3068 return ret; 3069 3070 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); 3071 init.ops = &qmp_dp_pixel_clk_ops; 3072 init.name = name; 3073 qmp->dp_pixel_hw.init = &init; 3074 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); 3075 if (ret) 3076 return ret; 3077 3078 return 0; 3079 } 3080 qmp_combo_clk_hw_get(struct of_phandle_args * clkspec,void * data)3081 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data) 3082 { 3083 struct qmp_combo *qmp = data; 3084 3085 switch (clkspec->args[0]) { 3086 case QMP_USB43DP_USB3_PIPE_CLK: 3087 return &qmp->pipe_clk_fixed.hw; 3088 case QMP_USB43DP_DP_LINK_CLK: 3089 return &qmp->dp_link_hw; 3090 case QMP_USB43DP_DP_VCO_DIV_CLK: 3091 return &qmp->dp_pixel_hw; 3092 } 3093 3094 return ERR_PTR(-EINVAL); 3095 } 3096 qmp_combo_register_clocks(struct qmp_combo * qmp,struct device_node * usb_np,struct device_node * dp_np)3097 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np, 3098 struct device_node *dp_np) 3099 { 3100 int ret; 3101 3102 ret = phy_pipe_clk_register(qmp, usb_np); 3103 if (ret) 3104 return ret; 3105 3106 ret = phy_dp_clks_register(qmp, dp_np); 3107 if (ret) 3108 return ret; 3109 3110 /* 3111 * Register a single provider for bindings without child nodes. 3112 */ 3113 if (usb_np == qmp->dev->of_node) 3114 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp); 3115 3116 /* 3117 * Register multiple providers for legacy bindings with child nodes. 3118 */ 3119 ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get, 3120 &qmp->pipe_clk_fixed.hw); 3121 if (ret) 3122 return ret; 3123 3124 /* 3125 * Roll a devm action because the clock provider is the child node, but 3126 * the child node is not actually a device. 3127 */ 3128 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np); 3129 if (ret) 3130 return ret; 3131 3132 ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp); 3133 if (ret) 3134 return ret; 3135 3136 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np); 3137 } 3138 3139 #if IS_ENABLED(CONFIG_TYPEC) qmp_combo_typec_switch_set(struct typec_switch_dev * sw,enum typec_orientation orientation)3140 static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw, 3141 enum typec_orientation orientation) 3142 { 3143 struct qmp_combo *qmp = typec_switch_get_drvdata(sw); 3144 const struct qmp_phy_cfg *cfg = qmp->cfg; 3145 3146 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE) 3147 return 0; 3148 3149 mutex_lock(&qmp->phy_mutex); 3150 qmp->orientation = orientation; 3151 3152 if (qmp->init_count) { 3153 if (qmp->usb_init_count) 3154 qmp_combo_usb_power_off(qmp->usb_phy); 3155 qmp_combo_com_exit(qmp, true); 3156 3157 qmp_combo_com_init(qmp, true); 3158 if (qmp->usb_init_count) 3159 qmp_combo_usb_power_on(qmp->usb_phy); 3160 if (qmp->dp_init_count) 3161 cfg->dp_aux_init(qmp); 3162 } 3163 mutex_unlock(&qmp->phy_mutex); 3164 3165 return 0; 3166 } 3167 qmp_combo_typec_unregister(void * data)3168 static void qmp_combo_typec_unregister(void *data) 3169 { 3170 struct qmp_combo *qmp = data; 3171 3172 typec_switch_unregister(qmp->sw); 3173 } 3174 qmp_combo_typec_switch_register(struct qmp_combo * qmp)3175 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp) 3176 { 3177 struct typec_switch_desc sw_desc = {}; 3178 struct device *dev = qmp->dev; 3179 3180 sw_desc.drvdata = qmp; 3181 sw_desc.fwnode = dev->fwnode; 3182 sw_desc.set = qmp_combo_typec_switch_set; 3183 qmp->sw = typec_switch_register(dev, &sw_desc); 3184 if (IS_ERR(qmp->sw)) { 3185 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw); 3186 return PTR_ERR(qmp->sw); 3187 } 3188 3189 return devm_add_action_or_reset(dev, qmp_combo_typec_unregister, qmp); 3190 } 3191 #else qmp_combo_typec_switch_register(struct qmp_combo * qmp)3192 static int qmp_combo_typec_switch_register(struct qmp_combo *qmp) 3193 { 3194 return 0; 3195 } 3196 #endif 3197 3198 #if IS_ENABLED(CONFIG_DRM) qmp_combo_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)3199 static int qmp_combo_bridge_attach(struct drm_bridge *bridge, 3200 enum drm_bridge_attach_flags flags) 3201 { 3202 struct qmp_combo *qmp = container_of(bridge, struct qmp_combo, bridge); 3203 struct drm_bridge *next_bridge; 3204 3205 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 3206 return -EINVAL; 3207 3208 next_bridge = devm_drm_of_get_bridge(qmp->dev, qmp->dev->of_node, 0, 0); 3209 if (IS_ERR(next_bridge)) { 3210 dev_err(qmp->dev, "failed to acquire drm_bridge: %pe\n", next_bridge); 3211 return PTR_ERR(next_bridge); 3212 } 3213 3214 return drm_bridge_attach(bridge->encoder, next_bridge, bridge, 3215 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 3216 } 3217 3218 static const struct drm_bridge_funcs qmp_combo_bridge_funcs = { 3219 .attach = qmp_combo_bridge_attach, 3220 }; 3221 qmp_combo_dp_register_bridge(struct qmp_combo * qmp)3222 static int qmp_combo_dp_register_bridge(struct qmp_combo *qmp) 3223 { 3224 qmp->bridge.funcs = &qmp_combo_bridge_funcs; 3225 qmp->bridge.of_node = qmp->dev->of_node; 3226 3227 return devm_drm_bridge_add(qmp->dev, &qmp->bridge); 3228 } 3229 #else qmp_combo_dp_register_bridge(struct qmp_combo * qmp)3230 static int qmp_combo_dp_register_bridge(struct qmp_combo *qmp) 3231 { 3232 return 0; 3233 } 3234 #endif 3235 qmp_combo_parse_dt_lecacy_dp(struct qmp_combo * qmp,struct device_node * np)3236 static int qmp_combo_parse_dt_lecacy_dp(struct qmp_combo *qmp, struct device_node *np) 3237 { 3238 struct device *dev = qmp->dev; 3239 3240 /* 3241 * Get memory resources from the DP child node: 3242 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3243 * tx2 -> 3; rx2 -> 4 3244 * 3245 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP 3246 * implementation. 3247 */ 3248 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL); 3249 if (IS_ERR(qmp->dp_tx)) 3250 return PTR_ERR(qmp->dp_tx); 3251 3252 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL); 3253 if (IS_ERR(qmp->dp_dp_phy)) 3254 return PTR_ERR(qmp->dp_dp_phy); 3255 3256 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL); 3257 if (IS_ERR(qmp->dp_tx2)) 3258 return PTR_ERR(qmp->dp_tx2); 3259 3260 return 0; 3261 } 3262 qmp_combo_parse_dt_lecacy_usb(struct qmp_combo * qmp,struct device_node * np)3263 static int qmp_combo_parse_dt_lecacy_usb(struct qmp_combo *qmp, struct device_node *np) 3264 { 3265 const struct qmp_phy_cfg *cfg = qmp->cfg; 3266 struct device *dev = qmp->dev; 3267 3268 /* 3269 * Get memory resources from the USB child node: 3270 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2; 3271 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5 3272 */ 3273 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 3274 if (IS_ERR(qmp->tx)) 3275 return PTR_ERR(qmp->tx); 3276 3277 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 3278 if (IS_ERR(qmp->rx)) 3279 return PTR_ERR(qmp->rx); 3280 3281 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 3282 if (IS_ERR(qmp->pcs)) 3283 return PTR_ERR(qmp->pcs); 3284 3285 if (cfg->pcs_usb_offset) 3286 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 3287 3288 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 3289 if (IS_ERR(qmp->tx2)) 3290 return PTR_ERR(qmp->tx2); 3291 3292 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 3293 if (IS_ERR(qmp->rx2)) 3294 return PTR_ERR(qmp->rx2); 3295 3296 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 3297 if (IS_ERR(qmp->pcs_misc)) { 3298 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 3299 qmp->pcs_misc = NULL; 3300 } 3301 3302 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 3303 if (IS_ERR(qmp->pipe_clk)) { 3304 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3305 "failed to get pipe clock\n"); 3306 } 3307 3308 return 0; 3309 } 3310 qmp_combo_parse_dt_legacy(struct qmp_combo * qmp,struct device_node * usb_np,struct device_node * dp_np)3311 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np, 3312 struct device_node *dp_np) 3313 { 3314 struct platform_device *pdev = to_platform_device(qmp->dev); 3315 int ret; 3316 3317 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 3318 if (IS_ERR(qmp->serdes)) 3319 return PTR_ERR(qmp->serdes); 3320 3321 qmp->com = devm_platform_ioremap_resource(pdev, 1); 3322 if (IS_ERR(qmp->com)) 3323 return PTR_ERR(qmp->com); 3324 3325 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2); 3326 if (IS_ERR(qmp->dp_serdes)) 3327 return PTR_ERR(qmp->dp_serdes); 3328 3329 ret = qmp_combo_parse_dt_lecacy_usb(qmp, usb_np); 3330 if (ret) 3331 return ret; 3332 3333 ret = qmp_combo_parse_dt_lecacy_dp(qmp, dp_np); 3334 if (ret) 3335 return ret; 3336 3337 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks); 3338 if (ret < 0) 3339 return ret; 3340 3341 qmp->num_clks = ret; 3342 3343 return 0; 3344 } 3345 qmp_combo_parse_dt(struct qmp_combo * qmp)3346 static int qmp_combo_parse_dt(struct qmp_combo *qmp) 3347 { 3348 struct platform_device *pdev = to_platform_device(qmp->dev); 3349 const struct qmp_phy_cfg *cfg = qmp->cfg; 3350 const struct qmp_combo_offsets *offs = cfg->offsets; 3351 struct device *dev = qmp->dev; 3352 void __iomem *base; 3353 int ret; 3354 3355 if (!offs) 3356 return -EINVAL; 3357 3358 base = devm_platform_ioremap_resource(pdev, 0); 3359 if (IS_ERR(base)) 3360 return PTR_ERR(base); 3361 3362 qmp->com = base + offs->com; 3363 qmp->tx = base + offs->txa; 3364 qmp->rx = base + offs->rxa; 3365 qmp->tx2 = base + offs->txb; 3366 qmp->rx2 = base + offs->rxb; 3367 3368 qmp->serdes = base + offs->usb3_serdes; 3369 qmp->pcs_misc = base + offs->usb3_pcs_misc; 3370 qmp->pcs = base + offs->usb3_pcs; 3371 qmp->pcs_usb = base + offs->usb3_pcs_usb; 3372 3373 qmp->dp_serdes = base + offs->dp_serdes; 3374 if (offs->dp_txa) { 3375 qmp->dp_tx = base + offs->dp_txa; 3376 qmp->dp_tx2 = base + offs->dp_txb; 3377 } else { 3378 qmp->dp_tx = base + offs->txa; 3379 qmp->dp_tx2 = base + offs->txb; 3380 } 3381 qmp->dp_dp_phy = base + offs->dp_dp_phy; 3382 3383 ret = qmp_combo_clk_init(qmp); 3384 if (ret) 3385 return ret; 3386 3387 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe"); 3388 if (IS_ERR(qmp->pipe_clk)) { 3389 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 3390 "failed to get usb3_pipe clock\n"); 3391 } 3392 3393 return 0; 3394 } 3395 qmp_combo_phy_xlate(struct device * dev,struct of_phandle_args * args)3396 static struct phy *qmp_combo_phy_xlate(struct device *dev, struct of_phandle_args *args) 3397 { 3398 struct qmp_combo *qmp = dev_get_drvdata(dev); 3399 3400 if (args->args_count == 0) 3401 return ERR_PTR(-EINVAL); 3402 3403 switch (args->args[0]) { 3404 case QMP_USB43DP_USB3_PHY: 3405 return qmp->usb_phy; 3406 case QMP_USB43DP_DP_PHY: 3407 return qmp->dp_phy; 3408 } 3409 3410 return ERR_PTR(-EINVAL); 3411 } 3412 qmp_combo_probe(struct platform_device * pdev)3413 static int qmp_combo_probe(struct platform_device *pdev) 3414 { 3415 struct qmp_combo *qmp; 3416 struct device *dev = &pdev->dev; 3417 struct device_node *dp_np, *usb_np; 3418 struct phy_provider *phy_provider; 3419 int ret; 3420 3421 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 3422 if (!qmp) 3423 return -ENOMEM; 3424 3425 qmp->dev = dev; 3426 3427 qmp->orientation = TYPEC_ORIENTATION_NORMAL; 3428 3429 qmp->cfg = of_device_get_match_data(dev); 3430 if (!qmp->cfg) 3431 return -EINVAL; 3432 3433 mutex_init(&qmp->phy_mutex); 3434 3435 ret = qmp_combo_reset_init(qmp); 3436 if (ret) 3437 return ret; 3438 3439 ret = qmp_combo_vreg_init(qmp); 3440 if (ret) 3441 return ret; 3442 3443 ret = qmp_combo_typec_switch_register(qmp); 3444 if (ret) 3445 return ret; 3446 3447 ret = qmp_combo_dp_register_bridge(qmp); 3448 if (ret) 3449 return ret; 3450 3451 /* Check for legacy binding with child nodes. */ 3452 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy"); 3453 if (usb_np) { 3454 dp_np = of_get_child_by_name(dev->of_node, "dp-phy"); 3455 if (!dp_np) { 3456 of_node_put(usb_np); 3457 return -EINVAL; 3458 } 3459 3460 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np); 3461 } else { 3462 usb_np = of_node_get(dev->of_node); 3463 dp_np = of_node_get(dev->of_node); 3464 3465 ret = qmp_combo_parse_dt(qmp); 3466 } 3467 if (ret) 3468 goto err_node_put; 3469 3470 pm_runtime_set_active(dev); 3471 ret = devm_pm_runtime_enable(dev); 3472 if (ret) 3473 goto err_node_put; 3474 /* 3475 * Prevent runtime pm from being ON by default. Users can enable 3476 * it using power/control in sysfs. 3477 */ 3478 pm_runtime_forbid(dev); 3479 3480 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np); 3481 if (ret) 3482 goto err_node_put; 3483 3484 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops); 3485 if (IS_ERR(qmp->usb_phy)) { 3486 ret = PTR_ERR(qmp->usb_phy); 3487 dev_err(dev, "failed to create USB PHY: %d\n", ret); 3488 goto err_node_put; 3489 } 3490 3491 phy_set_drvdata(qmp->usb_phy, qmp); 3492 3493 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops); 3494 if (IS_ERR(qmp->dp_phy)) { 3495 ret = PTR_ERR(qmp->dp_phy); 3496 dev_err(dev, "failed to create DP PHY: %d\n", ret); 3497 goto err_node_put; 3498 } 3499 3500 phy_set_drvdata(qmp->dp_phy, qmp); 3501 3502 dev_set_drvdata(dev, qmp); 3503 3504 if (usb_np == dev->of_node) 3505 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate); 3506 else 3507 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 3508 3509 of_node_put(usb_np); 3510 of_node_put(dp_np); 3511 3512 return PTR_ERR_OR_ZERO(phy_provider); 3513 3514 err_node_put: 3515 of_node_put(usb_np); 3516 of_node_put(dp_np); 3517 return ret; 3518 } 3519 3520 static const struct of_device_id qmp_combo_of_match_table[] = { 3521 { 3522 .compatible = "qcom,sc7180-qmp-usb3-dp-phy", 3523 .data = &sc7180_usb3dpphy_cfg, 3524 }, 3525 { 3526 .compatible = "qcom,sc7280-qmp-usb3-dp-phy", 3527 .data = &sm8250_usb3dpphy_cfg, 3528 }, 3529 { 3530 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy", 3531 .data = &sc8180x_usb3dpphy_cfg, 3532 }, 3533 { 3534 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy", 3535 .data = &sc8280xp_usb43dpphy_cfg, 3536 }, 3537 { 3538 .compatible = "qcom,sdm845-qmp-usb3-dp-phy", 3539 .data = &sdm845_usb3dpphy_cfg, 3540 }, 3541 { 3542 .compatible = "qcom,sm6350-qmp-usb3-dp-phy", 3543 .data = &sm6350_usb3dpphy_cfg, 3544 }, 3545 { 3546 .compatible = "qcom,sm8150-qmp-usb3-dp-phy", 3547 .data = &sc8180x_usb3dpphy_cfg, 3548 }, 3549 { 3550 .compatible = "qcom,sm8250-qmp-usb3-dp-phy", 3551 .data = &sm8250_usb3dpphy_cfg, 3552 }, 3553 { 3554 .compatible = "qcom,sm8350-qmp-usb3-dp-phy", 3555 .data = &sm8350_usb3dpphy_cfg, 3556 }, 3557 { 3558 .compatible = "qcom,sm8450-qmp-usb3-dp-phy", 3559 .data = &sm8350_usb3dpphy_cfg, 3560 }, 3561 { 3562 .compatible = "qcom,sm8550-qmp-usb3-dp-phy", 3563 .data = &sm8550_usb3dpphy_cfg, 3564 }, 3565 { } 3566 }; 3567 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table); 3568 3569 static struct platform_driver qmp_combo_driver = { 3570 .probe = qmp_combo_probe, 3571 .driver = { 3572 .name = "qcom-qmp-combo-phy", 3573 .pm = &qmp_combo_pm_ops, 3574 .of_match_table = qmp_combo_of_match_table, 3575 }, 3576 }; 3577 3578 module_platform_driver(qmp_combo_driver); 3579 3580 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 3581 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver"); 3582 MODULE_LICENSE("GPL v2"); 3583