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Searched defs:divn (Results 1 – 11 of 11) sorted by relevance

/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll-base-ld20.c32 unsigned int ssc_rate, unsigned int divn) in uniphier_ld20_sscpll_init()
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dcpu.c170 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, in pllx_set_rate()
H A Dclock.c89 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, in clock_ll_read_pll()
113 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, in clock_start_pll()
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dwarmboot.h73 u32 divn:10; member
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dwarmboot.c153 u32 divm, divn, divp, cpcon, lfcon; in warmboot_save_sdram_params() local
/openbmc/linux/drivers/media/dvb-frontends/
H A Dsi2165.c206 u8 divn = 56; /* 1..63 */ in si2165_init_pll() local
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32h7.c321 u16 divn; member
H A Dclk_stm32mp1.c863 int divm, divn; in pll_get_fvco() local
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c1066 u32 divm, divn, divp, cpcon; in clock_set_display_rate() local
/openbmc/linux/drivers/clk/tegra/
H A Dclk-pll.c1021 u32 divn = 0, divm = 0, divp = 0; in clk_plle_recalc_rate() local
/openbmc/linux/drivers/clk/
H A Dclk-stm32mp1.c842 u32 frac, divm, divn; in pll_recalc_rate() local