1 /*
2 * ARM mach-virt emulation
3 *
4 * Copyright (c) 2013 Linaro Limited
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "hw/sysbus.h"
37 #include "hw/arm/boot.h"
38 #include "hw/arm/primecell.h"
39 #include "hw/arm/virt.h"
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
43 #include "hw/display/ramfb.h"
44 #include "net/net.h"
45 #include "system/device_tree.h"
46 #include "system/numa.h"
47 #include "system/runstate.h"
48 #include "system/tpm.h"
49 #include "system/tcg.h"
50 #include "system/kvm.h"
51 #include "system/hvf.h"
52 #include "system/qtest.h"
53 #include "hw/loader.h"
54 #include "qapi/error.h"
55 #include "qemu/bitops.h"
56 #include "qemu/cutils.h"
57 #include "qemu/error-report.h"
58 #include "qemu/module.h"
59 #include "hw/pci-host/gpex.h"
60 #include "hw/pci-bridge/pci_expander_bridge.h"
61 #include "hw/virtio/virtio-pci.h"
62 #include "hw/core/sysbus-fdt.h"
63 #include "hw/platform-bus.h"
64 #include "hw/qdev-properties.h"
65 #include "hw/arm/fdt.h"
66 #include "hw/intc/arm_gic.h"
67 #include "hw/intc/arm_gicv3_common.h"
68 #include "hw/intc/arm_gicv3_its_common.h"
69 #include "hw/irq.h"
70 #include "kvm_arm.h"
71 #include "hvf_arm.h"
72 #include "hw/firmware/smbios.h"
73 #include "qapi/visitor.h"
74 #include "qapi/qapi-visit-common.h"
75 #include "qobject/qlist.h"
76 #include "standard-headers/linux/input.h"
77 #include "hw/arm/smmuv3.h"
78 #include "hw/acpi/acpi.h"
79 #include "hw/acpi/pcihp.h"
80 #include "target/arm/cpu-qom.h"
81 #include "target/arm/internals.h"
82 #include "target/arm/multiprocessing.h"
83 #include "target/arm/gtimer.h"
84 #include "hw/mem/pc-dimm.h"
85 #include "hw/mem/nvdimm.h"
86 #include "hw/acpi/generic_event_device.h"
87 #include "hw/uefi/var-service-api.h"
88 #include "hw/virtio/virtio-md-pci.h"
89 #include "hw/virtio/virtio-iommu.h"
90 #include "hw/char/pl011.h"
91 #include "hw/cxl/cxl.h"
92 #include "hw/cxl/cxl_host.h"
93 #include "qemu/guest-random.h"
94
95 static GlobalProperty arm_virt_compat[] = {
96 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" },
97 };
98 static const size_t arm_virt_compat_len = G_N_ELEMENTS(arm_virt_compat);
99
100 /*
101 * This cannot be called from the virt_machine_class_init() because
102 * TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new()
103 * only is called on virt non abstract class init.
104 */
arm_virt_compat_set(MachineClass * mc)105 static void arm_virt_compat_set(MachineClass *mc)
106 {
107 compat_props_add(mc->compat_props, arm_virt_compat,
108 arm_virt_compat_len);
109 }
110
111 #define DEFINE_VIRT_MACHINE_IMPL(latest, ...) \
112 static void MACHINE_VER_SYM(class_init, virt, __VA_ARGS__)( \
113 ObjectClass *oc, \
114 const void *data) \
115 { \
116 MachineClass *mc = MACHINE_CLASS(oc); \
117 arm_virt_compat_set(mc); \
118 MACHINE_VER_SYM(options, virt, __VA_ARGS__)(mc); \
119 mc->desc = "QEMU " MACHINE_VER_STR(__VA_ARGS__) " ARM Virtual Machine"; \
120 MACHINE_VER_DEPRECATION(__VA_ARGS__); \
121 if (latest) { \
122 mc->alias = "virt"; \
123 } \
124 } \
125 static const TypeInfo MACHINE_VER_SYM(info, virt, __VA_ARGS__) = \
126 { \
127 .name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \
128 .parent = TYPE_VIRT_MACHINE, \
129 .class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \
130 }; \
131 static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \
132 { \
133 MACHINE_VER_DELETION(__VA_ARGS__); \
134 type_register_static(&MACHINE_VER_SYM(info, virt, __VA_ARGS__)); \
135 } \
136 type_init(MACHINE_VER_SYM(register, virt, __VA_ARGS__));
137
138 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
139 DEFINE_VIRT_MACHINE_IMPL(true, major, minor)
140 #define DEFINE_VIRT_MACHINE(major, minor) \
141 DEFINE_VIRT_MACHINE_IMPL(false, major, minor)
142
143
144 /* Number of external interrupt lines to configure the GIC with */
145 #define NUM_IRQS 256
146
147 #define PLATFORM_BUS_NUM_IRQS 64
148
149 /* Legacy RAM limit in GB (< version 4.0) */
150 #define LEGACY_RAMLIMIT_GB 255
151 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
152
153 /* Addresses and sizes of our components.
154 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
155 * 128MB..256MB is used for miscellaneous device I/O.
156 * 256MB..1GB is reserved for possible future PCI support (ie where the
157 * PCI memory window will go if we add a PCI host controller).
158 * 1GB and up is RAM (which may happily spill over into the
159 * high memory region beyond 4GB).
160 * This represents a compromise between how much RAM can be given to
161 * a 32 bit VM and leaving space for expansion and in particular for PCI.
162 * Note that devices should generally be placed at multiples of 0x10000,
163 * to accommodate guests using 64K pages.
164 */
165 static const MemMapEntry base_memmap[] = {
166 /* Space up to 0x8000000 is reserved for a boot ROM */
167 [VIRT_FLASH] = { 0, 0x08000000 },
168 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
169 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
170 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
171 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
172 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
173 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
174 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
175 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
176 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
177 /* This redistributor space allows up to 2*64kB*123 CPUs */
178 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
179 [VIRT_UART0] = { 0x09000000, 0x00001000 },
180 [VIRT_RTC] = { 0x09010000, 0x00001000 },
181 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
182 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
183 [VIRT_UART1] = { 0x09040000, 0x00001000 },
184 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
185 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
186 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
187 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
188 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
189 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
190 [VIRT_ACPI_PCIHP] = { 0x090c0000, ACPI_PCIHP_SIZE },
191 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
192 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
193 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
194 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
195 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
196 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
197 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
198 /* Actual RAM size depends on initial RAM and device memory settings */
199 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
200 };
201
202 /* Update the docs for highmem-mmio-size when changing this default */
203 #define DEFAULT_HIGH_PCIE_MMIO_SIZE_GB 512
204 #define DEFAULT_HIGH_PCIE_MMIO_SIZE (DEFAULT_HIGH_PCIE_MMIO_SIZE_GB * GiB)
205
206 /*
207 * Highmem IO Regions: This memory map is floating, located after the RAM.
208 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
209 * top of the RAM, so that its base get the same alignment as the size,
210 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
211 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
212 * Note the extended_memmap is sized so that it eventually also includes the
213 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
214 * index of base_memmap).
215 *
216 * The memory map for these Highmem IO Regions can be in legacy or compact
217 * layout, depending on 'compact-highmem' property. With legacy layout, the
218 * PA space for one specific region is always reserved, even if the region
219 * has been disabled or doesn't fit into the PA space. However, the PA space
220 * for the region won't be reserved in these circumstances with compact layout.
221 *
222 * Note that the highmem-mmio-size property will update the high PCIE MMIO size
223 * field in this array.
224 */
225 static MemMapEntry extended_memmap[] = {
226 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
227 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
228 [VIRT_CXL_HOST] = { 0x0, 64 * KiB * 16 }, /* 16 UID */
229 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
230 /* Second PCIe window */
231 [VIRT_HIGH_PCIE_MMIO] = { 0x0, DEFAULT_HIGH_PCIE_MMIO_SIZE },
232 /* Any CXL Fixed memory windows come here */
233 };
234
235 static const int a15irqmap[] = {
236 [VIRT_UART0] = 1,
237 [VIRT_RTC] = 2,
238 [VIRT_PCIE] = 3, /* ... to 6 */
239 [VIRT_GPIO] = 7,
240 [VIRT_UART1] = 8,
241 [VIRT_ACPI_GED] = 9,
242 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
243 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
244 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
245 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
246 };
247
create_randomness(MachineState * ms,const char * node)248 static void create_randomness(MachineState *ms, const char *node)
249 {
250 struct {
251 uint64_t kaslr;
252 uint8_t rng[32];
253 } seed;
254
255 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
256 return;
257 }
258 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr);
259 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
260 }
261
262 /*
263 * The CPU object always exposes the NS EL2 virt timer IRQ line,
264 * but we don't want to advertise it to the guest in the dtb or ACPI
265 * table unless it's really going to do something.
266 */
ns_el2_virt_timer_present(void)267 static bool ns_el2_virt_timer_present(void)
268 {
269 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
270 CPUARMState *env = &cpu->env;
271
272 return arm_feature(env, ARM_FEATURE_AARCH64) &&
273 arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);
274 }
275
create_fdt(VirtMachineState * vms)276 static void create_fdt(VirtMachineState *vms)
277 {
278 MachineState *ms = MACHINE(vms);
279 int nb_numa_nodes = ms->numa_state->num_nodes;
280 void *fdt = create_device_tree(&vms->fdt_size);
281
282 if (!fdt) {
283 error_report("create_device_tree() failed");
284 exit(1);
285 }
286
287 ms->fdt = fdt;
288
289 /* Header */
290 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
291 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
292 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
293 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
294
295 /*
296 * For QEMU, all DMA is coherent. Advertising this in the root node
297 * has two benefits:
298 *
299 * - It avoids potential bugs where we forget to mark a DMA
300 * capable device as being dma-coherent
301 * - It avoids spurious warnings from the Linux kernel about
302 * devices which can't do DMA at all
303 */
304 qemu_fdt_setprop(fdt, "/", "dma-coherent", NULL, 0);
305
306 /* /chosen must exist for load_dtb to fill in necessary properties later */
307 qemu_fdt_add_subnode(fdt, "/chosen");
308 if (vms->dtb_randomness) {
309 create_randomness(ms, "/chosen");
310 }
311
312 if (vms->secure) {
313 qemu_fdt_add_subnode(fdt, "/secure-chosen");
314 if (vms->dtb_randomness) {
315 create_randomness(ms, "/secure-chosen");
316 }
317 }
318
319 qemu_fdt_add_subnode(fdt, "/aliases");
320
321 /* Clock node, for the benefit of the UART. The kernel device tree
322 * binding documentation claims the PL011 node clock properties are
323 * optional but in practice if you omit them the kernel refuses to
324 * probe for the device.
325 */
326 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
327 qemu_fdt_add_subnode(fdt, "/apb-pclk");
328 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
329 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
330 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
331 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
332 "clk24mhz");
333 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
334
335 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
336 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
337 uint32_t *matrix = g_malloc0(size);
338 int idx, i, j;
339
340 for (i = 0; i < nb_numa_nodes; i++) {
341 for (j = 0; j < nb_numa_nodes; j++) {
342 idx = (i * nb_numa_nodes + j) * 3;
343 matrix[idx + 0] = cpu_to_be32(i);
344 matrix[idx + 1] = cpu_to_be32(j);
345 matrix[idx + 2] =
346 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
347 }
348 }
349
350 qemu_fdt_add_subnode(fdt, "/distance-map");
351 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
352 "numa-distance-map-v1");
353 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
354 matrix, size);
355 g_free(matrix);
356 }
357 }
358
fdt_add_timer_nodes(const VirtMachineState * vms)359 static void fdt_add_timer_nodes(const VirtMachineState *vms)
360 {
361 /* On real hardware these interrupts are level-triggered.
362 * On KVM they were edge-triggered before host kernel version 4.4,
363 * and level-triggered afterwards.
364 * On emulated QEMU they are level-triggered.
365 *
366 * Getting the DTB info about them wrong is awkward for some
367 * guest kernels:
368 * pre-4.8 ignore the DT and leave the interrupt configured
369 * with whatever the GIC reset value (or the bootloader) left it at
370 * 4.8 before rc6 honour the incorrect data by programming it back
371 * into the GIC, causing problems
372 * 4.8rc6 and later ignore the DT and always write "level triggered"
373 * into the GIC
374 *
375 * For backwards-compatibility, virt-2.8 and earlier will continue
376 * to say these are edge-triggered, but later machines will report
377 * the correct information.
378 */
379 ARMCPU *armcpu;
380 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
381 MachineState *ms = MACHINE(vms);
382
383 if (vms->gic_version == VIRT_GIC_VERSION_2) {
384 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
385 GIC_FDT_IRQ_PPI_CPU_WIDTH,
386 (1 << MACHINE(vms)->smp.cpus) - 1);
387 }
388
389 qemu_fdt_add_subnode(ms->fdt, "/timer");
390
391 armcpu = ARM_CPU(qemu_get_cpu(0));
392 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
393 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
394 qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
395 compat, sizeof(compat));
396 } else {
397 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
398 "arm,armv7-timer");
399 }
400 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
401 if (vms->ns_el2_virt_timer_irq) {
402 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
403 GIC_FDT_IRQ_TYPE_PPI,
404 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
405 GIC_FDT_IRQ_TYPE_PPI,
406 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
407 GIC_FDT_IRQ_TYPE_PPI,
408 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
409 GIC_FDT_IRQ_TYPE_PPI,
410 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags,
411 GIC_FDT_IRQ_TYPE_PPI,
412 INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags);
413 } else {
414 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
415 GIC_FDT_IRQ_TYPE_PPI,
416 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
417 GIC_FDT_IRQ_TYPE_PPI,
418 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
419 GIC_FDT_IRQ_TYPE_PPI,
420 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
421 GIC_FDT_IRQ_TYPE_PPI,
422 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
423 }
424 }
425
fdt_add_cpu_nodes(const VirtMachineState * vms)426 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
427 {
428 int cpu;
429 int addr_cells = 1;
430 const MachineState *ms = MACHINE(vms);
431 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
432 int smp_cpus = ms->smp.cpus;
433
434 /*
435 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
436 * On ARM v8 64-bit systems value should be set to 2,
437 * that corresponds to the MPIDR_EL1 register size.
438 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
439 * in the system, #address-cells can be set to 1, since
440 * MPIDR_EL1[63:32] bits are not used for CPUs
441 * identification.
442 *
443 * Here we actually don't know whether our system is 32- or 64-bit one.
444 * The simplest way to go is to examine affinity IDs of all our CPUs. If
445 * at least one of them has Aff3 populated, we set #address-cells to 2.
446 */
447 for (cpu = 0; cpu < smp_cpus; cpu++) {
448 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
449
450 if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) {
451 addr_cells = 2;
452 break;
453 }
454 }
455
456 qemu_fdt_add_subnode(ms->fdt, "/cpus");
457 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
458 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
459
460 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
461 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
462 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
463 CPUState *cs = CPU(armcpu);
464
465 qemu_fdt_add_subnode(ms->fdt, nodename);
466 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
467 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
468 armcpu->dtb_compatible);
469
470 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
471 qemu_fdt_setprop_string(ms->fdt, nodename,
472 "enable-method", "psci");
473 }
474
475 if (addr_cells == 2) {
476 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
477 arm_cpu_mp_affinity(armcpu));
478 } else {
479 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
480 arm_cpu_mp_affinity(armcpu));
481 }
482
483 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
484 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
485 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
486 }
487
488 if (!vmc->no_cpu_topology) {
489 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
490 qemu_fdt_alloc_phandle(ms->fdt));
491 }
492
493 g_free(nodename);
494 }
495
496 if (!vmc->no_cpu_topology) {
497 /*
498 * Add vCPU topology description through fdt node cpu-map.
499 *
500 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
501 * In a SMP system, the hierarchy of CPUs can be defined through
502 * four entities that are used to describe the layout of CPUs in
503 * the system: socket/cluster/core/thread.
504 *
505 * A socket node represents the boundary of system physical package
506 * and its child nodes must be one or more cluster nodes. A system
507 * can contain several layers of clustering within a single physical
508 * package and cluster nodes can be contained in parent cluster nodes.
509 *
510 * Note: currently we only support one layer of clustering within
511 * each physical package.
512 */
513 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
514
515 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
516 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu);
517 char *map_path;
518
519 if (ms->smp.threads > 1) {
520 map_path = g_strdup_printf(
521 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
522 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads),
523 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters,
524 (cpu / ms->smp.threads) % ms->smp.cores,
525 cpu % ms->smp.threads);
526 } else {
527 map_path = g_strdup_printf(
528 "/cpus/cpu-map/socket%d/cluster%d/core%d",
529 cpu / (ms->smp.clusters * ms->smp.cores),
530 (cpu / ms->smp.cores) % ms->smp.clusters,
531 cpu % ms->smp.cores);
532 }
533 qemu_fdt_add_path(ms->fdt, map_path);
534 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
535
536 g_free(map_path);
537 g_free(cpu_path);
538 }
539 }
540 }
541
fdt_add_its_gic_node(VirtMachineState * vms)542 static void fdt_add_its_gic_node(VirtMachineState *vms)
543 {
544 char *nodename;
545 MachineState *ms = MACHINE(vms);
546
547 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
548 nodename = g_strdup_printf("/intc/its@%" PRIx64,
549 vms->memmap[VIRT_GIC_ITS].base);
550 qemu_fdt_add_subnode(ms->fdt, nodename);
551 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
552 "arm,gic-v3-its");
553 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
554 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
555 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
556 2, vms->memmap[VIRT_GIC_ITS].base,
557 2, vms->memmap[VIRT_GIC_ITS].size);
558 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
559 g_free(nodename);
560 }
561
fdt_add_v2m_gic_node(VirtMachineState * vms)562 static void fdt_add_v2m_gic_node(VirtMachineState *vms)
563 {
564 MachineState *ms = MACHINE(vms);
565 char *nodename;
566
567 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
568 vms->memmap[VIRT_GIC_V2M].base);
569 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
570 qemu_fdt_add_subnode(ms->fdt, nodename);
571 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
572 "arm,gic-v2m-frame");
573 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
574 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
575 2, vms->memmap[VIRT_GIC_V2M].base,
576 2, vms->memmap[VIRT_GIC_V2M].size);
577 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
578 g_free(nodename);
579 }
580
fdt_add_gic_node(VirtMachineState * vms)581 static void fdt_add_gic_node(VirtMachineState *vms)
582 {
583 MachineState *ms = MACHINE(vms);
584 char *nodename;
585
586 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
587 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
588
589 nodename = g_strdup_printf("/intc@%" PRIx64,
590 vms->memmap[VIRT_GIC_DIST].base);
591 qemu_fdt_add_subnode(ms->fdt, nodename);
592 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
593 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
594 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
595 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
596 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
597 if (vms->gic_version != VIRT_GIC_VERSION_2) {
598 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
599
600 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
601 "arm,gic-v3");
602
603 qemu_fdt_setprop_cell(ms->fdt, nodename,
604 "#redistributor-regions", nb_redist_regions);
605
606 if (nb_redist_regions == 1) {
607 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
608 2, vms->memmap[VIRT_GIC_DIST].base,
609 2, vms->memmap[VIRT_GIC_DIST].size,
610 2, vms->memmap[VIRT_GIC_REDIST].base,
611 2, vms->memmap[VIRT_GIC_REDIST].size);
612 } else {
613 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
614 2, vms->memmap[VIRT_GIC_DIST].base,
615 2, vms->memmap[VIRT_GIC_DIST].size,
616 2, vms->memmap[VIRT_GIC_REDIST].base,
617 2, vms->memmap[VIRT_GIC_REDIST].size,
618 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
619 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
620 }
621
622 if (vms->virt) {
623 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
624 GIC_FDT_IRQ_TYPE_PPI,
625 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
626 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
627 }
628 } else {
629 /* 'cortex-a15-gic' means 'GIC v2' */
630 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
631 "arm,cortex-a15-gic");
632 if (!vms->virt) {
633 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
634 2, vms->memmap[VIRT_GIC_DIST].base,
635 2, vms->memmap[VIRT_GIC_DIST].size,
636 2, vms->memmap[VIRT_GIC_CPU].base,
637 2, vms->memmap[VIRT_GIC_CPU].size);
638 } else {
639 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
640 2, vms->memmap[VIRT_GIC_DIST].base,
641 2, vms->memmap[VIRT_GIC_DIST].size,
642 2, vms->memmap[VIRT_GIC_CPU].base,
643 2, vms->memmap[VIRT_GIC_CPU].size,
644 2, vms->memmap[VIRT_GIC_HYP].base,
645 2, vms->memmap[VIRT_GIC_HYP].size,
646 2, vms->memmap[VIRT_GIC_VCPU].base,
647 2, vms->memmap[VIRT_GIC_VCPU].size);
648 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
649 GIC_FDT_IRQ_TYPE_PPI,
650 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
651 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
652 }
653 }
654
655 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
656 g_free(nodename);
657 }
658
fdt_add_pmu_nodes(const VirtMachineState * vms)659 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
660 {
661 ARMCPU *armcpu = ARM_CPU(first_cpu);
662 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
663 MachineState *ms = MACHINE(vms);
664
665 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
666 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
667 return;
668 }
669
670 if (vms->gic_version == VIRT_GIC_VERSION_2) {
671 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
672 GIC_FDT_IRQ_PPI_CPU_WIDTH,
673 (1 << MACHINE(vms)->smp.cpus) - 1);
674 }
675
676 qemu_fdt_add_subnode(ms->fdt, "/pmu");
677 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
678 const char compat[] = "arm,armv8-pmuv3";
679 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
680 compat, sizeof(compat));
681 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
682 GIC_FDT_IRQ_TYPE_PPI,
683 INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags);
684 }
685 }
686
create_acpi_ged(VirtMachineState * vms)687 static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
688 {
689 DeviceState *dev;
690 MachineState *ms = MACHINE(vms);
691 SysBusDevice *sbdev;
692 int irq = vms->irqmap[VIRT_ACPI_GED];
693 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
694 bool acpi_pcihp;
695
696 if (ms->ram_slots) {
697 event |= ACPI_GED_MEM_HOTPLUG_EVT;
698 }
699
700 if (ms->nvdimms_state->is_enabled) {
701 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
702 }
703
704 dev = qdev_new(TYPE_ACPI_GED);
705 qdev_prop_set_uint32(dev, "ged-event", event);
706 object_property_set_link(OBJECT(dev), "bus", OBJECT(vms->bus), &error_abort);
707 sbdev = SYS_BUS_DEVICE(dev);
708 sysbus_realize_and_unref(sbdev, &error_fatal);
709
710 sysbus_mmio_map_name(sbdev, TYPE_ACPI_GED, vms->memmap[VIRT_ACPI_GED].base);
711 sysbus_mmio_map_name(sbdev, ACPI_MEMHP_REGION_NAME,
712 vms->memmap[VIRT_PCDIMM_ACPI].base);
713
714 acpi_pcihp = object_property_get_bool(OBJECT(dev),
715 ACPI_PM_PROP_ACPI_PCIHP_BRIDGE, NULL);
716
717 if (acpi_pcihp) {
718 int pcihp_region_index;
719
720 pcihp_region_index = sysbus_mmio_map_name(sbdev, ACPI_PCIHP_REGION_NAME,
721 vms->memmap[VIRT_ACPI_PCIHP].base);
722 assert(pcihp_region_index >= 0);
723 }
724
725 sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(vms->gic, irq));
726
727 return dev;
728 }
729
create_its(VirtMachineState * vms)730 static void create_its(VirtMachineState *vms)
731 {
732 DeviceState *dev;
733
734 assert(vms->its);
735 if (!kvm_irqchip_in_kernel() && !vms->tcg_its) {
736 /*
737 * Do nothing if ITS is neither supported by the host nor emulated by
738 * the machine.
739 */
740 return;
741 }
742
743 dev = qdev_new(its_class_name());
744
745 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
746 &error_abort);
747 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
748 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
749
750 fdt_add_its_gic_node(vms);
751 vms->msi_controller = VIRT_MSI_CTRL_ITS;
752 }
753
create_v2m(VirtMachineState * vms)754 static void create_v2m(VirtMachineState *vms)
755 {
756 int i;
757 int irq = vms->irqmap[VIRT_GIC_V2M];
758 DeviceState *dev;
759
760 dev = qdev_new("arm-gicv2m");
761 qdev_prop_set_uint32(dev, "base-spi", irq);
762 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
763 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
764 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
765
766 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
767 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
768 qdev_get_gpio_in(vms->gic, irq + i));
769 }
770
771 fdt_add_v2m_gic_node(vms);
772 vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
773 }
774
775 /*
776 * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too.
777 * It's permitted to have a configuration with NMI in the CPU (and thus the
778 * GICv3 CPU interface) but not in the distributor/redistributors, but it's
779 * not very useful.
780 */
gicv3_nmi_present(VirtMachineState * vms)781 static bool gicv3_nmi_present(VirtMachineState *vms)
782 {
783 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
784
785 return tcg_enabled() && cpu_isar_feature(aa64_nmi, cpu) &&
786 (vms->gic_version != VIRT_GIC_VERSION_2);
787 }
788
create_gic(VirtMachineState * vms,MemoryRegion * mem)789 static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
790 {
791 MachineState *ms = MACHINE(vms);
792 /* We create a standalone GIC */
793 SysBusDevice *gicbusdev;
794 const char *gictype;
795 int i;
796 unsigned int smp_cpus = ms->smp.cpus;
797 uint32_t nb_redist_regions = 0;
798 int revision;
799
800 if (vms->gic_version == VIRT_GIC_VERSION_2) {
801 gictype = gic_class_name();
802 } else {
803 gictype = gicv3_class_name();
804 }
805
806 switch (vms->gic_version) {
807 case VIRT_GIC_VERSION_2:
808 revision = 2;
809 break;
810 case VIRT_GIC_VERSION_3:
811 revision = 3;
812 break;
813 case VIRT_GIC_VERSION_4:
814 revision = 4;
815 break;
816 default:
817 g_assert_not_reached();
818 }
819
820 if (kvm_enabled() && vms->virt &&
821 (revision != 3 || !kvm_irqchip_in_kernel())) {
822 error_report("KVM EL2 is only supported with in-kernel GICv3");
823 exit(1);
824 }
825
826 vms->gic = qdev_new(gictype);
827 qdev_prop_set_uint32(vms->gic, "revision", revision);
828 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
829 /* Note that the num-irq property counts both internal and external
830 * interrupts; there are always 32 of the former (mandated by GIC spec).
831 */
832 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
833 if (!kvm_irqchip_in_kernel()) {
834 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
835 }
836
837 if (vms->gic_version != VIRT_GIC_VERSION_2) {
838 QList *redist_region_count;
839 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST);
840 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
841
842 nb_redist_regions = virt_gicv3_redist_region_count(vms);
843
844 redist_region_count = qlist_new();
845 qlist_append_int(redist_region_count, redist0_count);
846 if (nb_redist_regions == 2) {
847 uint32_t redist1_capacity =
848 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
849
850 qlist_append_int(redist_region_count,
851 MIN(smp_cpus - redist0_count, redist1_capacity));
852 }
853 qdev_prop_set_array(vms->gic, "redist-region-count",
854 redist_region_count);
855
856 if (!kvm_irqchip_in_kernel()) {
857 if (vms->tcg_its) {
858 object_property_set_link(OBJECT(vms->gic), "sysmem",
859 OBJECT(mem), &error_fatal);
860 qdev_prop_set_bit(vms->gic, "has-lpi", true);
861 }
862 } else if (vms->virt) {
863 qdev_prop_set_uint32(vms->gic, "maintenance-interrupt-id",
864 ARCH_GIC_MAINT_IRQ);
865 }
866 } else {
867 if (!kvm_irqchip_in_kernel()) {
868 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
869 vms->virt);
870 }
871 }
872
873 if (gicv3_nmi_present(vms)) {
874 qdev_prop_set_bit(vms->gic, "has-nmi", true);
875 }
876
877 gicbusdev = SYS_BUS_DEVICE(vms->gic);
878 sysbus_realize_and_unref(gicbusdev, &error_fatal);
879 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
880 if (vms->gic_version != VIRT_GIC_VERSION_2) {
881 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
882 if (nb_redist_regions == 2) {
883 sysbus_mmio_map(gicbusdev, 2,
884 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
885 }
886 } else {
887 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
888 if (vms->virt) {
889 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
890 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
891 }
892 }
893
894 /* Wire the outputs from each CPU's generic timer and the GICv3
895 * maintenance interrupt signal to the appropriate GIC PPI inputs,
896 * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the
897 * CPU's inputs.
898 */
899 for (i = 0; i < smp_cpus; i++) {
900 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
901 int intidbase = NUM_IRQS + i * GIC_INTERNAL;
902 /* Mapping from the output timer irq lines from the CPU to the
903 * GIC PPI inputs we use for the virt board.
904 */
905 const int timer_irq[] = {
906 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
907 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
908 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
909 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
910 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
911 [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ,
912 [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ,
913 };
914
915 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
916 qdev_connect_gpio_out(cpudev, irq,
917 qdev_get_gpio_in(vms->gic,
918 intidbase + timer_irq[irq]));
919 }
920
921 if (vms->gic_version != VIRT_GIC_VERSION_2) {
922 qemu_irq irq = qdev_get_gpio_in(vms->gic,
923 intidbase + ARCH_GIC_MAINT_IRQ);
924 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
925 0, irq);
926 } else if (vms->virt) {
927 qemu_irq irq = qdev_get_gpio_in(vms->gic,
928 intidbase + ARCH_GIC_MAINT_IRQ);
929 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
930 }
931
932 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
933 qdev_get_gpio_in(vms->gic, intidbase
934 + VIRTUAL_PMU_IRQ));
935
936 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
937 sysbus_connect_irq(gicbusdev, i + smp_cpus,
938 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
939 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
940 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
941 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
942 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
943
944 if (vms->gic_version != VIRT_GIC_VERSION_2) {
945 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus,
946 qdev_get_gpio_in(cpudev, ARM_CPU_NMI));
947 sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus,
948 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI));
949 }
950 }
951
952 fdt_add_gic_node(vms);
953
954 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) {
955 create_its(vms);
956 } else if (vms->gic_version == VIRT_GIC_VERSION_2) {
957 create_v2m(vms);
958 }
959 }
960
create_uart(const VirtMachineState * vms,int uart,MemoryRegion * mem,Chardev * chr,bool secure)961 static void create_uart(const VirtMachineState *vms, int uart,
962 MemoryRegion *mem, Chardev *chr, bool secure)
963 {
964 char *nodename;
965 hwaddr base = vms->memmap[uart].base;
966 hwaddr size = vms->memmap[uart].size;
967 int irq = vms->irqmap[uart];
968 const char compat[] = "arm,pl011\0arm,primecell";
969 const char clocknames[] = "uartclk\0apb_pclk";
970 DeviceState *dev = qdev_new(TYPE_PL011);
971 SysBusDevice *s = SYS_BUS_DEVICE(dev);
972 MachineState *ms = MACHINE(vms);
973
974 qdev_prop_set_chr(dev, "chardev", chr);
975 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
976 memory_region_add_subregion(mem, base,
977 sysbus_mmio_get_region(s, 0));
978 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
979
980 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
981 qemu_fdt_add_subnode(ms->fdt, nodename);
982 /* Note that we can't use setprop_string because of the embedded NUL */
983 qemu_fdt_setprop(ms->fdt, nodename, "compatible",
984 compat, sizeof(compat));
985 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
986 2, base, 2, size);
987 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
988 GIC_FDT_IRQ_TYPE_SPI, irq,
989 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
990 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
991 vms->clock_phandle, vms->clock_phandle);
992 qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
993 clocknames, sizeof(clocknames));
994
995 if (uart == VIRT_UART0) {
996 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
997 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename);
998 } else {
999 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial1", nodename);
1000 }
1001 if (secure) {
1002 /* Mark as not usable by the normal world */
1003 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1004 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1005
1006 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
1007 nodename);
1008 }
1009
1010 g_free(nodename);
1011 }
1012
create_rtc(const VirtMachineState * vms)1013 static void create_rtc(const VirtMachineState *vms)
1014 {
1015 char *nodename;
1016 hwaddr base = vms->memmap[VIRT_RTC].base;
1017 hwaddr size = vms->memmap[VIRT_RTC].size;
1018 int irq = vms->irqmap[VIRT_RTC];
1019 const char compat[] = "arm,pl031\0arm,primecell";
1020 MachineState *ms = MACHINE(vms);
1021
1022 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
1023
1024 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
1025 qemu_fdt_add_subnode(ms->fdt, nodename);
1026 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
1027 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1028 2, base, 2, size);
1029 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1030 GIC_FDT_IRQ_TYPE_SPI, irq,
1031 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
1032 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
1033 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1034 g_free(nodename);
1035 }
1036
1037 static DeviceState *gpio_key_dev;
virt_powerdown_req(Notifier * n,void * opaque)1038 static void virt_powerdown_req(Notifier *n, void *opaque)
1039 {
1040 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
1041
1042 if (s->acpi_dev) {
1043 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
1044 } else {
1045 /* use gpio Pin for power button event */
1046 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
1047 }
1048 }
1049
create_gpio_keys(char * fdt,DeviceState * pl061_dev,uint32_t phandle)1050 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev,
1051 uint32_t phandle)
1052 {
1053 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
1054 qdev_get_gpio_in(pl061_dev,
1055 GPIO_PIN_POWER_BUTTON));
1056
1057 qemu_fdt_add_subnode(fdt, "/gpio-keys");
1058 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
1059
1060 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
1061 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
1062 "label", "GPIO Key Poweroff");
1063 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
1064 KEY_POWER);
1065 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
1066 "gpios", phandle, GPIO_PIN_POWER_BUTTON, 0);
1067 }
1068
1069 #define SECURE_GPIO_POWEROFF 0
1070 #define SECURE_GPIO_RESET 1
1071
create_secure_gpio_pwr(char * fdt,DeviceState * pl061_dev,uint32_t phandle)1072 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev,
1073 uint32_t phandle)
1074 {
1075 DeviceState *gpio_pwr_dev;
1076
1077 /* gpio-pwr */
1078 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
1079
1080 /* connect secure pl061 to gpio-pwr */
1081 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
1082 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
1083 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
1084 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
1085
1086 qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
1087 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
1088 "gpio-poweroff");
1089 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
1090 "gpios", phandle, SECURE_GPIO_POWEROFF, 0);
1091 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
1092 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
1093 "okay");
1094
1095 qemu_fdt_add_subnode(fdt, "/gpio-restart");
1096 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
1097 "gpio-restart");
1098 qemu_fdt_setprop_cells(fdt, "/gpio-restart",
1099 "gpios", phandle, SECURE_GPIO_RESET, 0);
1100 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
1101 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
1102 "okay");
1103 }
1104
create_gpio_devices(const VirtMachineState * vms,int gpio,MemoryRegion * mem)1105 static void create_gpio_devices(const VirtMachineState *vms, int gpio,
1106 MemoryRegion *mem)
1107 {
1108 char *nodename;
1109 DeviceState *pl061_dev;
1110 hwaddr base = vms->memmap[gpio].base;
1111 hwaddr size = vms->memmap[gpio].size;
1112 int irq = vms->irqmap[gpio];
1113 const char compat[] = "arm,pl061\0arm,primecell";
1114 SysBusDevice *s;
1115 MachineState *ms = MACHINE(vms);
1116
1117 pl061_dev = qdev_new("pl061");
1118 /* Pull lines down to 0 if not driven by the PL061 */
1119 qdev_prop_set_uint32(pl061_dev, "pullups", 0);
1120 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
1121 s = SYS_BUS_DEVICE(pl061_dev);
1122 sysbus_realize_and_unref(s, &error_fatal);
1123 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
1124 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
1125
1126 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
1127 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
1128 qemu_fdt_add_subnode(ms->fdt, nodename);
1129 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1130 2, base, 2, size);
1131 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
1132 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
1133 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
1134 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1135 GIC_FDT_IRQ_TYPE_SPI, irq,
1136 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
1137 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
1138 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1139 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
1140
1141 if (gpio != VIRT_GPIO) {
1142 /* Mark as not usable by the normal world */
1143 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1144 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1145 }
1146 g_free(nodename);
1147
1148 /* Child gpio devices */
1149 if (gpio == VIRT_GPIO) {
1150 create_gpio_keys(ms->fdt, pl061_dev, phandle);
1151 } else {
1152 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
1153 }
1154 }
1155
create_virtio_devices(const VirtMachineState * vms)1156 static void create_virtio_devices(const VirtMachineState *vms)
1157 {
1158 int i;
1159 hwaddr size = vms->memmap[VIRT_MMIO].size;
1160 MachineState *ms = MACHINE(vms);
1161
1162 /* We create the transports in forwards order. Since qbus_realize()
1163 * prepends (not appends) new child buses, the incrementing loop below will
1164 * create a list of virtio-mmio buses with decreasing base addresses.
1165 *
1166 * When a -device option is processed from the command line,
1167 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1168 * order. The upshot is that -device options in increasing command line
1169 * order are mapped to virtio-mmio buses with decreasing base addresses.
1170 *
1171 * When this code was originally written, that arrangement ensured that the
1172 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1173 * the first -device on the command line. (The end-to-end order is a
1174 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1175 * guest kernel's name-to-address assignment strategy.)
1176 *
1177 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1178 * the message, if not necessarily the code, of commit 70161ff336.
1179 * Therefore the loop now establishes the inverse of the original intent.
1180 *
1181 * Unfortunately, we can't counteract the kernel change by reversing the
1182 * loop; it would break existing command lines.
1183 *
1184 * In any case, the kernel makes no guarantee about the stability of
1185 * enumeration order of virtio devices (as demonstrated by it changing
1186 * between kernel versions). For reliable and stable identification
1187 * of disks users must use UUIDs or similar mechanisms.
1188 */
1189 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
1190 int irq = vms->irqmap[VIRT_MMIO] + i;
1191 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1192
1193 sysbus_create_simple("virtio-mmio", base,
1194 qdev_get_gpio_in(vms->gic, irq));
1195 }
1196
1197 /* We add dtb nodes in reverse order so that they appear in the finished
1198 * device tree lowest address first.
1199 *
1200 * Note that this mapping is independent of the loop above. The previous
1201 * loop influences virtio device to virtio transport assignment, whereas
1202 * this loop controls how virtio transports are laid out in the dtb.
1203 */
1204 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
1205 char *nodename;
1206 int irq = vms->irqmap[VIRT_MMIO] + i;
1207 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1208
1209 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
1210 qemu_fdt_add_subnode(ms->fdt, nodename);
1211 qemu_fdt_setprop_string(ms->fdt, nodename,
1212 "compatible", "virtio,mmio");
1213 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1214 2, base, 2, size);
1215 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1216 GIC_FDT_IRQ_TYPE_SPI, irq,
1217 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1218 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1219 g_free(nodename);
1220 }
1221 }
1222
1223 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1224
virt_flash_create1(VirtMachineState * vms,const char * name,const char * alias_prop_name)1225 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
1226 const char *name,
1227 const char *alias_prop_name)
1228 {
1229 /*
1230 * Create a single flash device. We use the same parameters as
1231 * the flash devices on the Versatile Express board.
1232 */
1233 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
1234
1235 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1236 qdev_prop_set_uint8(dev, "width", 4);
1237 qdev_prop_set_uint8(dev, "device-width", 2);
1238 qdev_prop_set_bit(dev, "big-endian", false);
1239 qdev_prop_set_uint16(dev, "id0", 0x89);
1240 qdev_prop_set_uint16(dev, "id1", 0x18);
1241 qdev_prop_set_uint16(dev, "id2", 0x00);
1242 qdev_prop_set_uint16(dev, "id3", 0x00);
1243 qdev_prop_set_string(dev, "name", name);
1244 object_property_add_child(OBJECT(vms), name, OBJECT(dev));
1245 object_property_add_alias(OBJECT(vms), alias_prop_name,
1246 OBJECT(dev), "drive");
1247 return PFLASH_CFI01(dev);
1248 }
1249
virt_flash_create(VirtMachineState * vms)1250 static void virt_flash_create(VirtMachineState *vms)
1251 {
1252 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1253 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1254 }
1255
virt_flash_map1(PFlashCFI01 * flash,hwaddr base,hwaddr size,MemoryRegion * sysmem)1256 static void virt_flash_map1(PFlashCFI01 *flash,
1257 hwaddr base, hwaddr size,
1258 MemoryRegion *sysmem)
1259 {
1260 DeviceState *dev = DEVICE(flash);
1261
1262 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
1263 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
1264 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1265 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1266
1267 memory_region_add_subregion(sysmem, base,
1268 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
1269 0));
1270 }
1271
virt_flash_map(VirtMachineState * vms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)1272 static void virt_flash_map(VirtMachineState *vms,
1273 MemoryRegion *sysmem,
1274 MemoryRegion *secure_sysmem)
1275 {
1276 /*
1277 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1278 * sysmem is the system memory space. secure_sysmem is the secure view
1279 * of the system, and the first flash device should be made visible only
1280 * there. The second flash device is visible to both secure and nonsecure.
1281 * If sysmem == secure_sysmem this means there is no separate Secure
1282 * address space and both flash devices are generally visible.
1283 */
1284 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1285 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1286
1287 virt_flash_map1(vms->flash[0], flashbase, flashsize,
1288 secure_sysmem);
1289 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1290 sysmem);
1291 }
1292
virt_flash_fdt(VirtMachineState * vms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)1293 static void virt_flash_fdt(VirtMachineState *vms,
1294 MemoryRegion *sysmem,
1295 MemoryRegion *secure_sysmem)
1296 {
1297 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1298 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1299 MachineState *ms = MACHINE(vms);
1300 char *nodename;
1301
1302 if (sysmem == secure_sysmem) {
1303 /* Report both flash devices as a single node in the DT */
1304 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1305 qemu_fdt_add_subnode(ms->fdt, nodename);
1306 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1307 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1308 2, flashbase, 2, flashsize,
1309 2, flashbase + flashsize, 2, flashsize);
1310 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1311 g_free(nodename);
1312 } else {
1313 /*
1314 * Report the devices as separate nodes so we can mark one as
1315 * only visible to the secure world.
1316 */
1317 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1318 qemu_fdt_add_subnode(ms->fdt, nodename);
1319 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1320 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1321 2, flashbase, 2, flashsize);
1322 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1323 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1324 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1325 g_free(nodename);
1326
1327 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize);
1328 qemu_fdt_add_subnode(ms->fdt, nodename);
1329 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1330 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1331 2, flashbase + flashsize, 2, flashsize);
1332 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1333 g_free(nodename);
1334 }
1335 }
1336
virt_firmware_init(VirtMachineState * vms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)1337 static bool virt_firmware_init(VirtMachineState *vms,
1338 MemoryRegion *sysmem,
1339 MemoryRegion *secure_sysmem)
1340 {
1341 int i;
1342 const char *bios_name;
1343 BlockBackend *pflash_blk0;
1344
1345 /* Map legacy -drive if=pflash to machine properties */
1346 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1347 pflash_cfi01_legacy_drive(vms->flash[i],
1348 drive_get(IF_PFLASH, 0, i));
1349 }
1350
1351 virt_flash_map(vms, sysmem, secure_sysmem);
1352
1353 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1354
1355 bios_name = MACHINE(vms)->firmware;
1356 if (bios_name) {
1357 char *fname;
1358 MemoryRegion *mr;
1359 int image_size;
1360
1361 if (pflash_blk0) {
1362 error_report("The contents of the first flash device may be "
1363 "specified with -bios or with -drive if=pflash... "
1364 "but you cannot use both options at once");
1365 exit(1);
1366 }
1367
1368 /* Fall back to -bios */
1369
1370 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1371 if (!fname) {
1372 error_report("Could not find ROM image '%s'", bios_name);
1373 exit(1);
1374 }
1375 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1376 image_size = load_image_mr(fname, mr);
1377 g_free(fname);
1378 if (image_size < 0) {
1379 error_report("Could not load ROM image '%s'", bios_name);
1380 exit(1);
1381 }
1382 }
1383
1384 return pflash_blk0 || bios_name;
1385 }
1386
create_fw_cfg(const VirtMachineState * vms,AddressSpace * as)1387 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1388 {
1389 MachineState *ms = MACHINE(vms);
1390 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1391 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1392 FWCfgState *fw_cfg;
1393 char *nodename;
1394
1395 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1396 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1397
1398 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1399 qemu_fdt_add_subnode(ms->fdt, nodename);
1400 qemu_fdt_setprop_string(ms->fdt, nodename,
1401 "compatible", "qemu,fw-cfg-mmio");
1402 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1403 2, base, 2, size);
1404 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1405 g_free(nodename);
1406 return fw_cfg;
1407 }
1408
create_pcie_irq_map(const MachineState * ms,uint32_t gic_phandle,int first_irq,const char * nodename)1409 static void create_pcie_irq_map(const MachineState *ms,
1410 uint32_t gic_phandle,
1411 int first_irq, const char *nodename)
1412 {
1413 int devfn, pin;
1414 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1415 uint32_t *irq_map = full_irq_map;
1416
1417 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1418 for (pin = 0; pin < 4; pin++) {
1419 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1420 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1421 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1422 int i;
1423
1424 uint32_t map[] = {
1425 devfn << 8, 0, 0, /* devfn */
1426 pin + 1, /* PCI pin */
1427 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1428
1429 /* Convert map to big endian */
1430 for (i = 0; i < 10; i++) {
1431 irq_map[i] = cpu_to_be32(map[i]);
1432 }
1433 irq_map += 10;
1434 }
1435 }
1436
1437 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1438 full_irq_map, sizeof(full_irq_map));
1439
1440 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1441 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1442 0, 0,
1443 0x7 /* PCI irq */);
1444 }
1445
create_smmu(const VirtMachineState * vms,PCIBus * bus)1446 static void create_smmu(const VirtMachineState *vms,
1447 PCIBus *bus)
1448 {
1449 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1450 char *node;
1451 const char compat[] = "arm,smmu-v3";
1452 int irq = vms->irqmap[VIRT_SMMU];
1453 int i;
1454 hwaddr base = vms->memmap[VIRT_SMMU].base;
1455 hwaddr size = vms->memmap[VIRT_SMMU].size;
1456 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1457 DeviceState *dev;
1458 MachineState *ms = MACHINE(vms);
1459
1460 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1461 return;
1462 }
1463
1464 dev = qdev_new(TYPE_ARM_SMMUV3);
1465
1466 if (!vmc->no_nested_smmu) {
1467 object_property_set_str(OBJECT(dev), "stage", "nested", &error_fatal);
1468 }
1469 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1470 &error_abort);
1471 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1472 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1473 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1474 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1475 qdev_get_gpio_in(vms->gic, irq + i));
1476 }
1477
1478 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1479 qemu_fdt_add_subnode(ms->fdt, node);
1480 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1481 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
1482
1483 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
1484 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1485 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1486 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1487 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1488
1489 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
1490 sizeof(irq_names));
1491
1492 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
1493
1494 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1495
1496 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1497 g_free(node);
1498 }
1499
create_virtio_iommu_dt_bindings(VirtMachineState * vms)1500 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
1501 {
1502 const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
1503 uint16_t bdf = vms->virtio_iommu_bdf;
1504 MachineState *ms = MACHINE(vms);
1505 char *node;
1506
1507 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1508
1509 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename,
1510 PCI_SLOT(bdf), PCI_FUNC(bdf));
1511 qemu_fdt_add_subnode(ms->fdt, node);
1512 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1513 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
1514 1, bdf << 8, 1, 0, 1, 0,
1515 1, 0, 1, 0);
1516
1517 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1518 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1519 g_free(node);
1520
1521 if (!vms->default_bus_bypass_iommu) {
1522 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
1523 0x0, vms->iommu_phandle, 0x0, bdf,
1524 bdf + 1, vms->iommu_phandle, bdf + 1,
1525 0xffff - bdf);
1526 }
1527 }
1528
create_pcie(VirtMachineState * vms)1529 static void create_pcie(VirtMachineState *vms)
1530 {
1531 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1532 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1533 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1534 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1535 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1536 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1537 hwaddr base_ecam, size_ecam;
1538 hwaddr base = base_mmio;
1539 int nr_pcie_buses;
1540 int irq = vms->irqmap[VIRT_PCIE];
1541 MemoryRegion *mmio_alias;
1542 MemoryRegion *mmio_reg;
1543 MemoryRegion *ecam_alias;
1544 MemoryRegion *ecam_reg;
1545 DeviceState *dev;
1546 char *nodename;
1547 int i, ecam_id;
1548 PCIHostState *pci;
1549 MachineState *ms = MACHINE(vms);
1550 MachineClass *mc = MACHINE_GET_CLASS(ms);
1551
1552 dev = qdev_new(TYPE_GPEX_HOST);
1553 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1554
1555 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1556 base_ecam = vms->memmap[ecam_id].base;
1557 size_ecam = vms->memmap[ecam_id].size;
1558 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1559 /* Map only the first size_ecam bytes of ECAM space */
1560 ecam_alias = g_new0(MemoryRegion, 1);
1561 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1562 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1563 ecam_reg, 0, size_ecam);
1564 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1565
1566 /* Map the MMIO window into system address space so as to expose
1567 * the section of PCI MMIO space which starts at the same base address
1568 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1569 * the window).
1570 */
1571 mmio_alias = g_new0(MemoryRegion, 1);
1572 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1573 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1574 mmio_reg, base_mmio, size_mmio);
1575 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1576
1577 if (vms->highmem_mmio) {
1578 /* Map high MMIO space */
1579 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1580
1581 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1582 mmio_reg, base_mmio_high, size_mmio_high);
1583 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1584 high_mmio_alias);
1585 }
1586
1587 /* Map IO port space */
1588 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1589
1590 for (i = 0; i < PCI_NUM_PINS; i++) {
1591 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1592 qdev_get_gpio_in(vms->gic, irq + i));
1593 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1594 }
1595
1596 pci = PCI_HOST_BRIDGE(dev);
1597 pci->bypass_iommu = vms->default_bus_bypass_iommu;
1598 vms->bus = pci->bus;
1599 if (vms->bus) {
1600 pci_init_nic_devices(pci->bus, mc->default_nic);
1601 }
1602
1603 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1604 qemu_fdt_add_subnode(ms->fdt, nodename);
1605 qemu_fdt_setprop_string(ms->fdt, nodename,
1606 "compatible", "pci-host-ecam-generic");
1607 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
1608 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
1609 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
1610 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
1611 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
1612 nr_pcie_buses - 1);
1613 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1614
1615 if (vms->msi_phandle) {
1616 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
1617 0, vms->msi_phandle, 0, 0x10000);
1618 }
1619
1620 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1621 2, base_ecam, 2, size_ecam);
1622
1623 if (vms->highmem_mmio) {
1624 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1625 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1626 2, base_pio, 2, size_pio,
1627 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1628 2, base_mmio, 2, size_mmio,
1629 1, FDT_PCI_RANGE_MMIO_64BIT,
1630 2, base_mmio_high,
1631 2, base_mmio_high, 2, size_mmio_high);
1632 } else {
1633 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1634 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1635 2, base_pio, 2, size_pio,
1636 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1637 2, base_mmio, 2, size_mmio);
1638 }
1639
1640 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
1641 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
1642
1643 if (vms->iommu) {
1644 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1645
1646 switch (vms->iommu) {
1647 case VIRT_IOMMU_SMMUV3:
1648 create_smmu(vms, vms->bus);
1649 if (!vms->default_bus_bypass_iommu) {
1650 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
1651 0x0, vms->iommu_phandle, 0x0, 0x10000);
1652 }
1653 break;
1654 default:
1655 g_assert_not_reached();
1656 }
1657 }
1658 }
1659
create_cxl_host_reg_region(VirtMachineState * vms)1660 static void create_cxl_host_reg_region(VirtMachineState *vms)
1661 {
1662 MemoryRegion *sysmem = get_system_memory();
1663 MemoryRegion *mr = &vms->cxl_devices_state.host_mr;
1664
1665 memory_region_init(mr, OBJECT(vms), "cxl_host_reg",
1666 vms->memmap[VIRT_CXL_HOST].size);
1667 memory_region_add_subregion(sysmem, vms->memmap[VIRT_CXL_HOST].base, mr);
1668 vms->highmem_cxl = true;
1669 }
1670
create_platform_bus(VirtMachineState * vms)1671 static void create_platform_bus(VirtMachineState *vms)
1672 {
1673 DeviceState *dev;
1674 SysBusDevice *s;
1675 int i;
1676 MemoryRegion *sysmem = get_system_memory();
1677
1678 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1679 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1680 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1681 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1682 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1683 vms->platform_bus_dev = dev;
1684
1685 s = SYS_BUS_DEVICE(dev);
1686 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1687 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1688 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1689 }
1690
1691 memory_region_add_subregion(sysmem,
1692 vms->memmap[VIRT_PLATFORM_BUS].base,
1693 sysbus_mmio_get_region(s, 0));
1694 }
1695
create_tag_ram(MemoryRegion * tag_sysmem,hwaddr base,hwaddr size,const char * name)1696 static void create_tag_ram(MemoryRegion *tag_sysmem,
1697 hwaddr base, hwaddr size,
1698 const char *name)
1699 {
1700 MemoryRegion *tagram = g_new(MemoryRegion, 1);
1701
1702 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
1703 memory_region_add_subregion(tag_sysmem, base / 32, tagram);
1704 }
1705
create_secure_ram(VirtMachineState * vms,MemoryRegion * secure_sysmem,MemoryRegion * secure_tag_sysmem)1706 static void create_secure_ram(VirtMachineState *vms,
1707 MemoryRegion *secure_sysmem,
1708 MemoryRegion *secure_tag_sysmem)
1709 {
1710 MemoryRegion *secram = g_new(MemoryRegion, 1);
1711 char *nodename;
1712 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1713 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1714 MachineState *ms = MACHINE(vms);
1715
1716 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1717 &error_fatal);
1718 memory_region_add_subregion(secure_sysmem, base, secram);
1719
1720 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1721 qemu_fdt_add_subnode(ms->fdt, nodename);
1722 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
1723 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
1724 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1725 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1726
1727 if (secure_tag_sysmem) {
1728 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1729 }
1730
1731 g_free(nodename);
1732 }
1733
machvirt_dtb(const struct arm_boot_info * binfo,int * fdt_size)1734 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1735 {
1736 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1737 bootinfo);
1738 MachineState *ms = MACHINE(board);
1739
1740
1741 *fdt_size = board->fdt_size;
1742 return ms->fdt;
1743 }
1744
virt_build_smbios(VirtMachineState * vms)1745 static void virt_build_smbios(VirtMachineState *vms)
1746 {
1747 MachineClass *mc = MACHINE_GET_CLASS(vms);
1748 MachineState *ms = MACHINE(vms);
1749 uint8_t *smbios_tables, *smbios_anchor;
1750 size_t smbios_tables_len, smbios_anchor_len;
1751 struct smbios_phys_mem_area mem_array;
1752 const char *product = "QEMU Virtual Machine";
1753
1754 if (kvm_enabled()) {
1755 product = "KVM Virtual Machine";
1756 }
1757
1758 smbios_set_defaults("QEMU", product, mc->name);
1759
1760 /* build the array of physical mem area from base_memmap */
1761 mem_array.address = vms->memmap[VIRT_MEM].base;
1762 mem_array.length = ms->ram_size;
1763
1764 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, &mem_array, 1,
1765 &smbios_tables, &smbios_tables_len,
1766 &smbios_anchor, &smbios_anchor_len,
1767 &error_fatal);
1768
1769 if (smbios_anchor) {
1770 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1771 smbios_tables, smbios_tables_len);
1772 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1773 smbios_anchor, smbios_anchor_len);
1774 }
1775 }
1776
1777 static
virt_machine_done(Notifier * notifier,void * data)1778 void virt_machine_done(Notifier *notifier, void *data)
1779 {
1780 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1781 machine_done);
1782 MachineState *ms = MACHINE(vms);
1783 ARMCPU *cpu = ARM_CPU(first_cpu);
1784 struct arm_boot_info *info = &vms->bootinfo;
1785 AddressSpace *as = arm_boot_address_space(cpu, info);
1786
1787 cxl_hook_up_pxb_registers(vms->bus, &vms->cxl_devices_state,
1788 &error_fatal);
1789
1790 if (vms->cxl_devices_state.is_enabled) {
1791 cxl_fmws_link_targets(&error_fatal);
1792 }
1793 /*
1794 * If the user provided a dtb, we assume the dynamic sysbus nodes
1795 * already are integrated there. This corresponds to a use case where
1796 * the dynamic sysbus nodes are complex and their generation is not yet
1797 * supported. In that case the user can take charge of the guest dt
1798 * while qemu takes charge of the qom stuff.
1799 */
1800 if (info->dtb_filename == NULL) {
1801 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
1802 vms->memmap[VIRT_PLATFORM_BUS].base,
1803 vms->memmap[VIRT_PLATFORM_BUS].size,
1804 vms->irqmap[VIRT_PLATFORM_BUS]);
1805 }
1806 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms, cpu) < 0) {
1807 exit(1);
1808 }
1809
1810 pci_bus_add_fw_cfg_extra_pci_roots(vms->fw_cfg, vms->bus,
1811 &error_abort);
1812
1813 virt_acpi_setup(vms);
1814 virt_build_smbios(vms);
1815 }
1816
virt_cpu_mp_affinity(VirtMachineState * vms,int idx)1817 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1818 {
1819 uint8_t clustersz;
1820
1821 /*
1822 * Adjust MPIDR to make TCG consistent (with 64-bit KVM hosts)
1823 * and to improve SGI efficiency.
1824 */
1825 if (vms->gic_version == VIRT_GIC_VERSION_2) {
1826 clustersz = GIC_TARGETLIST_BITS;
1827 } else {
1828 clustersz = GICV3_TARGETLIST_BITS;
1829 }
1830
1831 return arm_build_mp_affinity(idx, clustersz);
1832 }
1833
virt_get_high_memmap_enabled(VirtMachineState * vms,int index)1834 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,
1835 int index)
1836 {
1837 bool *enabled_array[] = {
1838 &vms->highmem_redists,
1839 &vms->highmem_cxl,
1840 &vms->highmem_ecam,
1841 &vms->highmem_mmio,
1842 };
1843
1844 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST ==
1845 ARRAY_SIZE(enabled_array));
1846 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));
1847
1848 return enabled_array[index - VIRT_LOWMEMMAP_LAST];
1849 }
1850
virt_set_high_memmap(VirtMachineState * vms,hwaddr base,int pa_bits)1851 static void virt_set_high_memmap(VirtMachineState *vms,
1852 hwaddr base, int pa_bits)
1853 {
1854 hwaddr region_base, region_size;
1855 bool *region_enabled, fits;
1856 int i;
1857
1858 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1859 region_enabled = virt_get_high_memmap_enabled(vms, i);
1860 region_base = ROUND_UP(base, extended_memmap[i].size);
1861 region_size = extended_memmap[i].size;
1862
1863 vms->memmap[i].base = region_base;
1864 vms->memmap[i].size = region_size;
1865
1866 /*
1867 * Check each device to see if it fits in the PA space,
1868 * moving highest_gpa as we go. For compatibility, move
1869 * highest_gpa for disabled fitting devices as well, if
1870 * the compact layout has been disabled.
1871 *
1872 * For each device that doesn't fit, disable it.
1873 */
1874 fits = (region_base + region_size) <= BIT_ULL(pa_bits);
1875 *region_enabled &= fits;
1876 if (vms->highmem_compact && !*region_enabled) {
1877 continue;
1878 }
1879
1880 base = region_base + region_size;
1881 if (fits) {
1882 vms->highest_gpa = base - 1;
1883 }
1884 }
1885 }
1886
virt_set_memmap(VirtMachineState * vms,int pa_bits)1887 static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
1888 {
1889 MachineState *ms = MACHINE(vms);
1890 hwaddr base, device_memory_base, device_memory_size, memtop;
1891 int i;
1892
1893 vms->memmap = extended_memmap;
1894
1895 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1896 vms->memmap[i] = base_memmap[i];
1897 }
1898
1899 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1900 error_report("unsupported number of memory slots: %"PRIu64,
1901 ms->ram_slots);
1902 exit(EXIT_FAILURE);
1903 }
1904
1905 /*
1906 * !highmem is exactly the same as limiting the PA space to 32bit,
1907 * irrespective of the underlying capabilities of the HW.
1908 */
1909 if (!vms->highmem) {
1910 pa_bits = 32;
1911 }
1912
1913 /*
1914 * We compute the base of the high IO region depending on the
1915 * amount of initial and device memory. The device memory start/size
1916 * is aligned on 1GiB. We never put the high IO region below 256GiB
1917 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1918 * The device region size assumes 1GiB page max alignment per slot.
1919 */
1920 device_memory_base =
1921 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1922 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1923
1924 /* Base address of the high IO region */
1925 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1926 if (memtop > BIT_ULL(pa_bits)) {
1927 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes",
1928 pa_bits, memtop - BIT_ULL(pa_bits));
1929 exit(EXIT_FAILURE);
1930 }
1931 if (base < device_memory_base) {
1932 error_report("maxmem/slots too huge");
1933 exit(EXIT_FAILURE);
1934 }
1935 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1936 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1937 }
1938
1939 /* We know for sure that at least the memory fits in the PA space */
1940 vms->highest_gpa = memtop - 1;
1941
1942 virt_set_high_memmap(vms, base, pa_bits);
1943
1944 if (device_memory_size > 0) {
1945 machine_memory_devices_init(ms, device_memory_base, device_memory_size);
1946 }
1947 vms->highest_gpa = cxl_fmws_set_memmap(ROUND_UP(vms->highest_gpa + 1,
1948 256 * MiB),
1949 BIT_ULL(pa_bits)) - 1;
1950 }
1951
finalize_gic_version_do(const char * accel_name,VirtGICType gic_version,int gics_supported,unsigned int max_cpus)1952 static VirtGICType finalize_gic_version_do(const char *accel_name,
1953 VirtGICType gic_version,
1954 int gics_supported,
1955 unsigned int max_cpus)
1956 {
1957 /* Convert host/max/nosel to GIC version number */
1958 switch (gic_version) {
1959 case VIRT_GIC_VERSION_HOST:
1960 if (!kvm_enabled()) {
1961 error_report("gic-version=host requires KVM");
1962 exit(1);
1963 }
1964
1965 /* For KVM, gic-version=host means gic-version=max */
1966 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX,
1967 gics_supported, max_cpus);
1968 case VIRT_GIC_VERSION_MAX:
1969 if (gics_supported & VIRT_GIC_VERSION_4_MASK) {
1970 gic_version = VIRT_GIC_VERSION_4;
1971 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
1972 gic_version = VIRT_GIC_VERSION_3;
1973 } else {
1974 gic_version = VIRT_GIC_VERSION_2;
1975 }
1976 break;
1977 case VIRT_GIC_VERSION_NOSEL:
1978 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) &&
1979 max_cpus <= GIC_NCPU) {
1980 gic_version = VIRT_GIC_VERSION_2;
1981 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
1982 /*
1983 * in case the host does not support v2 emulation or
1984 * the end-user requested more than 8 VCPUs we now default
1985 * to v3. In any case defaulting to v2 would be broken.
1986 */
1987 gic_version = VIRT_GIC_VERSION_3;
1988 } else if (max_cpus > GIC_NCPU) {
1989 error_report("%s only supports GICv2 emulation but more than 8 "
1990 "vcpus are requested", accel_name);
1991 exit(1);
1992 }
1993 break;
1994 case VIRT_GIC_VERSION_2:
1995 case VIRT_GIC_VERSION_3:
1996 case VIRT_GIC_VERSION_4:
1997 break;
1998 }
1999
2000 /* Check chosen version is effectively supported */
2001 switch (gic_version) {
2002 case VIRT_GIC_VERSION_2:
2003 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) {
2004 error_report("%s does not support GICv2 emulation", accel_name);
2005 exit(1);
2006 }
2007 break;
2008 case VIRT_GIC_VERSION_3:
2009 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) {
2010 error_report("%s does not support GICv3 emulation", accel_name);
2011 exit(1);
2012 }
2013 break;
2014 case VIRT_GIC_VERSION_4:
2015 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) {
2016 error_report("%s does not support GICv4 emulation, is virtualization=on?",
2017 accel_name);
2018 exit(1);
2019 }
2020 break;
2021 default:
2022 error_report("logic error in finalize_gic_version");
2023 exit(1);
2024 break;
2025 }
2026
2027 return gic_version;
2028 }
2029
2030 /*
2031 * finalize_gic_version - Determines the final gic_version
2032 * according to the gic-version property
2033 *
2034 * Default GIC type is v2
2035 */
finalize_gic_version(VirtMachineState * vms)2036 static void finalize_gic_version(VirtMachineState *vms)
2037 {
2038 const char *accel_name = current_accel_name();
2039 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
2040 int gics_supported = 0;
2041
2042 /* Determine which GIC versions the current environment supports */
2043 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
2044 int probe_bitmap = kvm_arm_vgic_probe();
2045
2046 if (!probe_bitmap) {
2047 error_report("Unable to determine GIC version supported by host");
2048 exit(1);
2049 }
2050
2051 if (probe_bitmap & KVM_ARM_VGIC_V2) {
2052 gics_supported |= VIRT_GIC_VERSION_2_MASK;
2053 }
2054 if (probe_bitmap & KVM_ARM_VGIC_V3) {
2055 gics_supported |= VIRT_GIC_VERSION_3_MASK;
2056 }
2057 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
2058 /* KVM w/o kernel irqchip can only deal with GICv2 */
2059 gics_supported |= VIRT_GIC_VERSION_2_MASK;
2060 accel_name = "KVM with kernel-irqchip=off";
2061 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
2062 gics_supported |= VIRT_GIC_VERSION_2_MASK;
2063 if (module_object_class_by_name("arm-gicv3")) {
2064 gics_supported |= VIRT_GIC_VERSION_3_MASK;
2065 if (vms->virt) {
2066 /* GICv4 only makes sense if CPU has EL2 */
2067 gics_supported |= VIRT_GIC_VERSION_4_MASK;
2068 }
2069 }
2070 } else {
2071 error_report("Unsupported accelerator, can not determine GIC support");
2072 exit(1);
2073 }
2074
2075 /*
2076 * Then convert helpers like host/max to concrete GIC versions and ensure
2077 * the desired version is supported
2078 */
2079 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
2080 gics_supported, max_cpus);
2081 }
2082
2083 /*
2084 * virt_post_cpus_gic_realized() must be called after the CPUs and
2085 * the GIC have both been realized.
2086 */
virt_post_cpus_gic_realized(VirtMachineState * vms,MemoryRegion * sysmem)2087 static void virt_post_cpus_gic_realized(VirtMachineState *vms,
2088 MemoryRegion *sysmem)
2089 {
2090 int max_cpus = MACHINE(vms)->smp.max_cpus;
2091 bool aarch64, pmu, steal_time;
2092 CPUState *cpu;
2093
2094 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
2095 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
2096 steal_time = object_property_get_bool(OBJECT(first_cpu),
2097 "kvm-steal-time", NULL);
2098
2099 if (kvm_enabled()) {
2100 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
2101 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
2102
2103 if (steal_time) {
2104 MemoryRegion *pvtime = g_new(MemoryRegion, 1);
2105 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
2106
2107 /* The memory region size must be a multiple of host page size. */
2108 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
2109
2110 if (pvtime_size > pvtime_reg_size) {
2111 error_report("pvtime requires a %" HWADDR_PRId
2112 " byte memory region for %d CPUs,"
2113 " but only %" HWADDR_PRId " has been reserved",
2114 pvtime_size, max_cpus, pvtime_reg_size);
2115 exit(1);
2116 }
2117
2118 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
2119 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
2120 }
2121 if (!aarch64 && vms->virt) {
2122 error_report("KVM does not support EL2 on an AArch32 vCPU");
2123 exit(1);
2124 }
2125
2126 CPU_FOREACH(cpu) {
2127 if (pmu) {
2128 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
2129 if (kvm_irqchip_in_kernel()) {
2130 kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ);
2131 }
2132 kvm_arm_pmu_init(ARM_CPU(cpu));
2133 }
2134 if (steal_time) {
2135 kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base
2136 + cpu->cpu_index
2137 * PVTIME_SIZE_PER_CPU);
2138 }
2139 }
2140 } else {
2141 if (aarch64 && vms->highmem) {
2142 int requested_pa_size = 64 - clz64(vms->highest_gpa);
2143 int pamax = arm_pamax(ARM_CPU(first_cpu));
2144
2145 if (pamax < requested_pa_size) {
2146 error_report("VCPU supports less PA bits (%d) than "
2147 "requested by the memory map (%d)",
2148 pamax, requested_pa_size);
2149 exit(1);
2150 }
2151 }
2152 }
2153 }
2154
machvirt_init(MachineState * machine)2155 static void machvirt_init(MachineState *machine)
2156 {
2157 VirtMachineState *vms = VIRT_MACHINE(machine);
2158 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
2159 MachineClass *mc = MACHINE_GET_CLASS(machine);
2160 const CPUArchIdList *possible_cpus;
2161 MemoryRegion *sysmem = get_system_memory();
2162 MemoryRegion *secure_sysmem = NULL;
2163 MemoryRegion *tag_sysmem = NULL;
2164 MemoryRegion *secure_tag_sysmem = NULL;
2165 int n, virt_max_cpus;
2166 bool firmware_loaded;
2167 bool aarch64 = true;
2168 bool has_ged = !vmc->no_ged;
2169 unsigned int smp_cpus = machine->smp.cpus;
2170 unsigned int max_cpus = machine->smp.max_cpus;
2171
2172 possible_cpus = mc->possible_cpu_arch_ids(machine);
2173
2174 /*
2175 * In accelerated mode, the memory map is computed earlier in kvm_type()
2176 * for Linux, or hvf_get_physical_address_range() for macOS to create a
2177 * VM with the right number of IPA bits.
2178 */
2179 if (!vms->memmap) {
2180 Object *cpuobj;
2181 ARMCPU *armcpu;
2182 int pa_bits;
2183
2184 /*
2185 * Instantiate a temporary CPU object to find out about what
2186 * we are about to deal with. Once this is done, get rid of
2187 * the object.
2188 */
2189 cpuobj = object_new(possible_cpus->cpus[0].type);
2190 armcpu = ARM_CPU(cpuobj);
2191
2192 pa_bits = arm_pamax(armcpu);
2193
2194 object_unref(cpuobj);
2195
2196 virt_set_memmap(vms, pa_bits);
2197 }
2198
2199 /* We can probe only here because during property set
2200 * KVM is not available yet
2201 */
2202 finalize_gic_version(vms);
2203
2204 if (vms->secure) {
2205 /*
2206 * The Secure view of the world is the same as the NonSecure,
2207 * but with a few extra devices. Create it as a container region
2208 * containing the system memory at low priority; any secure-only
2209 * devices go in at higher priority and take precedence.
2210 */
2211 secure_sysmem = g_new(MemoryRegion, 1);
2212 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
2213 UINT64_MAX);
2214 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
2215 }
2216
2217 firmware_loaded = virt_firmware_init(vms, sysmem,
2218 secure_sysmem ?: sysmem);
2219
2220 /* If we have an EL3 boot ROM then the assumption is that it will
2221 * implement PSCI itself, so disable QEMU's internal implementation
2222 * so it doesn't get in the way. Instead of starting secondary
2223 * CPUs in PSCI powerdown state we will start them all running and
2224 * let the boot ROM sort them out.
2225 * The usual case is that we do use QEMU's PSCI implementation;
2226 * if the guest has EL2 then we will use SMC as the conduit,
2227 * and otherwise we will use HVC (for backwards compatibility and
2228 * because if we're using KVM then we must use HVC).
2229 */
2230 if (vms->secure && firmware_loaded) {
2231 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
2232 } else if (vms->virt) {
2233 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
2234 } else {
2235 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
2236 }
2237
2238 /*
2239 * The maximum number of CPUs depends on the GIC version, or on how
2240 * many redistributors we can fit into the memory map (which in turn
2241 * depends on whether this is a GICv3 or v4).
2242 */
2243 if (vms->gic_version == VIRT_GIC_VERSION_2) {
2244 virt_max_cpus = GIC_NCPU;
2245 } else {
2246 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST);
2247 if (vms->highmem_redists) {
2248 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
2249 }
2250 }
2251
2252 if (max_cpus > virt_max_cpus) {
2253 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2254 "supported by machine 'mach-virt' (%d)",
2255 max_cpus, virt_max_cpus);
2256 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) {
2257 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2258 }
2259
2260 exit(1);
2261 }
2262
2263 if (vms->secure && !tcg_enabled() && !qtest_enabled()) {
2264 error_report("mach-virt: %s does not support providing "
2265 "Security extensions (TrustZone) to the guest CPU",
2266 current_accel_name());
2267 exit(1);
2268 }
2269
2270 if (vms->virt && kvm_enabled() && !kvm_arm_el2_supported()) {
2271 error_report("mach-virt: host kernel KVM does not support providing "
2272 "Virtualization extensions to the guest CPU");
2273 exit(1);
2274 }
2275
2276 if (vms->virt && !kvm_enabled() && !tcg_enabled() && !qtest_enabled()) {
2277 error_report("mach-virt: %s does not support providing "
2278 "Virtualization extensions to the guest CPU",
2279 current_accel_name());
2280 exit(1);
2281 }
2282
2283 if (vms->mte && hvf_enabled()) {
2284 error_report("mach-virt: %s does not support providing "
2285 "MTE to the guest CPU",
2286 current_accel_name());
2287 exit(1);
2288 }
2289
2290 create_fdt(vms);
2291
2292 assert(possible_cpus->len == max_cpus);
2293 for (n = 0; n < possible_cpus->len; n++) {
2294 Object *cpuobj;
2295 CPUState *cs;
2296
2297 if (n >= smp_cpus) {
2298 break;
2299 }
2300
2301 cpuobj = object_new(possible_cpus->cpus[n].type);
2302 object_property_set_int(cpuobj, "mp-affinity",
2303 possible_cpus->cpus[n].arch_id, NULL);
2304
2305 cs = CPU(cpuobj);
2306 cs->cpu_index = n;
2307
2308 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
2309 &error_fatal);
2310
2311 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
2312
2313 if (!vms->secure) {
2314 object_property_set_bool(cpuobj, "has_el3", false, NULL);
2315 }
2316
2317 if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
2318 object_property_set_bool(cpuobj, "has_el2", false, NULL);
2319 }
2320
2321 if (vmc->kvm_no_adjvtime &&
2322 object_property_find(cpuobj, "kvm-no-adjvtime")) {
2323 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
2324 }
2325
2326 if (vmc->no_kvm_steal_time &&
2327 object_property_find(cpuobj, "kvm-steal-time")) {
2328 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
2329 }
2330
2331 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) {
2332 object_property_set_bool(cpuobj, "lpa2", false, NULL);
2333 }
2334
2335 if (object_property_find(cpuobj, "reset-cbar")) {
2336 object_property_set_int(cpuobj, "reset-cbar",
2337 vms->memmap[VIRT_CPUPERIPHS].base,
2338 &error_abort);
2339 }
2340
2341 object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
2342 &error_abort);
2343 if (vms->secure) {
2344 object_property_set_link(cpuobj, "secure-memory",
2345 OBJECT(secure_sysmem), &error_abort);
2346 }
2347
2348 if (vms->mte) {
2349 if (tcg_enabled()) {
2350 /* Create the memory region only once, but link to all cpus. */
2351 if (!tag_sysmem) {
2352 /*
2353 * The property exists only if MemTag is supported.
2354 * If it is, we must allocate the ram to back that up.
2355 */
2356 if (!object_property_find(cpuobj, "tag-memory")) {
2357 error_report("MTE requested, but not supported "
2358 "by the guest CPU");
2359 exit(1);
2360 }
2361
2362 tag_sysmem = g_new(MemoryRegion, 1);
2363 memory_region_init(tag_sysmem, OBJECT(machine),
2364 "tag-memory", UINT64_MAX / 32);
2365
2366 if (vms->secure) {
2367 secure_tag_sysmem = g_new(MemoryRegion, 1);
2368 memory_region_init(secure_tag_sysmem, OBJECT(machine),
2369 "secure-tag-memory",
2370 UINT64_MAX / 32);
2371
2372 /* As with ram, secure-tag takes precedence over tag. */
2373 memory_region_add_subregion_overlap(secure_tag_sysmem,
2374 0, tag_sysmem, -1);
2375 }
2376 }
2377
2378 object_property_set_link(cpuobj, "tag-memory",
2379 OBJECT(tag_sysmem), &error_abort);
2380 if (vms->secure) {
2381 object_property_set_link(cpuobj, "secure-tag-memory",
2382 OBJECT(secure_tag_sysmem),
2383 &error_abort);
2384 }
2385 } else if (kvm_enabled()) {
2386 if (!kvm_arm_mte_supported()) {
2387 error_report("MTE requested, but not supported by KVM");
2388 exit(1);
2389 }
2390 kvm_arm_enable_mte(cpuobj, &error_abort);
2391 } else {
2392 error_report("MTE requested, but not supported ");
2393 exit(1);
2394 }
2395 }
2396
2397 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
2398 object_unref(cpuobj);
2399 }
2400
2401 /* Now we've created the CPUs we can see if they have the hypvirt timer */
2402 vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
2403 !vmc->no_ns_el2_virt_timer_irq;
2404
2405 fdt_add_timer_nodes(vms);
2406 fdt_add_cpu_nodes(vms);
2407
2408 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
2409 machine->ram);
2410
2411 cxl_fmws_update_mmio();
2412
2413 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
2414
2415 create_gic(vms, sysmem);
2416
2417 virt_post_cpus_gic_realized(vms, sysmem);
2418
2419 fdt_add_pmu_nodes(vms);
2420
2421 /*
2422 * The first UART always exists. If the security extensions are
2423 * enabled, the second UART also always exists. Otherwise, it only exists
2424 * if a backend is configured explicitly via '-serial <backend>'.
2425 * This avoids potentially breaking existing user setups that expect
2426 * only one NonSecure UART to be present (for instance, older EDK2
2427 * binaries).
2428 *
2429 * The nodes end up in the DTB in reverse order of creation, so we must
2430 * create UART0 last to ensure it appears as the first node in the DTB,
2431 * for compatibility with guest software that just iterates through the
2432 * DTB to find the first UART, as older versions of EDK2 do.
2433 * DTB readers that follow the spec, as Linux does, should honour the
2434 * aliases node information and /chosen/stdout-path regardless of
2435 * the order that nodes appear in the DTB.
2436 *
2437 * For similar back-compatibility reasons, if UART1 is the secure UART
2438 * we create it second (and so it appears first in the DTB), because
2439 * that's what QEMU has always done.
2440 */
2441 if (!vms->secure) {
2442 Chardev *serial1 = serial_hd(1);
2443
2444 if (serial1) {
2445 vms->second_ns_uart_present = true;
2446 create_uart(vms, VIRT_UART1, sysmem, serial1, false);
2447 }
2448 }
2449 create_uart(vms, VIRT_UART0, sysmem, serial_hd(0), false);
2450 if (vms->secure) {
2451 create_uart(vms, VIRT_UART1, secure_sysmem, serial_hd(1), true);
2452 }
2453
2454 if (vms->secure) {
2455 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
2456 }
2457
2458 if (tag_sysmem) {
2459 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
2460 machine->ram_size, "mach-virt.tag");
2461 }
2462
2463 vms->highmem_ecam &= (!firmware_loaded || aarch64);
2464
2465 create_rtc(vms);
2466
2467 create_pcie(vms);
2468 create_cxl_host_reg_region(vms);
2469
2470 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
2471 vms->acpi_dev = create_acpi_ged(vms);
2472 } else {
2473 create_gpio_devices(vms, VIRT_GPIO, sysmem);
2474 }
2475
2476 if (vms->secure && !vmc->no_secure_gpio) {
2477 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
2478 }
2479
2480 /* connect powerdown request */
2481 vms->powerdown_notifier.notify = virt_powerdown_req;
2482 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
2483
2484 /* Create mmio transports, so the user can create virtio backends
2485 * (which will be automatically plugged in to the transports). If
2486 * no backend is created the transport will just sit harmlessly idle.
2487 */
2488 create_virtio_devices(vms);
2489
2490 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2491 rom_set_fw(vms->fw_cfg);
2492
2493 create_platform_bus(vms);
2494
2495 if (machine->nvdimms_state->is_enabled) {
2496 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
2497 .space_id = AML_AS_SYSTEM_MEMORY,
2498 .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2499 .bit_width = NVDIMM_ACPI_IO_LEN << 3
2500 };
2501
2502 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2503 arm_virt_nvdimm_acpi_dsmio,
2504 vms->fw_cfg, OBJECT(vms));
2505 }
2506
2507 vms->bootinfo.ram_size = machine->ram_size;
2508 vms->bootinfo.board_id = -1;
2509 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2510 vms->bootinfo.get_dtb = machvirt_dtb;
2511 vms->bootinfo.skip_dtb_autoload = true;
2512 vms->bootinfo.firmware_loaded = firmware_loaded;
2513 vms->bootinfo.psci_conduit = vms->psci_conduit;
2514 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
2515
2516 vms->machine_done.notify = virt_machine_done;
2517 qemu_add_machine_init_done_notifier(&vms->machine_done);
2518 }
2519
virt_get_secure(Object * obj,Error ** errp)2520 static bool virt_get_secure(Object *obj, Error **errp)
2521 {
2522 VirtMachineState *vms = VIRT_MACHINE(obj);
2523
2524 return vms->secure;
2525 }
2526
virt_set_secure(Object * obj,bool value,Error ** errp)2527 static void virt_set_secure(Object *obj, bool value, Error **errp)
2528 {
2529 VirtMachineState *vms = VIRT_MACHINE(obj);
2530
2531 vms->secure = value;
2532 }
2533
virt_get_virt(Object * obj,Error ** errp)2534 static bool virt_get_virt(Object *obj, Error **errp)
2535 {
2536 VirtMachineState *vms = VIRT_MACHINE(obj);
2537
2538 return vms->virt;
2539 }
2540
virt_set_virt(Object * obj,bool value,Error ** errp)2541 static void virt_set_virt(Object *obj, bool value, Error **errp)
2542 {
2543 VirtMachineState *vms = VIRT_MACHINE(obj);
2544
2545 vms->virt = value;
2546 }
2547
virt_get_highmem(Object * obj,Error ** errp)2548 static bool virt_get_highmem(Object *obj, Error **errp)
2549 {
2550 VirtMachineState *vms = VIRT_MACHINE(obj);
2551
2552 return vms->highmem;
2553 }
2554
virt_set_highmem(Object * obj,bool value,Error ** errp)2555 static void virt_set_highmem(Object *obj, bool value, Error **errp)
2556 {
2557 VirtMachineState *vms = VIRT_MACHINE(obj);
2558
2559 vms->highmem = value;
2560 }
2561
virt_get_compact_highmem(Object * obj,Error ** errp)2562 static bool virt_get_compact_highmem(Object *obj, Error **errp)
2563 {
2564 VirtMachineState *vms = VIRT_MACHINE(obj);
2565
2566 return vms->highmem_compact;
2567 }
2568
virt_set_compact_highmem(Object * obj,bool value,Error ** errp)2569 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
2570 {
2571 VirtMachineState *vms = VIRT_MACHINE(obj);
2572
2573 vms->highmem_compact = value;
2574 }
2575
virt_get_highmem_redists(Object * obj,Error ** errp)2576 static bool virt_get_highmem_redists(Object *obj, Error **errp)
2577 {
2578 VirtMachineState *vms = VIRT_MACHINE(obj);
2579
2580 return vms->highmem_redists;
2581 }
2582
virt_set_highmem_redists(Object * obj,bool value,Error ** errp)2583 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp)
2584 {
2585 VirtMachineState *vms = VIRT_MACHINE(obj);
2586
2587 vms->highmem_redists = value;
2588 }
2589
virt_get_highmem_ecam(Object * obj,Error ** errp)2590 static bool virt_get_highmem_ecam(Object *obj, Error **errp)
2591 {
2592 VirtMachineState *vms = VIRT_MACHINE(obj);
2593
2594 return vms->highmem_ecam;
2595 }
2596
virt_set_highmem_ecam(Object * obj,bool value,Error ** errp)2597 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp)
2598 {
2599 VirtMachineState *vms = VIRT_MACHINE(obj);
2600
2601 vms->highmem_ecam = value;
2602 }
2603
virt_get_highmem_mmio(Object * obj,Error ** errp)2604 static bool virt_get_highmem_mmio(Object *obj, Error **errp)
2605 {
2606 VirtMachineState *vms = VIRT_MACHINE(obj);
2607
2608 return vms->highmem_mmio;
2609 }
2610
virt_set_highmem_mmio(Object * obj,bool value,Error ** errp)2611 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp)
2612 {
2613 VirtMachineState *vms = VIRT_MACHINE(obj);
2614
2615 vms->highmem_mmio = value;
2616 }
2617
virt_get_highmem_mmio_size(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)2618 static void virt_get_highmem_mmio_size(Object *obj, Visitor *v,
2619 const char *name, void *opaque,
2620 Error **errp)
2621 {
2622 uint64_t size = extended_memmap[VIRT_HIGH_PCIE_MMIO].size;
2623
2624 visit_type_size(v, name, &size, errp);
2625 }
2626
virt_set_highmem_mmio_size(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)2627 static void virt_set_highmem_mmio_size(Object *obj, Visitor *v,
2628 const char *name, void *opaque,
2629 Error **errp)
2630 {
2631 uint64_t size;
2632
2633 if (!visit_type_size(v, name, &size, errp)) {
2634 return;
2635 }
2636
2637 if (!is_power_of_2(size)) {
2638 error_setg(errp, "highmem-mmio-size is not a power of 2");
2639 return;
2640 }
2641
2642 if (size < DEFAULT_HIGH_PCIE_MMIO_SIZE) {
2643 char *sz = size_to_str(DEFAULT_HIGH_PCIE_MMIO_SIZE);
2644 error_setg(errp, "highmem-mmio-size cannot be set to a lower value "
2645 "than the default (%s)", sz);
2646 g_free(sz);
2647 return;
2648 }
2649
2650 extended_memmap[VIRT_HIGH_PCIE_MMIO].size = size;
2651 }
2652
virt_get_its(Object * obj,Error ** errp)2653 static bool virt_get_its(Object *obj, Error **errp)
2654 {
2655 VirtMachineState *vms = VIRT_MACHINE(obj);
2656
2657 return vms->its;
2658 }
2659
virt_set_its(Object * obj,bool value,Error ** errp)2660 static void virt_set_its(Object *obj, bool value, Error **errp)
2661 {
2662 VirtMachineState *vms = VIRT_MACHINE(obj);
2663
2664 vms->its = value;
2665 }
2666
virt_get_dtb_randomness(Object * obj,Error ** errp)2667 static bool virt_get_dtb_randomness(Object *obj, Error **errp)
2668 {
2669 VirtMachineState *vms = VIRT_MACHINE(obj);
2670
2671 return vms->dtb_randomness;
2672 }
2673
virt_set_dtb_randomness(Object * obj,bool value,Error ** errp)2674 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp)
2675 {
2676 VirtMachineState *vms = VIRT_MACHINE(obj);
2677
2678 vms->dtb_randomness = value;
2679 }
2680
virt_get_oem_id(Object * obj,Error ** errp)2681 static char *virt_get_oem_id(Object *obj, Error **errp)
2682 {
2683 VirtMachineState *vms = VIRT_MACHINE(obj);
2684
2685 return g_strdup(vms->oem_id);
2686 }
2687
virt_set_oem_id(Object * obj,const char * value,Error ** errp)2688 static void virt_set_oem_id(Object *obj, const char *value, Error **errp)
2689 {
2690 VirtMachineState *vms = VIRT_MACHINE(obj);
2691 size_t len = strlen(value);
2692
2693 if (len > 6) {
2694 error_setg(errp,
2695 "User specified oem-id value is bigger than 6 bytes in size");
2696 return;
2697 }
2698
2699 strncpy(vms->oem_id, value, 6);
2700 }
2701
virt_get_oem_table_id(Object * obj,Error ** errp)2702 static char *virt_get_oem_table_id(Object *obj, Error **errp)
2703 {
2704 VirtMachineState *vms = VIRT_MACHINE(obj);
2705
2706 return g_strdup(vms->oem_table_id);
2707 }
2708
virt_set_oem_table_id(Object * obj,const char * value,Error ** errp)2709 static void virt_set_oem_table_id(Object *obj, const char *value,
2710 Error **errp)
2711 {
2712 VirtMachineState *vms = VIRT_MACHINE(obj);
2713 size_t len = strlen(value);
2714
2715 if (len > 8) {
2716 error_setg(errp,
2717 "User specified oem-table-id value is bigger than 8 bytes in size");
2718 return;
2719 }
2720 strncpy(vms->oem_table_id, value, 8);
2721 }
2722
2723
virt_is_acpi_enabled(VirtMachineState * vms)2724 bool virt_is_acpi_enabled(VirtMachineState *vms)
2725 {
2726 if (vms->acpi == ON_OFF_AUTO_OFF) {
2727 return false;
2728 }
2729 return true;
2730 }
2731
virt_get_acpi(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)2732 static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
2733 void *opaque, Error **errp)
2734 {
2735 VirtMachineState *vms = VIRT_MACHINE(obj);
2736 OnOffAuto acpi = vms->acpi;
2737
2738 visit_type_OnOffAuto(v, name, &acpi, errp);
2739 }
2740
virt_set_acpi(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)2741 static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
2742 void *opaque, Error **errp)
2743 {
2744 VirtMachineState *vms = VIRT_MACHINE(obj);
2745
2746 visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2747 }
2748
virt_get_ras(Object * obj,Error ** errp)2749 static bool virt_get_ras(Object *obj, Error **errp)
2750 {
2751 VirtMachineState *vms = VIRT_MACHINE(obj);
2752
2753 return vms->ras;
2754 }
2755
virt_set_ras(Object * obj,bool value,Error ** errp)2756 static void virt_set_ras(Object *obj, bool value, Error **errp)
2757 {
2758 VirtMachineState *vms = VIRT_MACHINE(obj);
2759
2760 vms->ras = value;
2761 }
2762
virt_get_mte(Object * obj,Error ** errp)2763 static bool virt_get_mte(Object *obj, Error **errp)
2764 {
2765 VirtMachineState *vms = VIRT_MACHINE(obj);
2766
2767 return vms->mte;
2768 }
2769
virt_set_mte(Object * obj,bool value,Error ** errp)2770 static void virt_set_mte(Object *obj, bool value, Error **errp)
2771 {
2772 VirtMachineState *vms = VIRT_MACHINE(obj);
2773
2774 vms->mte = value;
2775 }
2776
virt_get_gic_version(Object * obj,Error ** errp)2777 static char *virt_get_gic_version(Object *obj, Error **errp)
2778 {
2779 VirtMachineState *vms = VIRT_MACHINE(obj);
2780 const char *val;
2781
2782 switch (vms->gic_version) {
2783 case VIRT_GIC_VERSION_4:
2784 val = "4";
2785 break;
2786 case VIRT_GIC_VERSION_3:
2787 val = "3";
2788 break;
2789 default:
2790 val = "2";
2791 break;
2792 }
2793 return g_strdup(val);
2794 }
2795
virt_set_gic_version(Object * obj,const char * value,Error ** errp)2796 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
2797 {
2798 VirtMachineState *vms = VIRT_MACHINE(obj);
2799
2800 if (!strcmp(value, "4")) {
2801 vms->gic_version = VIRT_GIC_VERSION_4;
2802 } else if (!strcmp(value, "3")) {
2803 vms->gic_version = VIRT_GIC_VERSION_3;
2804 } else if (!strcmp(value, "2")) {
2805 vms->gic_version = VIRT_GIC_VERSION_2;
2806 } else if (!strcmp(value, "host")) {
2807 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
2808 } else if (!strcmp(value, "max")) {
2809 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
2810 } else {
2811 error_setg(errp, "Invalid gic-version value");
2812 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
2813 }
2814 }
2815
virt_get_iommu(Object * obj,Error ** errp)2816 static char *virt_get_iommu(Object *obj, Error **errp)
2817 {
2818 VirtMachineState *vms = VIRT_MACHINE(obj);
2819
2820 switch (vms->iommu) {
2821 case VIRT_IOMMU_NONE:
2822 return g_strdup("none");
2823 case VIRT_IOMMU_SMMUV3:
2824 return g_strdup("smmuv3");
2825 default:
2826 g_assert_not_reached();
2827 }
2828 }
2829
virt_set_iommu(Object * obj,const char * value,Error ** errp)2830 static void virt_set_iommu(Object *obj, const char *value, Error **errp)
2831 {
2832 VirtMachineState *vms = VIRT_MACHINE(obj);
2833
2834 if (!strcmp(value, "smmuv3")) {
2835 vms->iommu = VIRT_IOMMU_SMMUV3;
2836 } else if (!strcmp(value, "none")) {
2837 vms->iommu = VIRT_IOMMU_NONE;
2838 } else {
2839 error_setg(errp, "Invalid iommu value");
2840 error_append_hint(errp, "Valid values are none, smmuv3.\n");
2841 }
2842 }
2843
virt_get_default_bus_bypass_iommu(Object * obj,Error ** errp)2844 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp)
2845 {
2846 VirtMachineState *vms = VIRT_MACHINE(obj);
2847
2848 return vms->default_bus_bypass_iommu;
2849 }
2850
virt_set_default_bus_bypass_iommu(Object * obj,bool value,Error ** errp)2851 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value,
2852 Error **errp)
2853 {
2854 VirtMachineState *vms = VIRT_MACHINE(obj);
2855
2856 vms->default_bus_bypass_iommu = value;
2857 }
2858
2859 static CpuInstanceProperties
virt_cpu_index_to_props(MachineState * ms,unsigned cpu_index)2860 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2861 {
2862 MachineClass *mc = MACHINE_GET_CLASS(ms);
2863 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2864
2865 assert(cpu_index < possible_cpus->len);
2866 return possible_cpus->cpus[cpu_index].props;
2867 }
2868
virt_get_default_cpu_node_id(const MachineState * ms,int idx)2869 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
2870 {
2871 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
2872
2873 return socket_id % ms->numa_state->num_nodes;
2874 }
2875
virt_possible_cpu_arch_ids(MachineState * ms)2876 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
2877 {
2878 int n;
2879 unsigned int max_cpus = ms->smp.max_cpus;
2880 VirtMachineState *vms = VIRT_MACHINE(ms);
2881 MachineClass *mc = MACHINE_GET_CLASS(vms);
2882
2883 if (ms->possible_cpus) {
2884 assert(ms->possible_cpus->len == max_cpus);
2885 return ms->possible_cpus;
2886 }
2887
2888 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2889 sizeof(CPUArchId) * max_cpus);
2890 ms->possible_cpus->len = max_cpus;
2891 for (n = 0; n < ms->possible_cpus->len; n++) {
2892 ms->possible_cpus->cpus[n].type = ms->cpu_type;
2893 ms->possible_cpus->cpus[n].arch_id =
2894 virt_cpu_mp_affinity(vms, n);
2895
2896 assert(!mc->smp_props.dies_supported);
2897 ms->possible_cpus->cpus[n].props.has_socket_id = true;
2898 ms->possible_cpus->cpus[n].props.socket_id =
2899 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
2900 ms->possible_cpus->cpus[n].props.has_cluster_id = true;
2901 ms->possible_cpus->cpus[n].props.cluster_id =
2902 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
2903 ms->possible_cpus->cpus[n].props.has_core_id = true;
2904 ms->possible_cpus->cpus[n].props.core_id =
2905 (n / ms->smp.threads) % ms->smp.cores;
2906 ms->possible_cpus->cpus[n].props.has_thread_id = true;
2907 ms->possible_cpus->cpus[n].props.thread_id =
2908 n % ms->smp.threads;
2909 }
2910 return ms->possible_cpus;
2911 }
2912
virt_memory_pre_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2913 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2914 Error **errp)
2915 {
2916 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2917 const MachineState *ms = MACHINE(hotplug_dev);
2918 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2919
2920 if (!vms->acpi_dev) {
2921 error_setg(errp,
2922 "memory hotplug is not enabled: missing acpi-ged device");
2923 return;
2924 }
2925
2926 if (vms->mte) {
2927 error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
2928 return;
2929 }
2930
2931 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2932 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2933 return;
2934 }
2935
2936 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp);
2937 }
2938
virt_memory_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2939 static void virt_memory_plug(HotplugHandler *hotplug_dev,
2940 DeviceState *dev, Error **errp)
2941 {
2942 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2943 MachineState *ms = MACHINE(hotplug_dev);
2944 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2945
2946 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
2947
2948 if (is_nvdimm) {
2949 nvdimm_plug(ms->nvdimms_state);
2950 }
2951
2952 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2953 dev, &error_abort);
2954 }
2955
virt_machine_device_pre_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2956 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2957 DeviceState *dev, Error **errp)
2958 {
2959 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2960
2961 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2962 virt_memory_pre_plug(hotplug_dev, dev, errp);
2963 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2964 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2965 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2966 hwaddr db_start = 0, db_end = 0;
2967 QList *reserved_regions;
2968 char *resv_prop_str;
2969
2970 if (vms->iommu != VIRT_IOMMU_NONE) {
2971 error_setg(errp, "virt machine does not support multiple IOMMUs");
2972 return;
2973 }
2974
2975 switch (vms->msi_controller) {
2976 case VIRT_MSI_CTRL_NONE:
2977 return;
2978 case VIRT_MSI_CTRL_ITS:
2979 /* GITS_TRANSLATER page */
2980 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
2981 db_end = base_memmap[VIRT_GIC_ITS].base +
2982 base_memmap[VIRT_GIC_ITS].size - 1;
2983 break;
2984 case VIRT_MSI_CTRL_GICV2M:
2985 /* MSI_SETSPI_NS page */
2986 db_start = base_memmap[VIRT_GIC_V2M].base;
2987 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2988 break;
2989 }
2990 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
2991 db_start, db_end,
2992 VIRTIO_IOMMU_RESV_MEM_T_MSI);
2993
2994 reserved_regions = qlist_new();
2995 qlist_append_str(reserved_regions, resv_prop_str);
2996 qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
2997 g_free(resv_prop_str);
2998 }
2999 }
3000
virt_machine_device_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3001 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
3002 DeviceState *dev, Error **errp)
3003 {
3004 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
3005
3006 if (vms->platform_bus_dev) {
3007 MachineClass *mc = MACHINE_GET_CLASS(vms);
3008
3009 if (device_is_dynamic_sysbus(mc, dev)) {
3010 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
3011 SYS_BUS_DEVICE(dev));
3012 }
3013 }
3014
3015 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3016 virt_memory_plug(hotplug_dev, dev, errp);
3017 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
3018 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
3019 }
3020
3021 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
3022 PCIDevice *pdev = PCI_DEVICE(dev);
3023
3024 vms->iommu = VIRT_IOMMU_VIRTIO;
3025 vms->virtio_iommu_bdf = pci_get_bdf(pdev);
3026 create_virtio_iommu_dt_bindings(vms);
3027 }
3028 }
3029
virt_dimm_unplug_request(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3030 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
3031 DeviceState *dev, Error **errp)
3032 {
3033 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
3034
3035 if (!vms->acpi_dev) {
3036 error_setg(errp,
3037 "memory hotplug is not enabled: missing acpi-ged device");
3038 return;
3039 }
3040
3041 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
3042 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
3043 return;
3044 }
3045
3046 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
3047 errp);
3048 }
3049
virt_dimm_unplug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3050 static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
3051 DeviceState *dev, Error **errp)
3052 {
3053 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
3054 Error *local_err = NULL;
3055
3056 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
3057 if (local_err) {
3058 goto out;
3059 }
3060
3061 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
3062 qdev_unrealize(dev);
3063
3064 out:
3065 error_propagate(errp, local_err);
3066 }
3067
virt_machine_device_unplug_request_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3068 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
3069 DeviceState *dev, Error **errp)
3070 {
3071 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3072 virt_dimm_unplug_request(hotplug_dev, dev, errp);
3073 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
3074 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
3075 errp);
3076 } else {
3077 error_setg(errp, "device unplug request for unsupported device"
3078 " type: %s", object_get_typename(OBJECT(dev)));
3079 }
3080 }
3081
virt_machine_device_unplug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)3082 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
3083 DeviceState *dev, Error **errp)
3084 {
3085 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
3086 virt_dimm_unplug(hotplug_dev, dev, errp);
3087 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
3088 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
3089 } else {
3090 error_setg(errp, "virt: device unplug for unsupported device"
3091 " type: %s", object_get_typename(OBJECT(dev)));
3092 }
3093 }
3094
virt_machine_get_hotplug_handler(MachineState * machine,DeviceState * dev)3095 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
3096 DeviceState *dev)
3097 {
3098 MachineClass *mc = MACHINE_GET_CLASS(machine);
3099
3100 if (device_is_dynamic_sysbus(mc, dev) ||
3101 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3102 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
3103 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
3104 return HOTPLUG_HANDLER(machine);
3105 }
3106 return NULL;
3107 }
3108
3109 /*
3110 * for arm64 kvm_type [7-0] encodes the requested number of bits
3111 * in the IPA address space
3112 */
virt_kvm_type(MachineState * ms,const char * type_str)3113 static int virt_kvm_type(MachineState *ms, const char *type_str)
3114 {
3115 VirtMachineState *vms = VIRT_MACHINE(ms);
3116 int max_vm_pa_size, requested_pa_size;
3117 bool fixed_ipa;
3118
3119 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
3120
3121 /* we freeze the memory map to compute the highest gpa */
3122 virt_set_memmap(vms, max_vm_pa_size);
3123
3124 requested_pa_size = 64 - clz64(vms->highest_gpa);
3125
3126 /*
3127 * KVM requires the IPA size to be at least 32 bits.
3128 */
3129 if (requested_pa_size < 32) {
3130 requested_pa_size = 32;
3131 }
3132
3133 if (requested_pa_size > max_vm_pa_size) {
3134 error_report("-m and ,maxmem option values "
3135 "require an IPA range (%d bits) larger than "
3136 "the one supported by the host (%d bits)",
3137 requested_pa_size, max_vm_pa_size);
3138 return -1;
3139 }
3140 /*
3141 * We return the requested PA log size, unless KVM only supports
3142 * the implicit legacy 40b IPA setting, in which case the kvm_type
3143 * must be 0.
3144 */
3145 return fixed_ipa ? 0 : requested_pa_size;
3146 }
3147
virt_hvf_get_physical_address_range(MachineState * ms)3148 static int virt_hvf_get_physical_address_range(MachineState *ms)
3149 {
3150 VirtMachineState *vms = VIRT_MACHINE(ms);
3151
3152 int default_ipa_size = hvf_arm_get_default_ipa_bit_size();
3153 int max_ipa_size = hvf_arm_get_max_ipa_bit_size();
3154
3155 /* We freeze the memory map to compute the highest gpa */
3156 virt_set_memmap(vms, max_ipa_size);
3157
3158 int requested_ipa_size = 64 - clz64(vms->highest_gpa);
3159
3160 /*
3161 * If we're <= the default IPA size just use the default.
3162 * If we're above the default but below the maximum, round up to
3163 * the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only
3164 * returns values that are valid ARM PARange values.
3165 */
3166 if (requested_ipa_size <= default_ipa_size) {
3167 requested_ipa_size = default_ipa_size;
3168 } else if (requested_ipa_size <= max_ipa_size) {
3169 requested_ipa_size = max_ipa_size;
3170 } else {
3171 error_report("-m and ,maxmem option values "
3172 "require an IPA range (%d bits) larger than "
3173 "the one supported by the host (%d bits)",
3174 requested_ipa_size, max_ipa_size);
3175 return -1;
3176 }
3177
3178 return requested_ipa_size;
3179 }
3180
virt_machine_class_init(ObjectClass * oc,const void * data)3181 static void virt_machine_class_init(ObjectClass *oc, const void *data)
3182 {
3183 MachineClass *mc = MACHINE_CLASS(oc);
3184 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3185 static const char * const valid_cpu_types[] = {
3186 #ifdef CONFIG_TCG
3187 ARM_CPU_TYPE_NAME("cortex-a7"),
3188 ARM_CPU_TYPE_NAME("cortex-a15"),
3189 #ifdef TARGET_AARCH64
3190 ARM_CPU_TYPE_NAME("cortex-a35"),
3191 ARM_CPU_TYPE_NAME("cortex-a55"),
3192 ARM_CPU_TYPE_NAME("cortex-a72"),
3193 ARM_CPU_TYPE_NAME("cortex-a76"),
3194 ARM_CPU_TYPE_NAME("cortex-a710"),
3195 ARM_CPU_TYPE_NAME("a64fx"),
3196 ARM_CPU_TYPE_NAME("neoverse-n1"),
3197 ARM_CPU_TYPE_NAME("neoverse-v1"),
3198 ARM_CPU_TYPE_NAME("neoverse-n2"),
3199 #endif /* TARGET_AARCH64 */
3200 #endif /* CONFIG_TCG */
3201 #ifdef TARGET_AARCH64
3202 ARM_CPU_TYPE_NAME("cortex-a53"),
3203 ARM_CPU_TYPE_NAME("cortex-a57"),
3204 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
3205 ARM_CPU_TYPE_NAME("host"),
3206 #endif /* CONFIG_KVM || CONFIG_HVF */
3207 #endif /* TARGET_AARCH64 */
3208 ARM_CPU_TYPE_NAME("max"),
3209 NULL
3210 };
3211
3212 mc->init = machvirt_init;
3213 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
3214 * The value may be reduced later when we have more information about the
3215 * configuration of the particular instance.
3216 */
3217 mc->max_cpus = 512;
3218 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
3219 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
3220 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
3221 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
3222 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_UEFI_VARS_SYSBUS);
3223 #ifdef CONFIG_TPM
3224 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
3225 #endif
3226 mc->block_default_type = IF_VIRTIO;
3227 mc->no_cdrom = 1;
3228 mc->pci_allow_0_address = true;
3229 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
3230 mc->minimum_page_bits = 12;
3231 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
3232 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
3233 #ifdef CONFIG_TCG
3234 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
3235 #else
3236 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
3237 #endif
3238 mc->valid_cpu_types = valid_cpu_types;
3239 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
3240 mc->kvm_type = virt_kvm_type;
3241 mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range;
3242 assert(!mc->get_hotplug_handler);
3243 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
3244 hc->pre_plug = virt_machine_device_pre_plug_cb;
3245 hc->plug = virt_machine_device_plug_cb;
3246 hc->unplug_request = virt_machine_device_unplug_request_cb;
3247 hc->unplug = virt_machine_device_unplug_cb;
3248 mc->nvdimm_supported = true;
3249 mc->smp_props.clusters_supported = true;
3250 mc->auto_enable_numa_with_memhp = true;
3251 mc->auto_enable_numa_with_memdev = true;
3252 /* platform instead of architectural choice */
3253 mc->cpu_cluster_has_numa_boundary = true;
3254 mc->default_ram_id = "mach-virt.ram";
3255 mc->default_nic = "virtio-net-pci";
3256
3257 object_class_property_add(oc, "acpi", "OnOffAuto",
3258 virt_get_acpi, virt_set_acpi,
3259 NULL, NULL);
3260 object_class_property_set_description(oc, "acpi",
3261 "Enable ACPI");
3262 object_class_property_add_bool(oc, "secure", virt_get_secure,
3263 virt_set_secure);
3264 object_class_property_set_description(oc, "secure",
3265 "Set on/off to enable/disable the ARM "
3266 "Security Extensions (TrustZone)");
3267
3268 object_class_property_add_bool(oc, "virtualization", virt_get_virt,
3269 virt_set_virt);
3270 object_class_property_set_description(oc, "virtualization",
3271 "Set on/off to enable/disable emulating a "
3272 "guest CPU which implements the ARM "
3273 "Virtualization Extensions");
3274
3275 object_class_property_add_bool(oc, "highmem", virt_get_highmem,
3276 virt_set_highmem);
3277 object_class_property_set_description(oc, "highmem",
3278 "Set on/off to enable/disable using "
3279 "physical address space above 32 bits");
3280
3281 object_class_property_add_bool(oc, "compact-highmem",
3282 virt_get_compact_highmem,
3283 virt_set_compact_highmem);
3284 object_class_property_set_description(oc, "compact-highmem",
3285 "Set on/off to enable/disable compact "
3286 "layout for high memory regions");
3287
3288 object_class_property_add_bool(oc, "highmem-redists",
3289 virt_get_highmem_redists,
3290 virt_set_highmem_redists);
3291 object_class_property_set_description(oc, "highmem-redists",
3292 "Set on/off to enable/disable high "
3293 "memory region for GICv3 or GICv4 "
3294 "redistributor");
3295
3296 object_class_property_add_bool(oc, "highmem-ecam",
3297 virt_get_highmem_ecam,
3298 virt_set_highmem_ecam);
3299 object_class_property_set_description(oc, "highmem-ecam",
3300 "Set on/off to enable/disable high "
3301 "memory region for PCI ECAM");
3302
3303 object_class_property_add_bool(oc, "highmem-mmio",
3304 virt_get_highmem_mmio,
3305 virt_set_highmem_mmio);
3306 object_class_property_set_description(oc, "highmem-mmio",
3307 "Set on/off to enable/disable high "
3308 "memory region for PCI MMIO");
3309
3310 object_class_property_add(oc, "highmem-mmio-size", "size",
3311 virt_get_highmem_mmio_size,
3312 virt_set_highmem_mmio_size,
3313 NULL, NULL);
3314 object_class_property_set_description(oc, "highmem-mmio-size",
3315 "Set the high memory region size "
3316 "for PCI MMIO");
3317
3318 object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
3319 virt_set_gic_version);
3320 object_class_property_set_description(oc, "gic-version",
3321 "Set GIC version. "
3322 "Valid values are 2, 3, 4, host and max");
3323
3324 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu);
3325 object_class_property_set_description(oc, "iommu",
3326 "Set the IOMMU type. "
3327 "Valid values are none and smmuv3");
3328
3329 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
3330 virt_get_default_bus_bypass_iommu,
3331 virt_set_default_bus_bypass_iommu);
3332 object_class_property_set_description(oc, "default-bus-bypass-iommu",
3333 "Set on/off to enable/disable "
3334 "bypass_iommu for default root bus");
3335
3336 object_class_property_add_bool(oc, "ras", virt_get_ras,
3337 virt_set_ras);
3338 object_class_property_set_description(oc, "ras",
3339 "Set on/off to enable/disable reporting host memory errors "
3340 "to a KVM guest using ACPI and guest external abort exceptions");
3341
3342 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte);
3343 object_class_property_set_description(oc, "mte",
3344 "Set on/off to enable/disable emulating a "
3345 "guest CPU which implements the ARM "
3346 "Memory Tagging Extension");
3347
3348 object_class_property_add_bool(oc, "its", virt_get_its,
3349 virt_set_its);
3350 object_class_property_set_description(oc, "its",
3351 "Set on/off to enable/disable "
3352 "ITS instantiation");
3353
3354 object_class_property_add_bool(oc, "dtb-randomness",
3355 virt_get_dtb_randomness,
3356 virt_set_dtb_randomness);
3357 object_class_property_set_description(oc, "dtb-randomness",
3358 "Set off to disable passing random or "
3359 "non-deterministic dtb nodes to guest");
3360
3361 object_class_property_add_bool(oc, "dtb-kaslr-seed",
3362 virt_get_dtb_randomness,
3363 virt_set_dtb_randomness);
3364 object_class_property_set_description(oc, "dtb-kaslr-seed",
3365 "Deprecated synonym of dtb-randomness");
3366
3367 object_class_property_add_str(oc, "x-oem-id",
3368 virt_get_oem_id,
3369 virt_set_oem_id);
3370 object_class_property_set_description(oc, "x-oem-id",
3371 "Override the default value of field OEMID "
3372 "in ACPI table header."
3373 "The string may be up to 6 bytes in size");
3374
3375
3376 object_class_property_add_str(oc, "x-oem-table-id",
3377 virt_get_oem_table_id,
3378 virt_set_oem_table_id);
3379 object_class_property_set_description(oc, "x-oem-table-id",
3380 "Override the default value of field OEM Table ID "
3381 "in ACPI table header."
3382 "The string may be up to 8 bytes in size");
3383
3384 }
3385
virt_instance_init(Object * obj)3386 static void virt_instance_init(Object *obj)
3387 {
3388 VirtMachineState *vms = VIRT_MACHINE(obj);
3389 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
3390
3391 /* EL3 is disabled by default on virt: this makes us consistent
3392 * between KVM and TCG for this board, and it also allows us to
3393 * boot UEFI blobs which assume no TrustZone support.
3394 */
3395 vms->secure = false;
3396
3397 /* EL2 is also disabled by default, for similar reasons */
3398 vms->virt = false;
3399
3400 /* High memory is enabled by default */
3401 vms->highmem = true;
3402 vms->highmem_compact = !vmc->no_highmem_compact;
3403 vms->gic_version = VIRT_GIC_VERSION_NOSEL;
3404
3405 vms->highmem_ecam = true;
3406 vms->highmem_mmio = true;
3407 vms->highmem_redists = true;
3408
3409 /* Default allows ITS instantiation */
3410 vms->its = true;
3411 /* Allow ITS emulation if the machine version supports it */
3412 vms->tcg_its = !vmc->no_tcg_its;
3413
3414 /* Default disallows iommu instantiation */
3415 vms->iommu = VIRT_IOMMU_NONE;
3416
3417 /* The default root bus is attached to iommu by default */
3418 vms->default_bus_bypass_iommu = false;
3419
3420 /* Default disallows RAS instantiation */
3421 vms->ras = false;
3422
3423 /* MTE is disabled by default. */
3424 vms->mte = false;
3425
3426 /* Supply kaslr-seed and rng-seed by default */
3427 vms->dtb_randomness = true;
3428
3429 vms->irqmap = a15irqmap;
3430
3431 virt_flash_create(vms);
3432
3433 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
3434 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
3435 cxl_machine_init(obj, &vms->cxl_devices_state);
3436 }
3437
3438 static const TypeInfo virt_machine_info = {
3439 .name = TYPE_VIRT_MACHINE,
3440 .parent = TYPE_MACHINE,
3441 .abstract = true,
3442 .instance_size = sizeof(VirtMachineState),
3443 .class_size = sizeof(VirtMachineClass),
3444 .class_init = virt_machine_class_init,
3445 .instance_init = virt_instance_init,
3446 .interfaces = (const InterfaceInfo[]) {
3447 { TYPE_HOTPLUG_HANDLER },
3448 { }
3449 },
3450 };
3451
machvirt_machine_init(void)3452 static void machvirt_machine_init(void)
3453 {
3454 type_register_static(&virt_machine_info);
3455 }
3456 type_init(machvirt_machine_init);
3457
virt_machine_10_1_options(MachineClass * mc)3458 static void virt_machine_10_1_options(MachineClass *mc)
3459 {
3460 }
3461 DEFINE_VIRT_MACHINE_AS_LATEST(10, 1)
3462
virt_machine_10_0_options(MachineClass * mc)3463 static void virt_machine_10_0_options(MachineClass *mc)
3464 {
3465 virt_machine_10_1_options(mc);
3466 compat_props_add(mc->compat_props, hw_compat_10_0, hw_compat_10_0_len);
3467 }
3468 DEFINE_VIRT_MACHINE(10, 0)
3469
virt_machine_9_2_options(MachineClass * mc)3470 static void virt_machine_9_2_options(MachineClass *mc)
3471 {
3472 virt_machine_10_0_options(mc);
3473 compat_props_add(mc->compat_props, hw_compat_9_2, hw_compat_9_2_len);
3474 }
3475 DEFINE_VIRT_MACHINE(9, 2)
3476
virt_machine_9_1_options(MachineClass * mc)3477 static void virt_machine_9_1_options(MachineClass *mc)
3478 {
3479 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3480
3481 virt_machine_9_2_options(mc);
3482 compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len);
3483 /* 9.1 and earlier have only a stage-1 SMMU, not a nested s1+2 one */
3484 vmc->no_nested_smmu = true;
3485 }
3486 DEFINE_VIRT_MACHINE(9, 1)
3487
virt_machine_9_0_options(MachineClass * mc)3488 static void virt_machine_9_0_options(MachineClass *mc)
3489 {
3490 virt_machine_9_1_options(mc);
3491 mc->smbios_memory_device_size = 16 * GiB;
3492 compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len);
3493 }
3494 DEFINE_VIRT_MACHINE(9, 0)
3495
virt_machine_8_2_options(MachineClass * mc)3496 static void virt_machine_8_2_options(MachineClass *mc)
3497 {
3498 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3499
3500 virt_machine_9_0_options(mc);
3501 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
3502 /*
3503 * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
3504 * earlier machines. (Exposing it tickles a bug in older EDK2
3505 * guest BIOS binaries.)
3506 */
3507 vmc->no_ns_el2_virt_timer_irq = true;
3508 }
3509 DEFINE_VIRT_MACHINE(8, 2)
3510
virt_machine_8_1_options(MachineClass * mc)3511 static void virt_machine_8_1_options(MachineClass *mc)
3512 {
3513 virt_machine_8_2_options(mc);
3514 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len);
3515 }
3516 DEFINE_VIRT_MACHINE(8, 1)
3517
virt_machine_8_0_options(MachineClass * mc)3518 static void virt_machine_8_0_options(MachineClass *mc)
3519 {
3520 virt_machine_8_1_options(mc);
3521 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len);
3522 }
3523 DEFINE_VIRT_MACHINE(8, 0)
3524
virt_machine_7_2_options(MachineClass * mc)3525 static void virt_machine_7_2_options(MachineClass *mc)
3526 {
3527 virt_machine_8_0_options(mc);
3528 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len);
3529 }
3530 DEFINE_VIRT_MACHINE(7, 2)
3531
virt_machine_7_1_options(MachineClass * mc)3532 static void virt_machine_7_1_options(MachineClass *mc)
3533 {
3534 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3535
3536 virt_machine_7_2_options(mc);
3537 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
3538 /* Compact layout for high memory regions was introduced with 7.2 */
3539 vmc->no_highmem_compact = true;
3540 }
3541 DEFINE_VIRT_MACHINE(7, 1)
3542
virt_machine_7_0_options(MachineClass * mc)3543 static void virt_machine_7_0_options(MachineClass *mc)
3544 {
3545 virt_machine_7_1_options(mc);
3546 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len);
3547 }
3548 DEFINE_VIRT_MACHINE(7, 0)
3549
virt_machine_6_2_options(MachineClass * mc)3550 static void virt_machine_6_2_options(MachineClass *mc)
3551 {
3552 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3553
3554 virt_machine_7_0_options(mc);
3555 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len);
3556 vmc->no_tcg_lpa2 = true;
3557 }
3558 DEFINE_VIRT_MACHINE(6, 2)
3559
virt_machine_6_1_options(MachineClass * mc)3560 static void virt_machine_6_1_options(MachineClass *mc)
3561 {
3562 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3563
3564 virt_machine_6_2_options(mc);
3565 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
3566 mc->smp_props.prefer_sockets = true;
3567 vmc->no_cpu_topology = true;
3568
3569 /* qemu ITS was introduced with 6.2 */
3570 vmc->no_tcg_its = true;
3571 }
3572 DEFINE_VIRT_MACHINE(6, 1)
3573
virt_machine_6_0_options(MachineClass * mc)3574 static void virt_machine_6_0_options(MachineClass *mc)
3575 {
3576 virt_machine_6_1_options(mc);
3577 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
3578 }
3579 DEFINE_VIRT_MACHINE(6, 0)
3580
virt_machine_5_2_options(MachineClass * mc)3581 static void virt_machine_5_2_options(MachineClass *mc)
3582 {
3583 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3584
3585 virt_machine_6_0_options(mc);
3586 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
3587 vmc->no_secure_gpio = true;
3588 }
3589 DEFINE_VIRT_MACHINE(5, 2)
3590
virt_machine_5_1_options(MachineClass * mc)3591 static void virt_machine_5_1_options(MachineClass *mc)
3592 {
3593 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3594
3595 virt_machine_5_2_options(mc);
3596 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
3597 vmc->no_kvm_steal_time = true;
3598 }
3599 DEFINE_VIRT_MACHINE(5, 1)
3600
virt_machine_5_0_options(MachineClass * mc)3601 static void virt_machine_5_0_options(MachineClass *mc)
3602 {
3603 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3604
3605 virt_machine_5_1_options(mc);
3606 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
3607 mc->numa_mem_supported = true;
3608 vmc->acpi_expose_flash = true;
3609 mc->auto_enable_numa_with_memdev = false;
3610 }
3611 DEFINE_VIRT_MACHINE(5, 0)
3612
virt_machine_4_2_options(MachineClass * mc)3613 static void virt_machine_4_2_options(MachineClass *mc)
3614 {
3615 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3616
3617 virt_machine_5_0_options(mc);
3618 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
3619 vmc->kvm_no_adjvtime = true;
3620 }
3621 DEFINE_VIRT_MACHINE(4, 2)
3622
virt_machine_4_1_options(MachineClass * mc)3623 static void virt_machine_4_1_options(MachineClass *mc)
3624 {
3625 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3626
3627 virt_machine_4_2_options(mc);
3628 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
3629 vmc->no_ged = true;
3630 mc->auto_enable_numa_with_memhp = false;
3631 }
3632 DEFINE_VIRT_MACHINE(4, 1)
3633