1 /*
2  * Copyright 2012-15 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "dm_services.h"
27 
28 #include "resource.h"
29 #include "include/irq_service_interface.h"
30 #include "link_encoder.h"
31 #include "stream_encoder.h"
32 #include "opp.h"
33 #include "timing_generator.h"
34 #include "transform.h"
35 #include "dccg.h"
36 #include "dchubbub.h"
37 #include "dpp.h"
38 #include "core_types.h"
39 #include "set_mode_types.h"
40 #include "virtual/virtual_stream_encoder.h"
41 #include "dpcd_defs.h"
42 #include "link_enc_cfg.h"
43 #include "link.h"
44 #include "virtual/virtual_link_hwss.h"
45 #include "link/hwss/link_hwss_dio.h"
46 #include "link/hwss/link_hwss_dpia.h"
47 #include "link/hwss/link_hwss_hpo_dp.h"
48 #include "link/hwss/link_hwss_dio_fixed_vs_pe_retimer.h"
49 #include "link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.h"
50 
51 #if defined(CONFIG_DRM_AMD_DC_SI)
52 #include "dce60/dce60_resource.h"
53 #endif
54 #include "dce80/dce80_resource.h"
55 #include "dce100/dce100_resource.h"
56 #include "dce110/dce110_resource.h"
57 #include "dce112/dce112_resource.h"
58 #include "dce120/dce120_resource.h"
59 #include "dcn10/dcn10_resource.h"
60 #include "dcn20/dcn20_resource.h"
61 #include "dcn21/dcn21_resource.h"
62 #include "dcn201/dcn201_resource.h"
63 #include "dcn30/dcn30_resource.h"
64 #include "dcn301/dcn301_resource.h"
65 #include "dcn302/dcn302_resource.h"
66 #include "dcn303/dcn303_resource.h"
67 #include "dcn31/dcn31_resource.h"
68 #include "dcn314/dcn314_resource.h"
69 #include "dcn315/dcn315_resource.h"
70 #include "dcn316/dcn316_resource.h"
71 #include "../dcn32/dcn32_resource.h"
72 #include "../dcn321/dcn321_resource.h"
73 
74 #define VISUAL_CONFIRM_BASE_DEFAULT 3
75 #define VISUAL_CONFIRM_BASE_MIN 1
76 #define VISUAL_CONFIRM_BASE_MAX 10
77 /* we choose 240 because it is a common denominator of common v addressable
78  * such as 2160, 1440, 1200, 960. So we take 1/240 portion of v addressable as
79  * the visual confirm dpp offset height. So visual confirm height can stay
80  * relatively the same independent from timing used.
81  */
82 #define VISUAL_CONFIRM_DPP_OFFSET_DENO 240
83 
84 #define DC_LOGGER_INIT(logger)
85 
86 #define UNABLE_TO_SPLIT -1
87 
resource_parse_asic_id(struct hw_asic_id asic_id)88 enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
89 {
90 	enum dce_version dc_version = DCE_VERSION_UNKNOWN;
91 
92 	switch (asic_id.chip_family) {
93 
94 #if defined(CONFIG_DRM_AMD_DC_SI)
95 	case FAMILY_SI:
96 		if (ASIC_REV_IS_TAHITI_P(asic_id.hw_internal_rev) ||
97 		    ASIC_REV_IS_PITCAIRN_PM(asic_id.hw_internal_rev) ||
98 		    ASIC_REV_IS_CAPEVERDE_M(asic_id.hw_internal_rev))
99 			dc_version = DCE_VERSION_6_0;
100 		else if (ASIC_REV_IS_OLAND_M(asic_id.hw_internal_rev))
101 			dc_version = DCE_VERSION_6_4;
102 		else
103 			dc_version = DCE_VERSION_6_1;
104 		break;
105 #endif
106 	case FAMILY_CI:
107 		dc_version = DCE_VERSION_8_0;
108 		break;
109 	case FAMILY_KV:
110 		if (ASIC_REV_IS_KALINDI(asic_id.hw_internal_rev) ||
111 		    ASIC_REV_IS_BHAVANI(asic_id.hw_internal_rev) ||
112 		    ASIC_REV_IS_GODAVARI(asic_id.hw_internal_rev))
113 			dc_version = DCE_VERSION_8_3;
114 		else
115 			dc_version = DCE_VERSION_8_1;
116 		break;
117 	case FAMILY_CZ:
118 		dc_version = DCE_VERSION_11_0;
119 		break;
120 
121 	case FAMILY_VI:
122 		if (ASIC_REV_IS_TONGA_P(asic_id.hw_internal_rev) ||
123 				ASIC_REV_IS_FIJI_P(asic_id.hw_internal_rev)) {
124 			dc_version = DCE_VERSION_10_0;
125 			break;
126 		}
127 		if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) ||
128 				ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) ||
129 				ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) {
130 			dc_version = DCE_VERSION_11_2;
131 		}
132 		if (ASIC_REV_IS_VEGAM(asic_id.hw_internal_rev))
133 			dc_version = DCE_VERSION_11_22;
134 		break;
135 	case FAMILY_AI:
136 		if (ASICREV_IS_VEGA20_P(asic_id.hw_internal_rev))
137 			dc_version = DCE_VERSION_12_1;
138 		else
139 			dc_version = DCE_VERSION_12_0;
140 		break;
141 	case FAMILY_RV:
142 		dc_version = DCN_VERSION_1_0;
143 		if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
144 			dc_version = DCN_VERSION_1_01;
145 		if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev))
146 			dc_version = DCN_VERSION_2_1;
147 		if (ASICREV_IS_GREEN_SARDINE(asic_id.hw_internal_rev))
148 			dc_version = DCN_VERSION_2_1;
149 		break;
150 
151 	case FAMILY_NV:
152 		dc_version = DCN_VERSION_2_0;
153 		if (asic_id.chip_id == DEVICE_ID_NV_13FE || asic_id.chip_id == DEVICE_ID_NV_143F) {
154 			dc_version = DCN_VERSION_2_01;
155 			break;
156 		}
157 		if (ASICREV_IS_SIENNA_CICHLID_P(asic_id.hw_internal_rev))
158 			dc_version = DCN_VERSION_3_0;
159 		if (ASICREV_IS_DIMGREY_CAVEFISH_P(asic_id.hw_internal_rev))
160 			dc_version = DCN_VERSION_3_02;
161 		if (ASICREV_IS_BEIGE_GOBY_P(asic_id.hw_internal_rev))
162 			dc_version = DCN_VERSION_3_03;
163 		break;
164 
165 	case FAMILY_VGH:
166 		dc_version = DCN_VERSION_3_01;
167 		break;
168 
169 	case FAMILY_YELLOW_CARP:
170 		if (ASICREV_IS_YELLOW_CARP(asic_id.hw_internal_rev))
171 			dc_version = DCN_VERSION_3_1;
172 		break;
173 	case AMDGPU_FAMILY_GC_10_3_6:
174 		if (ASICREV_IS_GC_10_3_6(asic_id.hw_internal_rev))
175 			dc_version = DCN_VERSION_3_15;
176 		break;
177 	case AMDGPU_FAMILY_GC_10_3_7:
178 		if (ASICREV_IS_GC_10_3_7(asic_id.hw_internal_rev))
179 			dc_version = DCN_VERSION_3_16;
180 		break;
181 	case AMDGPU_FAMILY_GC_11_0_0:
182 		dc_version = DCN_VERSION_3_2;
183 		if (ASICREV_IS_GC_11_0_2(asic_id.hw_internal_rev))
184 			dc_version = DCN_VERSION_3_21;
185 		break;
186 	case AMDGPU_FAMILY_GC_11_0_1:
187 		dc_version = DCN_VERSION_3_14;
188 		break;
189 	default:
190 		dc_version = DCE_VERSION_UNKNOWN;
191 		break;
192 	}
193 	return dc_version;
194 }
195 
dc_create_resource_pool(struct dc * dc,const struct dc_init_data * init_data,enum dce_version dc_version)196 struct resource_pool *dc_create_resource_pool(struct dc  *dc,
197 					      const struct dc_init_data *init_data,
198 					      enum dce_version dc_version)
199 {
200 	struct resource_pool *res_pool = NULL;
201 
202 	switch (dc_version) {
203 #if defined(CONFIG_DRM_AMD_DC_SI)
204 	case DCE_VERSION_6_0:
205 		res_pool = dce60_create_resource_pool(
206 			init_data->num_virtual_links, dc);
207 		break;
208 	case DCE_VERSION_6_1:
209 		res_pool = dce61_create_resource_pool(
210 			init_data->num_virtual_links, dc);
211 		break;
212 	case DCE_VERSION_6_4:
213 		res_pool = dce64_create_resource_pool(
214 			init_data->num_virtual_links, dc);
215 		break;
216 #endif
217 	case DCE_VERSION_8_0:
218 		res_pool = dce80_create_resource_pool(
219 				init_data->num_virtual_links, dc);
220 		break;
221 	case DCE_VERSION_8_1:
222 		res_pool = dce81_create_resource_pool(
223 				init_data->num_virtual_links, dc);
224 		break;
225 	case DCE_VERSION_8_3:
226 		res_pool = dce83_create_resource_pool(
227 				init_data->num_virtual_links, dc);
228 		break;
229 	case DCE_VERSION_10_0:
230 		res_pool = dce100_create_resource_pool(
231 				init_data->num_virtual_links, dc);
232 		break;
233 	case DCE_VERSION_11_0:
234 		res_pool = dce110_create_resource_pool(
235 				init_data->num_virtual_links, dc,
236 				init_data->asic_id);
237 		break;
238 	case DCE_VERSION_11_2:
239 	case DCE_VERSION_11_22:
240 		res_pool = dce112_create_resource_pool(
241 				init_data->num_virtual_links, dc);
242 		break;
243 	case DCE_VERSION_12_0:
244 	case DCE_VERSION_12_1:
245 		res_pool = dce120_create_resource_pool(
246 				init_data->num_virtual_links, dc);
247 		break;
248 
249 #if defined(CONFIG_DRM_AMD_DC_FP)
250 	case DCN_VERSION_1_0:
251 	case DCN_VERSION_1_01:
252 		res_pool = dcn10_create_resource_pool(init_data, dc);
253 		break;
254 	case DCN_VERSION_2_0:
255 		res_pool = dcn20_create_resource_pool(init_data, dc);
256 		break;
257 	case DCN_VERSION_2_1:
258 		res_pool = dcn21_create_resource_pool(init_data, dc);
259 		break;
260 	case DCN_VERSION_2_01:
261 		res_pool = dcn201_create_resource_pool(init_data, dc);
262 		break;
263 	case DCN_VERSION_3_0:
264 		res_pool = dcn30_create_resource_pool(init_data, dc);
265 		break;
266 	case DCN_VERSION_3_01:
267 		res_pool = dcn301_create_resource_pool(init_data, dc);
268 		break;
269 	case DCN_VERSION_3_02:
270 		res_pool = dcn302_create_resource_pool(init_data, dc);
271 		break;
272 	case DCN_VERSION_3_03:
273 		res_pool = dcn303_create_resource_pool(init_data, dc);
274 		break;
275 	case DCN_VERSION_3_1:
276 		res_pool = dcn31_create_resource_pool(init_data, dc);
277 		break;
278 	case DCN_VERSION_3_14:
279 		res_pool = dcn314_create_resource_pool(init_data, dc);
280 		break;
281 	case DCN_VERSION_3_15:
282 		res_pool = dcn315_create_resource_pool(init_data, dc);
283 		break;
284 	case DCN_VERSION_3_16:
285 		res_pool = dcn316_create_resource_pool(init_data, dc);
286 		break;
287 	case DCN_VERSION_3_2:
288 		res_pool = dcn32_create_resource_pool(init_data, dc);
289 		break;
290 	case DCN_VERSION_3_21:
291 		res_pool = dcn321_create_resource_pool(init_data, dc);
292 		break;
293 #endif /* CONFIG_DRM_AMD_DC_FP */
294 	default:
295 		break;
296 	}
297 
298 	if (res_pool != NULL) {
299 		if (dc->ctx->dc_bios->fw_info_valid) {
300 			res_pool->ref_clocks.xtalin_clock_inKhz =
301 				dc->ctx->dc_bios->fw_info.pll_info.crystal_frequency;
302 			/* initialize with firmware data first, no all
303 			 * ASIC have DCCG SW component. FPGA or
304 			 * simulation need initialization of
305 			 * dccg_ref_clock_inKhz, dchub_ref_clock_inKhz
306 			 * with xtalin_clock_inKhz
307 			 */
308 			res_pool->ref_clocks.dccg_ref_clock_inKhz =
309 				res_pool->ref_clocks.xtalin_clock_inKhz;
310 			res_pool->ref_clocks.dchub_ref_clock_inKhz =
311 				res_pool->ref_clocks.xtalin_clock_inKhz;
312 		} else
313 			ASSERT_CRITICAL(false);
314 	}
315 
316 	return res_pool;
317 }
318 
dc_destroy_resource_pool(struct dc * dc)319 void dc_destroy_resource_pool(struct dc  *dc)
320 {
321 	if (dc) {
322 		if (dc->res_pool)
323 			dc->res_pool->funcs->destroy(&dc->res_pool);
324 
325 		kfree(dc->hwseq);
326 	}
327 }
328 
update_num_audio(const struct resource_straps * straps,unsigned int * num_audio,struct audio_support * aud_support)329 static void update_num_audio(
330 	const struct resource_straps *straps,
331 	unsigned int *num_audio,
332 	struct audio_support *aud_support)
333 {
334 	aud_support->dp_audio = true;
335 	aud_support->hdmi_audio_native = false;
336 	aud_support->hdmi_audio_on_dongle = false;
337 
338 	if (straps->hdmi_disable == 0) {
339 		if (straps->dc_pinstraps_audio & 0x2) {
340 			aud_support->hdmi_audio_on_dongle = true;
341 			aud_support->hdmi_audio_native = true;
342 		}
343 	}
344 
345 	switch (straps->audio_stream_number) {
346 	case 0: /* multi streams supported */
347 		break;
348 	case 1: /* multi streams not supported */
349 		*num_audio = 1;
350 		break;
351 	default:
352 		DC_ERR("DC: unexpected audio fuse!\n");
353 	}
354 }
355 
resource_construct(unsigned int num_virtual_links,struct dc * dc,struct resource_pool * pool,const struct resource_create_funcs * create_funcs)356 bool resource_construct(
357 	unsigned int num_virtual_links,
358 	struct dc  *dc,
359 	struct resource_pool *pool,
360 	const struct resource_create_funcs *create_funcs)
361 {
362 	struct dc_context *ctx = dc->ctx;
363 	const struct resource_caps *caps = pool->res_cap;
364 	int i;
365 	unsigned int num_audio = caps->num_audio;
366 	struct resource_straps straps = {0};
367 
368 	if (create_funcs->read_dce_straps)
369 		create_funcs->read_dce_straps(dc->ctx, &straps);
370 
371 	pool->audio_count = 0;
372 	if (create_funcs->create_audio) {
373 		/* find the total number of streams available via the
374 		 * AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT
375 		 * registers (one for each pin) starting from pin 1
376 		 * up to the max number of audio pins.
377 		 * We stop on the first pin where
378 		 * PORT_CONNECTIVITY == 1 (as instructed by HW team).
379 		 */
380 		update_num_audio(&straps, &num_audio, &pool->audio_support);
381 		for (i = 0; i < caps->num_audio; i++) {
382 			struct audio *aud = create_funcs->create_audio(ctx, i);
383 
384 			if (aud == NULL) {
385 				DC_ERR("DC: failed to create audio!\n");
386 				return false;
387 			}
388 			if (!aud->funcs->endpoint_valid(aud)) {
389 				aud->funcs->destroy(&aud);
390 				break;
391 			}
392 			pool->audios[i] = aud;
393 			pool->audio_count++;
394 		}
395 	}
396 
397 	pool->stream_enc_count = 0;
398 	if (create_funcs->create_stream_encoder) {
399 		for (i = 0; i < caps->num_stream_encoder; i++) {
400 			pool->stream_enc[i] = create_funcs->create_stream_encoder(i, ctx);
401 			if (pool->stream_enc[i] == NULL)
402 				DC_ERR("DC: failed to create stream_encoder!\n");
403 			pool->stream_enc_count++;
404 		}
405 	}
406 
407 	pool->hpo_dp_stream_enc_count = 0;
408 	if (create_funcs->create_hpo_dp_stream_encoder) {
409 		for (i = 0; i < caps->num_hpo_dp_stream_encoder; i++) {
410 			pool->hpo_dp_stream_enc[i] = create_funcs->create_hpo_dp_stream_encoder(i+ENGINE_ID_HPO_DP_0, ctx);
411 			if (pool->hpo_dp_stream_enc[i] == NULL)
412 				DC_ERR("DC: failed to create HPO DP stream encoder!\n");
413 			pool->hpo_dp_stream_enc_count++;
414 
415 		}
416 	}
417 
418 	pool->hpo_dp_link_enc_count = 0;
419 	if (create_funcs->create_hpo_dp_link_encoder) {
420 		for (i = 0; i < caps->num_hpo_dp_link_encoder; i++) {
421 			pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder(i, ctx);
422 			if (pool->hpo_dp_link_enc[i] == NULL)
423 				DC_ERR("DC: failed to create HPO DP link encoder!\n");
424 			pool->hpo_dp_link_enc_count++;
425 		}
426 	}
427 
428 	for (i = 0; i < caps->num_mpc_3dlut; i++) {
429 		pool->mpc_lut[i] = dc_create_3dlut_func();
430 		if (pool->mpc_lut[i] == NULL)
431 			DC_ERR("DC: failed to create MPC 3dlut!\n");
432 		pool->mpc_shaper[i] = dc_create_transfer_func();
433 		if (pool->mpc_shaper[i] == NULL)
434 			DC_ERR("DC: failed to create MPC shaper!\n");
435 	}
436 
437 	dc->caps.dynamic_audio = false;
438 	if (pool->audio_count < pool->stream_enc_count) {
439 		dc->caps.dynamic_audio = true;
440 	}
441 	for (i = 0; i < num_virtual_links; i++) {
442 		pool->stream_enc[pool->stream_enc_count] =
443 			virtual_stream_encoder_create(
444 					ctx, ctx->dc_bios);
445 		if (pool->stream_enc[pool->stream_enc_count] == NULL) {
446 			DC_ERR("DC: failed to create stream_encoder!\n");
447 			return false;
448 		}
449 		pool->stream_enc_count++;
450 	}
451 
452 	dc->hwseq = create_funcs->create_hwseq(ctx);
453 
454 	return true;
455 }
find_matching_clock_source(const struct resource_pool * pool,struct clock_source * clock_source)456 static int find_matching_clock_source(
457 		const struct resource_pool *pool,
458 		struct clock_source *clock_source)
459 {
460 
461 	int i;
462 
463 	for (i = 0; i < pool->clk_src_count; i++) {
464 		if (pool->clock_sources[i] == clock_source)
465 			return i;
466 	}
467 	return -1;
468 }
469 
resource_unreference_clock_source(struct resource_context * res_ctx,const struct resource_pool * pool,struct clock_source * clock_source)470 void resource_unreference_clock_source(
471 		struct resource_context *res_ctx,
472 		const struct resource_pool *pool,
473 		struct clock_source *clock_source)
474 {
475 	int i = find_matching_clock_source(pool, clock_source);
476 
477 	if (i > -1)
478 		res_ctx->clock_source_ref_count[i]--;
479 
480 	if (pool->dp_clock_source == clock_source)
481 		res_ctx->dp_clock_source_ref_count--;
482 }
483 
resource_reference_clock_source(struct resource_context * res_ctx,const struct resource_pool * pool,struct clock_source * clock_source)484 void resource_reference_clock_source(
485 		struct resource_context *res_ctx,
486 		const struct resource_pool *pool,
487 		struct clock_source *clock_source)
488 {
489 	int i = find_matching_clock_source(pool, clock_source);
490 
491 	if (i > -1)
492 		res_ctx->clock_source_ref_count[i]++;
493 
494 	if (pool->dp_clock_source == clock_source)
495 		res_ctx->dp_clock_source_ref_count++;
496 }
497 
resource_get_clock_source_reference(struct resource_context * res_ctx,const struct resource_pool * pool,struct clock_source * clock_source)498 int resource_get_clock_source_reference(
499 		struct resource_context *res_ctx,
500 		const struct resource_pool *pool,
501 		struct clock_source *clock_source)
502 {
503 	int i = find_matching_clock_source(pool, clock_source);
504 
505 	if (i > -1)
506 		return res_ctx->clock_source_ref_count[i];
507 
508 	if (pool->dp_clock_source == clock_source)
509 		return res_ctx->dp_clock_source_ref_count;
510 
511 	return -1;
512 }
513 
resource_are_vblanks_synchronizable(struct dc_stream_state * stream1,struct dc_stream_state * stream2)514 bool resource_are_vblanks_synchronizable(
515 	struct dc_stream_state *stream1,
516 	struct dc_stream_state *stream2)
517 {
518 	uint32_t base60_refresh_rates[] = {10, 20, 5};
519 	uint8_t i;
520 	uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates);
521 	uint64_t frame_time_diff;
522 
523 	if (stream1->ctx->dc->config.vblank_alignment_dto_params &&
524 		stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0 &&
525 		dc_is_dp_signal(stream1->signal) &&
526 		dc_is_dp_signal(stream2->signal) &&
527 		false == stream1->has_non_synchronizable_pclk &&
528 		false == stream2->has_non_synchronizable_pclk &&
529 		stream1->timing.flags.VBLANK_SYNCHRONIZABLE &&
530 		stream2->timing.flags.VBLANK_SYNCHRONIZABLE) {
531 		/* disable refresh rates higher than 60Hz for now */
532 		if (stream1->timing.pix_clk_100hz*100/stream1->timing.h_total/
533 				stream1->timing.v_total > 60)
534 			return false;
535 		if (stream2->timing.pix_clk_100hz*100/stream2->timing.h_total/
536 				stream2->timing.v_total > 60)
537 			return false;
538 		frame_time_diff = (uint64_t)10000 *
539 			stream1->timing.h_total *
540 			stream1->timing.v_total *
541 			stream2->timing.pix_clk_100hz;
542 		frame_time_diff = div_u64(frame_time_diff, stream1->timing.pix_clk_100hz);
543 		frame_time_diff = div_u64(frame_time_diff, stream2->timing.h_total);
544 		frame_time_diff = div_u64(frame_time_diff, stream2->timing.v_total);
545 		for (i = 0; i < rr_count; i++) {
546 			int64_t diff = (int64_t)div_u64(frame_time_diff * base60_refresh_rates[i], 10) - 10000;
547 
548 			if (diff < 0)
549 				diff = -diff;
550 			if (diff < stream1->ctx->dc->config.vblank_alignment_max_frame_time_diff)
551 				return true;
552 		}
553 	}
554 	return false;
555 }
556 
resource_are_streams_timing_synchronizable(struct dc_stream_state * stream1,struct dc_stream_state * stream2)557 bool resource_are_streams_timing_synchronizable(
558 	struct dc_stream_state *stream1,
559 	struct dc_stream_state *stream2)
560 {
561 	if (stream1->timing.h_total != stream2->timing.h_total)
562 		return false;
563 
564 	if (stream1->timing.v_total != stream2->timing.v_total)
565 		return false;
566 
567 	if (stream1->timing.h_addressable
568 				!= stream2->timing.h_addressable)
569 		return false;
570 
571 	if (stream1->timing.v_addressable
572 				!= stream2->timing.v_addressable)
573 		return false;
574 
575 	if (stream1->timing.v_front_porch
576 				!= stream2->timing.v_front_porch)
577 		return false;
578 
579 	if (stream1->timing.pix_clk_100hz
580 				!= stream2->timing.pix_clk_100hz)
581 		return false;
582 
583 	if (stream1->clamping.c_depth != stream2->clamping.c_depth)
584 		return false;
585 
586 	if (stream1->phy_pix_clk != stream2->phy_pix_clk
587 			&& (!dc_is_dp_signal(stream1->signal)
588 			|| !dc_is_dp_signal(stream2->signal)))
589 		return false;
590 
591 	if (stream1->view_format != stream2->view_format)
592 		return false;
593 
594 	if (stream1->ignore_msa_timing_param || stream2->ignore_msa_timing_param)
595 		return false;
596 
597 	return true;
598 }
is_dp_and_hdmi_sharable(struct dc_stream_state * stream1,struct dc_stream_state * stream2)599 static bool is_dp_and_hdmi_sharable(
600 		struct dc_stream_state *stream1,
601 		struct dc_stream_state *stream2)
602 {
603 	if (stream1->ctx->dc->caps.disable_dp_clk_share)
604 		return false;
605 
606 	if (stream1->clamping.c_depth != COLOR_DEPTH_888 ||
607 		stream2->clamping.c_depth != COLOR_DEPTH_888)
608 		return false;
609 
610 	return true;
611 
612 }
613 
is_sharable_clk_src(const struct pipe_ctx * pipe_with_clk_src,const struct pipe_ctx * pipe)614 static bool is_sharable_clk_src(
615 	const struct pipe_ctx *pipe_with_clk_src,
616 	const struct pipe_ctx *pipe)
617 {
618 	if (pipe_with_clk_src->clock_source == NULL)
619 		return false;
620 
621 	if (pipe_with_clk_src->stream->signal == SIGNAL_TYPE_VIRTUAL)
622 		return false;
623 
624 	if (dc_is_dp_signal(pipe_with_clk_src->stream->signal) ||
625 		(dc_is_dp_signal(pipe->stream->signal) &&
626 		!is_dp_and_hdmi_sharable(pipe_with_clk_src->stream,
627 				     pipe->stream)))
628 		return false;
629 
630 	if (dc_is_hdmi_signal(pipe_with_clk_src->stream->signal)
631 			&& dc_is_dual_link_signal(pipe->stream->signal))
632 		return false;
633 
634 	if (dc_is_hdmi_signal(pipe->stream->signal)
635 			&& dc_is_dual_link_signal(pipe_with_clk_src->stream->signal))
636 		return false;
637 
638 	if (!resource_are_streams_timing_synchronizable(
639 			pipe_with_clk_src->stream, pipe->stream))
640 		return false;
641 
642 	return true;
643 }
644 
resource_find_used_clk_src_for_sharing(struct resource_context * res_ctx,struct pipe_ctx * pipe_ctx)645 struct clock_source *resource_find_used_clk_src_for_sharing(
646 					struct resource_context *res_ctx,
647 					struct pipe_ctx *pipe_ctx)
648 {
649 	int i;
650 
651 	for (i = 0; i < MAX_PIPES; i++) {
652 		if (is_sharable_clk_src(&res_ctx->pipe_ctx[i], pipe_ctx))
653 			return res_ctx->pipe_ctx[i].clock_source;
654 	}
655 
656 	return NULL;
657 }
658 
convert_pixel_format_to_dalsurface(enum surface_pixel_format surface_pixel_format)659 static enum pixel_format convert_pixel_format_to_dalsurface(
660 		enum surface_pixel_format surface_pixel_format)
661 {
662 	enum pixel_format dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
663 
664 	switch (surface_pixel_format) {
665 	case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
666 		dal_pixel_format = PIXEL_FORMAT_INDEX8;
667 		break;
668 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
669 		dal_pixel_format = PIXEL_FORMAT_RGB565;
670 		break;
671 	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
672 		dal_pixel_format = PIXEL_FORMAT_RGB565;
673 		break;
674 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
675 		dal_pixel_format = PIXEL_FORMAT_ARGB8888;
676 		break;
677 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
678 		dal_pixel_format = PIXEL_FORMAT_ARGB8888;
679 		break;
680 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
681 		dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
682 		break;
683 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
684 		dal_pixel_format = PIXEL_FORMAT_ARGB2101010;
685 		break;
686 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
687 		dal_pixel_format = PIXEL_FORMAT_ARGB2101010_XRBIAS;
688 		break;
689 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
690 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
691 		dal_pixel_format = PIXEL_FORMAT_FP16;
692 		break;
693 	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
694 	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
695 		dal_pixel_format = PIXEL_FORMAT_420BPP8;
696 		break;
697 	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
698 	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
699 		dal_pixel_format = PIXEL_FORMAT_420BPP10;
700 		break;
701 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
702 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
703 	default:
704 		dal_pixel_format = PIXEL_FORMAT_UNKNOWN;
705 		break;
706 	}
707 	return dal_pixel_format;
708 }
709 
get_vp_scan_direction(enum dc_rotation_angle rotation,bool horizontal_mirror,bool * orthogonal_rotation,bool * flip_vert_scan_dir,bool * flip_horz_scan_dir)710 static inline void get_vp_scan_direction(
711 	enum dc_rotation_angle rotation,
712 	bool horizontal_mirror,
713 	bool *orthogonal_rotation,
714 	bool *flip_vert_scan_dir,
715 	bool *flip_horz_scan_dir)
716 {
717 	*orthogonal_rotation = false;
718 	*flip_vert_scan_dir = false;
719 	*flip_horz_scan_dir = false;
720 	if (rotation == ROTATION_ANGLE_180) {
721 		*flip_vert_scan_dir = true;
722 		*flip_horz_scan_dir = true;
723 	} else if (rotation == ROTATION_ANGLE_90) {
724 		*orthogonal_rotation = true;
725 		*flip_horz_scan_dir = true;
726 	} else if (rotation == ROTATION_ANGLE_270) {
727 		*orthogonal_rotation = true;
728 		*flip_vert_scan_dir = true;
729 	}
730 
731 	if (horizontal_mirror)
732 		*flip_horz_scan_dir = !*flip_horz_scan_dir;
733 }
734 
resource_get_num_mpc_splits(const struct pipe_ctx * pipe)735 int resource_get_num_mpc_splits(const struct pipe_ctx *pipe)
736 {
737 	int mpc_split_count = 0;
738 	const struct pipe_ctx *other_pipe = pipe->bottom_pipe;
739 
740 	while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
741 		mpc_split_count++;
742 		other_pipe = other_pipe->bottom_pipe;
743 	}
744 	other_pipe = pipe->top_pipe;
745 	while (other_pipe && other_pipe->plane_state == pipe->plane_state) {
746 		mpc_split_count++;
747 		other_pipe = other_pipe->top_pipe;
748 	}
749 
750 	return mpc_split_count;
751 }
752 
resource_get_num_odm_splits(const struct pipe_ctx * pipe)753 int resource_get_num_odm_splits(const struct pipe_ctx *pipe)
754 {
755 	int odm_split_count = 0;
756 
757 	pipe = resource_get_otg_master(pipe);
758 
759 	while (pipe->next_odm_pipe) {
760 		odm_split_count++;
761 		pipe = pipe->next_odm_pipe;
762 	}
763 	return odm_split_count;
764 }
765 
get_odm_split_index(struct pipe_ctx * pipe_ctx)766 static int get_odm_split_index(struct pipe_ctx *pipe_ctx)
767 {
768 	int index = 0;
769 
770 	pipe_ctx = resource_get_opp_head(pipe_ctx);
771 	if (!pipe_ctx)
772 		return 0;
773 
774 	while (pipe_ctx->prev_odm_pipe) {
775 		index++;
776 		pipe_ctx = pipe_ctx->prev_odm_pipe;
777 	}
778 
779 	return index;
780 }
781 
get_mpc_split_index(struct pipe_ctx * pipe_ctx)782 static int get_mpc_split_index(struct pipe_ctx *pipe_ctx)
783 {
784 	struct pipe_ctx *split_pipe = pipe_ctx->top_pipe;
785 	int index = 0;
786 
787 	while (split_pipe && split_pipe->plane_state == pipe_ctx->plane_state) {
788 		index++;
789 		split_pipe = split_pipe->top_pipe;
790 	}
791 
792 	return index;
793 }
794 
795 /*
796  * This is a preliminary vp size calculation to allow us to check taps support.
797  * The result is completely overridden afterwards.
798  */
calculate_viewport_size(struct pipe_ctx * pipe_ctx)799 static void calculate_viewport_size(struct pipe_ctx *pipe_ctx)
800 {
801 	struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
802 
803 	data->viewport.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz, data->recout.width));
804 	data->viewport.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert, data->recout.height));
805 	data->viewport_c.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz_c, data->recout.width));
806 	data->viewport_c.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert_c, data->recout.height));
807 	if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
808 			pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) {
809 		swap(data->viewport.width, data->viewport.height);
810 		swap(data->viewport_c.width, data->viewport_c.height);
811 	}
812 }
813 
intersect_rec(const struct rect * r0,const struct rect * r1)814 static struct rect intersect_rec(const struct rect *r0, const struct rect *r1)
815 {
816 	struct rect rec;
817 	int r0_x_end = r0->x + r0->width;
818 	int r1_x_end = r1->x + r1->width;
819 	int r0_y_end = r0->y + r0->height;
820 	int r1_y_end = r1->y + r1->height;
821 
822 	rec.x = r0->x > r1->x ? r0->x : r1->x;
823 	rec.width = r0_x_end > r1_x_end ? r1_x_end - rec.x : r0_x_end - rec.x;
824 	rec.y = r0->y > r1->y ? r0->y : r1->y;
825 	rec.height = r0_y_end > r1_y_end ? r1_y_end - rec.y : r0_y_end - rec.y;
826 
827 	/* in case that there is no intersection */
828 	if (rec.width < 0 || rec.height < 0)
829 		memset(&rec, 0, sizeof(rec));
830 
831 	return rec;
832 }
833 
shift_rec(const struct rect * rec_in,int x,int y)834 static struct rect shift_rec(const struct rect *rec_in, int x, int y)
835 {
836 	struct rect rec_out = *rec_in;
837 
838 	rec_out.x += x;
839 	rec_out.y += y;
840 
841 	return rec_out;
842 }
843 
calculate_odm_slice_in_timing_active(struct pipe_ctx * pipe_ctx)844 static struct rect calculate_odm_slice_in_timing_active(struct pipe_ctx *pipe_ctx)
845 {
846 	const struct dc_stream_state *stream = pipe_ctx->stream;
847 	int odm_slice_count = resource_get_num_odm_splits(pipe_ctx) + 1;
848 	int odm_slice_idx = get_odm_split_index(pipe_ctx);
849 	bool is_last_odm_slice = (odm_slice_idx + 1) == odm_slice_count;
850 	int h_active = stream->timing.h_addressable +
851 			stream->timing.h_border_left +
852 			stream->timing.h_border_right;
853 	int odm_slice_width = h_active / odm_slice_count;
854 	struct rect odm_rec;
855 
856 	odm_rec.x = odm_slice_width * odm_slice_idx;
857 	odm_rec.width = is_last_odm_slice ?
858 			/* last slice width is the reminder of h_active */
859 			h_active - odm_slice_width * (odm_slice_count - 1) :
860 			/* odm slice width is the floor of h_active / count */
861 			odm_slice_width;
862 	odm_rec.y = 0;
863 	odm_rec.height = stream->timing.v_addressable +
864 			stream->timing.v_border_bottom +
865 			stream->timing.v_border_top;
866 
867 	return odm_rec;
868 }
869 
calculate_plane_rec_in_timing_active(struct pipe_ctx * pipe_ctx,const struct rect * rec_in)870 static struct rect calculate_plane_rec_in_timing_active(
871 		struct pipe_ctx *pipe_ctx,
872 		const struct rect *rec_in)
873 {
874 	/*
875 	 * The following diagram shows an example where we map a 1920x1200
876 	 * desktop to a 2560x1440 timing with a plane rect in the middle
877 	 * of the screen. To map a plane rect from Stream Source to Timing
878 	 * Active space, we first multiply stream scaling ratios (i.e 2304/1920
879 	 * horizontal and 1440/1200 vertical) to the plane's x and y, then
880 	 * we add stream destination offsets (i.e 128 horizontal, 0 vertical).
881 	 * This will give us a plane rect's position in Timing Active. However
882 	 * we have to remove the fractional. The rule is that we find left/right
883 	 * and top/bottom positions and round the value to the adjacent integer.
884 	 *
885 	 * Stream Source Space
886 	 * ------------
887 	 *        __________________________________________________
888 	 *       |Stream Source (1920 x 1200) ^                     |
889 	 *       |                            y                     |
890 	 *       |         <------- w --------|>                    |
891 	 *       |          __________________V                     |
892 	 *       |<-- x -->|Plane//////////////| ^                  |
893 	 *       |         |(pre scale)////////| |                  |
894 	 *       |         |///////////////////| |                  |
895 	 *       |         |///////////////////| h                  |
896 	 *       |         |///////////////////| |                  |
897 	 *       |         |///////////////////| |                  |
898 	 *       |         |///////////////////| V                  |
899 	 *       |                                                  |
900 	 *       |                                                  |
901 	 *       |__________________________________________________|
902 	 *
903 	 *
904 	 * Timing Active Space
905 	 * ---------------------------------
906 	 *
907 	 *       Timing Active (2560 x 1440)
908 	 *        __________________________________________________
909 	 *       |*****|  Stteam Destination (2304 x 1440)    |*****|
910 	 *       |*****|                                      |*****|
911 	 *       |<128>|                                      |*****|
912 	 *       |*****|     __________________               |*****|
913 	 *       |*****|    |Plane/////////////|              |*****|
914 	 *       |*****|    |(post scale)//////|              |*****|
915 	 *       |*****|    |//////////////////|              |*****|
916 	 *       |*****|    |//////////////////|              |*****|
917 	 *       |*****|    |//////////////////|              |*****|
918 	 *       |*****|    |//////////////////|              |*****|
919 	 *       |*****|                                      |*****|
920 	 *       |*****|                                      |*****|
921 	 *       |*****|                                      |*****|
922 	 *       |*****|______________________________________|*****|
923 	 *
924 	 * So the resulting formulas are shown below:
925 	 *
926 	 * recout_x = 128 + round(plane_x * 2304 / 1920)
927 	 * recout_w = 128 + round((plane_x + plane_w) * 2304 / 1920) - recout_x
928 	 * recout_y = 0 + round(plane_y * 1440 / 1280)
929 	 * recout_h = 0 + round((plane_y + plane_h) * 1440 / 1200) - recout_y
930 	 *
931 	 * NOTE: fixed point division is not error free. To reduce errors
932 	 * introduced by fixed point division, we divide only after
933 	 * multiplication is complete.
934 	 */
935 	const struct dc_stream_state *stream = pipe_ctx->stream;
936 	struct rect rec_out = {0};
937 	struct fixed31_32 temp;
938 
939 	temp = dc_fixpt_from_fraction(rec_in->x * stream->dst.width,
940 			stream->src.width);
941 	rec_out.x = stream->dst.x + dc_fixpt_round(temp);
942 
943 	temp = dc_fixpt_from_fraction(
944 			(rec_in->x + rec_in->width) * stream->dst.width,
945 			stream->src.width);
946 	rec_out.width = stream->dst.x + dc_fixpt_round(temp) - rec_out.x;
947 
948 	temp = dc_fixpt_from_fraction(rec_in->y * stream->dst.height,
949 			stream->src.height);
950 	rec_out.y = stream->dst.y + dc_fixpt_round(temp);
951 
952 	temp = dc_fixpt_from_fraction(
953 			(rec_in->y + rec_in->height) * stream->dst.height,
954 			stream->src.height);
955 	rec_out.height = stream->dst.y + dc_fixpt_round(temp) - rec_out.y;
956 
957 	return rec_out;
958 }
959 
calculate_mpc_slice_in_timing_active(struct pipe_ctx * pipe_ctx,struct rect * plane_clip_rec)960 static struct rect calculate_mpc_slice_in_timing_active(
961 		struct pipe_ctx *pipe_ctx,
962 		struct rect *plane_clip_rec)
963 {
964 	const struct dc_stream_state *stream = pipe_ctx->stream;
965 	int mpc_slice_count = resource_get_num_mpc_splits(pipe_ctx) + 1;
966 	int mpc_slice_idx = get_mpc_split_index(pipe_ctx);
967 	int epimo = mpc_slice_count - plane_clip_rec->width % mpc_slice_count - 1;
968 	struct rect mpc_rec;
969 
970 	mpc_rec.width = plane_clip_rec->width / mpc_slice_count;
971 	mpc_rec.x = plane_clip_rec->x + mpc_rec.width * mpc_slice_idx;
972 	mpc_rec.height = plane_clip_rec->height;
973 	mpc_rec.y = plane_clip_rec->y;
974 	ASSERT(mpc_slice_count == 1 ||
975 			stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE ||
976 			mpc_rec.width % 2 == 0);
977 
978 	/* extra pixels in the division remainder need to go to pipes after
979 	 * the extra pixel index minus one(epimo) defined here as:
980 	 */
981 	if (mpc_slice_idx > epimo) {
982 		mpc_rec.x += mpc_slice_idx - epimo - 1;
983 		mpc_rec.width += 1;
984 	}
985 
986 	if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) {
987 		ASSERT(mpc_rec.height % 2 == 0);
988 		mpc_rec.height /= 2;
989 	}
990 	return mpc_rec;
991 }
992 
adjust_recout_for_visual_confirm(struct rect * recout,struct pipe_ctx * pipe_ctx)993 static void adjust_recout_for_visual_confirm(struct rect *recout,
994 		struct pipe_ctx *pipe_ctx)
995 {
996 	struct dc *dc = pipe_ctx->stream->ctx->dc;
997 	int dpp_offset, base_offset;
998 
999 	if (dc->debug.visual_confirm == VISUAL_CONFIRM_DISABLE || !pipe_ctx->plane_res.dpp)
1000 		return;
1001 
1002 	dpp_offset = pipe_ctx->stream->timing.v_addressable / VISUAL_CONFIRM_DPP_OFFSET_DENO;
1003 	dpp_offset *= pipe_ctx->plane_res.dpp->inst;
1004 
1005 	if ((dc->debug.visual_confirm_rect_height >= VISUAL_CONFIRM_BASE_MIN) &&
1006 			dc->debug.visual_confirm_rect_height <= VISUAL_CONFIRM_BASE_MAX)
1007 		base_offset = dc->debug.visual_confirm_rect_height;
1008 	else
1009 		base_offset = VISUAL_CONFIRM_BASE_DEFAULT;
1010 
1011 	recout->height -= base_offset;
1012 	recout->height -= dpp_offset;
1013 }
1014 
1015 /*
1016  * The function maps a plane clip from Stream Source Space to ODM Slice Space
1017  * and calculates the rec of the overlapping area of MPC slice of the plane
1018  * clip, ODM slice associated with the pipe context and stream destination rec.
1019  */
calculate_recout(struct pipe_ctx * pipe_ctx)1020 static void calculate_recout(struct pipe_ctx *pipe_ctx)
1021 {
1022 	/*
1023 	 * A plane clip represents the desired plane size and position in Stream
1024 	 * Source Space. Stream Source is the destination where all planes are
1025 	 * blended (i.e. positioned, scaled and overlaid). It is a canvas where
1026 	 * all planes associated with the current stream are drawn together.
1027 	 * After Stream Source is completed, we will further scale and
1028 	 * reposition the entire canvas of the stream source to Stream
1029 	 * Destination in Timing Active Space. This could be due to display
1030 	 * overscan adjustment where we will need to rescale and reposition all
1031 	 * the planes so they can fit into a TV with overscan or downscale
1032 	 * upscale features such as GPU scaling or VSR.
1033 	 *
1034 	 * This two step blending is a virtual procedure in software. In
1035 	 * hardware there is no such thing as Stream Source. all planes are
1036 	 * blended once in Timing Active Space. Software virtualizes a Stream
1037 	 * Source space to decouple the math complicity so scaling param
1038 	 * calculation focuses on one step at a time.
1039 	 *
1040 	 * In the following two diagrams, user applied 10% overscan adjustment
1041 	 * so the Stream Source needs to be scaled down a little before mapping
1042 	 * to Timing Active Space. As a result the Plane Clip is also scaled
1043 	 * down by the same ratio, Plane Clip position (i.e. x and y) with
1044 	 * respect to Stream Source is also scaled down. To map it in Timing
1045 	 * Active Space additional x and y offsets from Stream Destination are
1046 	 * added to Plane Clip as well.
1047 	 *
1048 	 * Stream Source Space
1049 	 * ------------
1050 	 *        __________________________________________________
1051 	 *       |Stream Source (3840 x 2160) ^                     |
1052 	 *       |                            y                     |
1053 	 *       |                            |                     |
1054 	 *       |          __________________V                     |
1055 	 *       |<-- x -->|Plane Clip/////////|                    |
1056 	 *       |         |(pre scale)////////|                    |
1057 	 *       |         |///////////////////|                    |
1058 	 *       |         |///////////////////|                    |
1059 	 *       |         |///////////////////|                    |
1060 	 *       |         |///////////////////|                    |
1061 	 *       |         |///////////////////|                    |
1062 	 *       |                                                  |
1063 	 *       |                                                  |
1064 	 *       |__________________________________________________|
1065 	 *
1066 	 *
1067 	 * Timing Active Space (3840 x 2160)
1068 	 * ---------------------------------
1069 	 *
1070 	 *       Timing Active
1071 	 *        __________________________________________________
1072 	 *       | y_____________________________________________   |
1073 	 *       |x |Stream Destination (3456 x 1944)            |  |
1074 	 *       |  |                                            |  |
1075 	 *       |  |        __________________                  |  |
1076 	 *       |  |       |Plane Clip////////|                 |  |
1077 	 *       |  |       |(post scale)//////|                 |  |
1078 	 *       |  |       |//////////////////|                 |  |
1079 	 *       |  |       |//////////////////|                 |  |
1080 	 *       |  |       |//////////////////|                 |  |
1081 	 *       |  |       |//////////////////|                 |  |
1082 	 *       |  |                                            |  |
1083 	 *       |  |                                            |  |
1084 	 *       |  |____________________________________________|  |
1085 	 *       |__________________________________________________|
1086 	 *
1087 	 *
1088 	 * In Timing Active Space a plane clip could be further sliced into
1089 	 * pieces called MPC slices. Each Pipe Context is responsible for
1090 	 * processing only one MPC slice so the plane processing workload can be
1091 	 * distributed to multiple DPP Pipes. MPC slices could be blended
1092 	 * together to a single ODM slice. Each ODM slice is responsible for
1093 	 * processing a portion of Timing Active divided horizontally so the
1094 	 * output pixel processing workload can be distributed to multiple OPP
1095 	 * pipes. All ODM slices are mapped together in ODM block so all MPC
1096 	 * slices belong to different ODM slices could be pieced together to
1097 	 * form a single image in Timing Active. MPC slices must belong to
1098 	 * single ODM slice. If an MPC slice goes across ODM slice boundary, it
1099 	 * needs to be divided into two MPC slices one for each ODM slice.
1100 	 *
1101 	 * In the following diagram the output pixel processing workload is
1102 	 * divided horizontally into two ODM slices one for each OPP blend tree.
1103 	 * OPP0 blend tree is responsible for processing left half of Timing
1104 	 * Active, while OPP2 blend tree is responsible for processing right
1105 	 * half.
1106 	 *
1107 	 * The plane has two MPC slices. However since the right MPC slice goes
1108 	 * across ODM boundary, two DPP pipes are needed one for each OPP blend
1109 	 * tree. (i.e. DPP1 for OPP0 blend tree and DPP2 for OPP2 blend tree).
1110 	 *
1111 	 * Assuming that we have a Pipe Context associated with OPP0 and DPP1
1112 	 * working on processing the plane in the diagram. We want to know the
1113 	 * width and height of the shaded rectangle and its relative position
1114 	 * with respect to the ODM slice0. This is called the recout of the pipe
1115 	 * context.
1116 	 *
1117 	 * Planes can be at arbitrary size and position and there could be an
1118 	 * arbitrary number of MPC and ODM slices. The algorithm needs to take
1119 	 * all scenarios into account.
1120 	 *
1121 	 * Timing Active Space (3840 x 2160)
1122 	 * ---------------------------------
1123 	 *
1124 	 *       Timing Active
1125 	 *        __________________________________________________
1126 	 *       |OPP0(ODM slice0)^        |OPP2(ODM slice1)        |
1127 	 *       |                y        |                        |
1128 	 *       |                |  <- w ->                        |
1129 	 *       |           _____V________|____                    |
1130 	 *       |          |DPP0 ^  |DPP1 |DPP2|                   |
1131 	 *       |<------ x |-----|->|/////|    |                   |
1132 	 *       |          |     |  |/////|    |                   |
1133 	 *       |          |     h  |/////|    |                   |
1134 	 *       |          |     |  |/////|    |                   |
1135 	 *       |          |_____V__|/////|____|                   |
1136 	 *       |                         |                        |
1137 	 *       |                         |                        |
1138 	 *       |                         |                        |
1139 	 *       |_________________________|________________________|
1140 	 *
1141 	 *
1142 	 */
1143 	struct rect plane_clip;
1144 	struct rect mpc_slice_of_plane_clip;
1145 	struct rect odm_slice;
1146 	struct rect overlapping_area;
1147 
1148 	plane_clip = calculate_plane_rec_in_timing_active(pipe_ctx,
1149 			&pipe_ctx->plane_state->clip_rect);
1150 	/* guard plane clip from drawing beyond stream dst here */
1151 	plane_clip = intersect_rec(&plane_clip,
1152 				&pipe_ctx->stream->dst);
1153 	mpc_slice_of_plane_clip = calculate_mpc_slice_in_timing_active(
1154 			pipe_ctx, &plane_clip);
1155 	odm_slice = calculate_odm_slice_in_timing_active(pipe_ctx);
1156 	overlapping_area = intersect_rec(&mpc_slice_of_plane_clip, &odm_slice);
1157 	if (overlapping_area.height > 0 &&
1158 			overlapping_area.width > 0) {
1159 		/* shift the overlapping area so it is with respect to current
1160 		 * ODM slice's position
1161 		 */
1162 		pipe_ctx->plane_res.scl_data.recout = shift_rec(
1163 				&overlapping_area,
1164 				-odm_slice.x, -odm_slice.y);
1165 		adjust_recout_for_visual_confirm(
1166 				&pipe_ctx->plane_res.scl_data.recout,
1167 				pipe_ctx);
1168 	} else {
1169 		/* if there is no overlap, zero recout */
1170 		memset(&pipe_ctx->plane_res.scl_data.recout, 0,
1171 				sizeof(struct rect));
1172 	}
1173 
1174 }
1175 
calculate_scaling_ratios(struct pipe_ctx * pipe_ctx)1176 static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx)
1177 {
1178 	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1179 	const struct dc_stream_state *stream = pipe_ctx->stream;
1180 	struct rect surf_src = plane_state->src_rect;
1181 	const int in_w = stream->src.width;
1182 	const int in_h = stream->src.height;
1183 	const int out_w = stream->dst.width;
1184 	const int out_h = stream->dst.height;
1185 
1186 	/*Swap surf_src height and width since scaling ratios are in recout rotation*/
1187 	if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 ||
1188 			pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270)
1189 		swap(surf_src.height, surf_src.width);
1190 
1191 	pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction(
1192 					surf_src.width,
1193 					plane_state->dst_rect.width);
1194 	pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction(
1195 					surf_src.height,
1196 					plane_state->dst_rect.height);
1197 
1198 	if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
1199 		pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2;
1200 	else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
1201 		pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2;
1202 
1203 	pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64(
1204 		pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h);
1205 	pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64(
1206 		pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w);
1207 
1208 	pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz;
1209 	pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert;
1210 
1211 	if (pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP8
1212 			|| pipe_ctx->plane_res.scl_data.format == PIXEL_FORMAT_420BPP10) {
1213 		pipe_ctx->plane_res.scl_data.ratios.horz_c.value /= 2;
1214 		pipe_ctx->plane_res.scl_data.ratios.vert_c.value /= 2;
1215 	}
1216 	pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_truncate(
1217 			pipe_ctx->plane_res.scl_data.ratios.horz, 19);
1218 	pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate(
1219 			pipe_ctx->plane_res.scl_data.ratios.vert, 19);
1220 	pipe_ctx->plane_res.scl_data.ratios.horz_c = dc_fixpt_truncate(
1221 			pipe_ctx->plane_res.scl_data.ratios.horz_c, 19);
1222 	pipe_ctx->plane_res.scl_data.ratios.vert_c = dc_fixpt_truncate(
1223 			pipe_ctx->plane_res.scl_data.ratios.vert_c, 19);
1224 }
1225 
1226 
1227 /*
1228  * We completely calculate vp offset, size and inits here based entirely on scaling
1229  * ratios and recout for pixel perfect pipe combine.
1230  */
calculate_init_and_vp(bool flip_scan_dir,int recout_offset_within_recout_full,int recout_size,int src_size,int taps,struct fixed31_32 ratio,struct fixed31_32 * init,int * vp_offset,int * vp_size)1231 static void calculate_init_and_vp(
1232 		bool flip_scan_dir,
1233 		int recout_offset_within_recout_full,
1234 		int recout_size,
1235 		int src_size,
1236 		int taps,
1237 		struct fixed31_32 ratio,
1238 		struct fixed31_32 *init,
1239 		int *vp_offset,
1240 		int *vp_size)
1241 {
1242 	struct fixed31_32 temp;
1243 	int int_part;
1244 
1245 	/*
1246 	 * First of the taps starts sampling pixel number <init_int_part> corresponding to recout
1247 	 * pixel 1. Next recout pixel samples int part of <init + scaling ratio> and so on.
1248 	 * All following calculations are based on this logic.
1249 	 *
1250 	 * Init calculated according to formula:
1251 	 * 	init = (scaling_ratio + number_of_taps + 1) / 2
1252 	 * 	init_bot = init + scaling_ratio
1253 	 * 	to get pixel perfect combine add the fraction from calculating vp offset
1254 	 */
1255 	temp = dc_fixpt_mul_int(ratio, recout_offset_within_recout_full);
1256 	*vp_offset = dc_fixpt_floor(temp);
1257 	temp.value &= 0xffffffff;
1258 	*init = dc_fixpt_truncate(dc_fixpt_add(dc_fixpt_div_int(
1259 			dc_fixpt_add_int(ratio, taps + 1), 2), temp), 19);
1260 	/*
1261 	 * If viewport has non 0 offset and there are more taps than covered by init then
1262 	 * we should decrease the offset and increase init so we are never sampling
1263 	 * outside of viewport.
1264 	 */
1265 	int_part = dc_fixpt_floor(*init);
1266 	if (int_part < taps) {
1267 		int_part = taps - int_part;
1268 		if (int_part > *vp_offset)
1269 			int_part = *vp_offset;
1270 		*vp_offset -= int_part;
1271 		*init = dc_fixpt_add_int(*init, int_part);
1272 	}
1273 	/*
1274 	 * If taps are sampling outside of viewport at end of recout and there are more pixels
1275 	 * available in the surface we should increase the viewport size, regardless set vp to
1276 	 * only what is used.
1277 	 */
1278 	temp = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_size - 1));
1279 	*vp_size = dc_fixpt_floor(temp);
1280 	if (*vp_size + *vp_offset > src_size)
1281 		*vp_size = src_size - *vp_offset;
1282 
1283 	/* We did all the math assuming we are scanning same direction as display does,
1284 	 * however mirror/rotation changes how vp scans vs how it is offset. If scan direction
1285 	 * is flipped we simply need to calculate offset from the other side of plane.
1286 	 * Note that outside of viewport all scaling hardware works in recout space.
1287 	 */
1288 	if (flip_scan_dir)
1289 		*vp_offset = src_size - *vp_offset - *vp_size;
1290 }
1291 
calculate_inits_and_viewports(struct pipe_ctx * pipe_ctx)1292 static void calculate_inits_and_viewports(struct pipe_ctx *pipe_ctx)
1293 {
1294 	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1295 	struct scaler_data *data = &pipe_ctx->plane_res.scl_data;
1296 	struct rect src = plane_state->src_rect;
1297 	struct rect recout_dst_in_active_timing;
1298 	struct rect recout_clip_in_active_timing;
1299 	struct rect recout_clip_in_recout_dst;
1300 	struct rect overlap_in_active_timing;
1301 	struct rect odm_slice = calculate_odm_slice_in_timing_active(pipe_ctx);
1302 	int vpc_div = (data->format == PIXEL_FORMAT_420BPP8
1303 				|| data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1;
1304 	bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir;
1305 
1306 	recout_clip_in_active_timing = shift_rec(
1307 			&data->recout, odm_slice.x, odm_slice.y);
1308 	recout_dst_in_active_timing = calculate_plane_rec_in_timing_active(
1309 			pipe_ctx, &plane_state->dst_rect);
1310 	overlap_in_active_timing = intersect_rec(&recout_clip_in_active_timing,
1311 			&recout_dst_in_active_timing);
1312 	if (overlap_in_active_timing.width > 0 &&
1313 			overlap_in_active_timing.height > 0)
1314 		recout_clip_in_recout_dst = shift_rec(&overlap_in_active_timing,
1315 				-recout_dst_in_active_timing.x,
1316 				-recout_dst_in_active_timing.y);
1317 	else
1318 		memset(&recout_clip_in_recout_dst, 0, sizeof(struct rect));
1319 
1320 	/*
1321 	 * Work in recout rotation since that requires less transformations
1322 	 */
1323 	get_vp_scan_direction(
1324 			plane_state->rotation,
1325 			plane_state->horizontal_mirror,
1326 			&orthogonal_rotation,
1327 			&flip_vert_scan_dir,
1328 			&flip_horz_scan_dir);
1329 
1330 	if (orthogonal_rotation) {
1331 		swap(src.width, src.height);
1332 		swap(flip_vert_scan_dir, flip_horz_scan_dir);
1333 	}
1334 
1335 	calculate_init_and_vp(
1336 			flip_horz_scan_dir,
1337 			recout_clip_in_recout_dst.x,
1338 			data->recout.width,
1339 			src.width,
1340 			data->taps.h_taps,
1341 			data->ratios.horz,
1342 			&data->inits.h,
1343 			&data->viewport.x,
1344 			&data->viewport.width);
1345 	calculate_init_and_vp(
1346 			flip_horz_scan_dir,
1347 			recout_clip_in_recout_dst.x,
1348 			data->recout.width,
1349 			src.width / vpc_div,
1350 			data->taps.h_taps_c,
1351 			data->ratios.horz_c,
1352 			&data->inits.h_c,
1353 			&data->viewport_c.x,
1354 			&data->viewport_c.width);
1355 	calculate_init_and_vp(
1356 			flip_vert_scan_dir,
1357 			recout_clip_in_recout_dst.y,
1358 			data->recout.height,
1359 			src.height,
1360 			data->taps.v_taps,
1361 			data->ratios.vert,
1362 			&data->inits.v,
1363 			&data->viewport.y,
1364 			&data->viewport.height);
1365 	calculate_init_and_vp(
1366 			flip_vert_scan_dir,
1367 			recout_clip_in_recout_dst.y,
1368 			data->recout.height,
1369 			src.height / vpc_div,
1370 			data->taps.v_taps_c,
1371 			data->ratios.vert_c,
1372 			&data->inits.v_c,
1373 			&data->viewport_c.y,
1374 			&data->viewport_c.height);
1375 	if (orthogonal_rotation) {
1376 		swap(data->viewport.x, data->viewport.y);
1377 		swap(data->viewport.width, data->viewport.height);
1378 		swap(data->viewport_c.x, data->viewport_c.y);
1379 		swap(data->viewport_c.width, data->viewport_c.height);
1380 	}
1381 	data->viewport.x += src.x;
1382 	data->viewport.y += src.y;
1383 	ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0);
1384 	data->viewport_c.x += src.x / vpc_div;
1385 	data->viewport_c.y += src.y / vpc_div;
1386 }
1387 
resource_build_scaling_params(struct pipe_ctx * pipe_ctx)1388 bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
1389 {
1390 	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1391 	struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
1392 	const struct rect odm_slice_rec = calculate_odm_slice_in_timing_active(pipe_ctx);
1393 	bool res = false;
1394 	DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1395 
1396 	/* Invalid input */
1397 	if (!plane_state->dst_rect.width ||
1398 			!plane_state->dst_rect.height ||
1399 			!plane_state->src_rect.width ||
1400 			!plane_state->src_rect.height) {
1401 		ASSERT(0);
1402 		return false;
1403 	}
1404 
1405 	pipe_ctx->plane_res.scl_data.format = convert_pixel_format_to_dalsurface(
1406 			pipe_ctx->plane_state->format);
1407 
1408 	/* Timing borders are part of vactive that we are also supposed to skip in addition
1409 	 * to any stream dst offset. Since dm logic assumes dst is in addressable
1410 	 * space we need to add the left and top borders to dst offsets temporarily.
1411 	 * TODO: fix in DM, stream dst is supposed to be in vactive
1412 	 */
1413 	pipe_ctx->stream->dst.x += timing->h_border_left;
1414 	pipe_ctx->stream->dst.y += timing->v_border_top;
1415 
1416 	/* Calculate H and V active size */
1417 	pipe_ctx->plane_res.scl_data.h_active = odm_slice_rec.width;
1418 	pipe_ctx->plane_res.scl_data.v_active = odm_slice_rec.height;
1419 
1420 	/* depends on h_active */
1421 	calculate_recout(pipe_ctx);
1422 	/* depends on pixel format */
1423 	calculate_scaling_ratios(pipe_ctx);
1424 	/* depends on scaling ratios and recout, does not calculate offset yet */
1425 	calculate_viewport_size(pipe_ctx);
1426 
1427 	if (!pipe_ctx->stream->ctx->dc->config.enable_windowed_mpo_odm) {
1428 		/* Stopgap for validation of ODM + MPO on one side of screen case */
1429 		if (pipe_ctx->plane_res.scl_data.viewport.height < 1 ||
1430 				pipe_ctx->plane_res.scl_data.viewport.width < 1)
1431 			return false;
1432 	}
1433 
1434 	/*
1435 	 * LB calculations depend on vp size, h/v_active and scaling ratios
1436 	 * Setting line buffer pixel depth to 24bpp yields banding
1437 	 * on certain displays, such as the Sharp 4k. 36bpp is needed
1438 	 * to support SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 and
1439 	 * SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 with actual > 10 bpc
1440 	 * precision on DCN display engines, but apparently not for DCE, as
1441 	 * far as testing on DCE-11.2 and DCE-8 showed. Various DCE parts have
1442 	 * problems: Carrizo with DCE_VERSION_11_0 does not like 36 bpp lb depth,
1443 	 * neither do DCE-8 at 4k resolution, or DCE-11.2 (broken identify pixel
1444 	 * passthrough). Therefore only use 36 bpp on DCN where it is actually needed.
1445 	 */
1446 	if (plane_state->ctx->dce_version > DCE_VERSION_MAX)
1447 		pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_36BPP;
1448 	else
1449 		pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
1450 
1451 	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha;
1452 
1453 	if (pipe_ctx->plane_res.xfm != NULL)
1454 		res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1455 				pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1456 
1457 	if (pipe_ctx->plane_res.dpp != NULL)
1458 		res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1459 				pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality);
1460 
1461 
1462 	if (!res) {
1463 		/* Try 24 bpp linebuffer */
1464 		pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP;
1465 
1466 		if (pipe_ctx->plane_res.xfm != NULL)
1467 			res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps(
1468 					pipe_ctx->plane_res.xfm,
1469 					&pipe_ctx->plane_res.scl_data,
1470 					&plane_state->scaling_quality);
1471 
1472 		if (pipe_ctx->plane_res.dpp != NULL)
1473 			res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps(
1474 					pipe_ctx->plane_res.dpp,
1475 					&pipe_ctx->plane_res.scl_data,
1476 					&plane_state->scaling_quality);
1477 	}
1478 
1479 	/*
1480 	 * Depends on recout, scaling ratios, h_active and taps
1481 	 * May need to re-check lb size after this in some obscure scenario
1482 	 */
1483 	if (res)
1484 		calculate_inits_and_viewports(pipe_ctx);
1485 
1486 	/*
1487 	 * Handle side by side and top bottom 3d recout offsets after vp calculation
1488 	 * since 3d is special and needs to calculate vp as if there is no recout offset
1489 	 * This may break with rotation, good thing we aren't mixing hw rotation and 3d
1490 	 */
1491 	if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) {
1492 		ASSERT(plane_state->rotation == ROTATION_ANGLE_0 ||
1493 			(pipe_ctx->stream->view_format != VIEW_3D_FORMAT_TOP_AND_BOTTOM &&
1494 				pipe_ctx->stream->view_format != VIEW_3D_FORMAT_SIDE_BY_SIDE));
1495 		if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM)
1496 			pipe_ctx->plane_res.scl_data.recout.y += pipe_ctx->plane_res.scl_data.recout.height;
1497 		else if (pipe_ctx->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE)
1498 			pipe_ctx->plane_res.scl_data.recout.x += pipe_ctx->plane_res.scl_data.recout.width;
1499 	}
1500 
1501 	/* Clamp minimum viewport size */
1502 	if (pipe_ctx->plane_res.scl_data.viewport.height < MIN_VIEWPORT_SIZE)
1503 		pipe_ctx->plane_res.scl_data.viewport.height = MIN_VIEWPORT_SIZE;
1504 	if (pipe_ctx->plane_res.scl_data.viewport.width < MIN_VIEWPORT_SIZE)
1505 		pipe_ctx->plane_res.scl_data.viewport.width = MIN_VIEWPORT_SIZE;
1506 
1507 
1508 	DC_LOG_SCALER("%s pipe %d:\nViewport: height:%d width:%d x:%d y:%d  Recout: height:%d width:%d x:%d y:%d  HACTIVE:%d VACTIVE:%d\n"
1509 			"src_rect: height:%d width:%d x:%d y:%d  dst_rect: height:%d width:%d x:%d y:%d  clip_rect: height:%d width:%d x:%d y:%d\n",
1510 			__func__,
1511 			pipe_ctx->pipe_idx,
1512 			pipe_ctx->plane_res.scl_data.viewport.height,
1513 			pipe_ctx->plane_res.scl_data.viewport.width,
1514 			pipe_ctx->plane_res.scl_data.viewport.x,
1515 			pipe_ctx->plane_res.scl_data.viewport.y,
1516 			pipe_ctx->plane_res.scl_data.recout.height,
1517 			pipe_ctx->plane_res.scl_data.recout.width,
1518 			pipe_ctx->plane_res.scl_data.recout.x,
1519 			pipe_ctx->plane_res.scl_data.recout.y,
1520 			pipe_ctx->plane_res.scl_data.h_active,
1521 			pipe_ctx->plane_res.scl_data.v_active,
1522 			plane_state->src_rect.height,
1523 			plane_state->src_rect.width,
1524 			plane_state->src_rect.x,
1525 			plane_state->src_rect.y,
1526 			plane_state->dst_rect.height,
1527 			plane_state->dst_rect.width,
1528 			plane_state->dst_rect.x,
1529 			plane_state->dst_rect.y,
1530 			plane_state->clip_rect.height,
1531 			plane_state->clip_rect.width,
1532 			plane_state->clip_rect.x,
1533 			plane_state->clip_rect.y);
1534 
1535 	pipe_ctx->stream->dst.x -= timing->h_border_left;
1536 	pipe_ctx->stream->dst.y -= timing->v_border_top;
1537 
1538 	return res;
1539 }
1540 
1541 
resource_build_scaling_params_for_context(const struct dc * dc,struct dc_state * context)1542 enum dc_status resource_build_scaling_params_for_context(
1543 	const struct dc  *dc,
1544 	struct dc_state *context)
1545 {
1546 	int i;
1547 
1548 	for (i = 0; i < MAX_PIPES; i++) {
1549 		if (context->res_ctx.pipe_ctx[i].plane_state != NULL &&
1550 				context->res_ctx.pipe_ctx[i].stream != NULL)
1551 			if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i]))
1552 				return DC_FAIL_SCALING;
1553 	}
1554 
1555 	return DC_OK;
1556 }
1557 
resource_find_free_secondary_pipe_legacy(struct resource_context * res_ctx,const struct resource_pool * pool,const struct pipe_ctx * primary_pipe)1558 struct pipe_ctx *resource_find_free_secondary_pipe_legacy(
1559 		struct resource_context *res_ctx,
1560 		const struct resource_pool *pool,
1561 		const struct pipe_ctx *primary_pipe)
1562 {
1563 	int i;
1564 	struct pipe_ctx *secondary_pipe = NULL;
1565 
1566 	/*
1567 	 * We add a preferred pipe mapping to avoid the chance that
1568 	 * MPCCs already in use will need to be reassigned to other trees.
1569 	 * For example, if we went with the strict, assign backwards logic:
1570 	 *
1571 	 * (State 1)
1572 	 * Display A on, no surface, top pipe = 0
1573 	 * Display B on, no surface, top pipe = 1
1574 	 *
1575 	 * (State 2)
1576 	 * Display A on, no surface, top pipe = 0
1577 	 * Display B on, surface enable, top pipe = 1, bottom pipe = 5
1578 	 *
1579 	 * (State 3)
1580 	 * Display A on, surface enable, top pipe = 0, bottom pipe = 5
1581 	 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1582 	 *
1583 	 * The state 2->3 transition requires remapping MPCC 5 from display B
1584 	 * to display A.
1585 	 *
1586 	 * However, with the preferred pipe logic, state 2 would look like:
1587 	 *
1588 	 * (State 2)
1589 	 * Display A on, no surface, top pipe = 0
1590 	 * Display B on, surface enable, top pipe = 1, bottom pipe = 4
1591 	 *
1592 	 * This would then cause 2->3 to not require remapping any MPCCs.
1593 	 */
1594 	if (primary_pipe) {
1595 		int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
1596 		if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1597 			secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1598 			secondary_pipe->pipe_idx = preferred_pipe_idx;
1599 		}
1600 	}
1601 
1602 	/*
1603 	 * search backwards for the second pipe to keep pipe
1604 	 * assignment more consistent
1605 	 */
1606 	if (!secondary_pipe)
1607 		for (i = pool->pipe_count - 1; i >= 0; i--) {
1608 			if (res_ctx->pipe_ctx[i].stream == NULL) {
1609 				secondary_pipe = &res_ctx->pipe_ctx[i];
1610 				secondary_pipe->pipe_idx = i;
1611 				break;
1612 			}
1613 		}
1614 
1615 	return secondary_pipe;
1616 }
1617 
resource_find_free_pipe_used_in_cur_mpc_blending_tree(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct pipe_ctx * cur_opp_head)1618 int resource_find_free_pipe_used_in_cur_mpc_blending_tree(
1619 		const struct resource_context *cur_res_ctx,
1620 		struct resource_context *new_res_ctx,
1621 		const struct pipe_ctx *cur_opp_head)
1622 {
1623 	const struct pipe_ctx *cur_sec_dpp = cur_opp_head->bottom_pipe;
1624 	struct pipe_ctx *new_pipe;
1625 	int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1626 
1627 	while (cur_sec_dpp) {
1628 		/* find a free pipe used in current opp blend tree,
1629 		 * this is to avoid MPO pipe switching to different opp blending
1630 		 * tree
1631 		 */
1632 		new_pipe = &new_res_ctx->pipe_ctx[cur_sec_dpp->pipe_idx];
1633 		if (resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1634 			free_pipe_idx = cur_sec_dpp->pipe_idx;
1635 			break;
1636 		}
1637 		cur_sec_dpp = cur_sec_dpp->bottom_pipe;
1638 	}
1639 
1640 	return free_pipe_idx;
1641 }
1642 
recource_find_free_pipe_not_used_in_cur_res_ctx(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool)1643 int recource_find_free_pipe_not_used_in_cur_res_ctx(
1644 		const struct resource_context *cur_res_ctx,
1645 		struct resource_context *new_res_ctx,
1646 		const struct resource_pool *pool)
1647 {
1648 	int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1649 	const struct pipe_ctx *new_pipe, *cur_pipe;
1650 	int i;
1651 
1652 	for (i = 0; i < pool->pipe_count; i++) {
1653 		cur_pipe = &cur_res_ctx->pipe_ctx[i];
1654 		new_pipe = &new_res_ctx->pipe_ctx[i];
1655 
1656 		if (resource_is_pipe_type(cur_pipe, FREE_PIPE) &&
1657 				resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1658 			free_pipe_idx = i;
1659 			break;
1660 		}
1661 	}
1662 
1663 	return free_pipe_idx;
1664 }
1665 
resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine(const struct resource_context * cur_res_ctx,struct resource_context * new_res_ctx,const struct resource_pool * pool)1666 int resource_find_free_pipe_used_as_cur_sec_dpp_in_mpcc_combine(
1667 		const struct resource_context *cur_res_ctx,
1668 		struct resource_context *new_res_ctx,
1669 		const struct resource_pool *pool)
1670 {
1671 	int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1672 	const struct pipe_ctx *new_pipe, *cur_pipe;
1673 	int i;
1674 
1675 	for (i = 0; i < pool->pipe_count; i++) {
1676 		cur_pipe = &cur_res_ctx->pipe_ctx[i];
1677 		new_pipe = &new_res_ctx->pipe_ctx[i];
1678 
1679 		if (resource_is_pipe_type(cur_pipe, DPP_PIPE) &&
1680 				!resource_is_pipe_type(cur_pipe, OPP_HEAD) &&
1681 				resource_is_for_mpcc_combine(cur_pipe) &&
1682 				resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1683 			free_pipe_idx = i;
1684 			break;
1685 		}
1686 	}
1687 
1688 	return free_pipe_idx;
1689 }
1690 
resource_find_any_free_pipe(struct resource_context * new_res_ctx,const struct resource_pool * pool)1691 int resource_find_any_free_pipe(struct resource_context *new_res_ctx,
1692 		const struct resource_pool *pool)
1693 {
1694 	int free_pipe_idx = FREE_PIPE_INDEX_NOT_FOUND;
1695 	const struct pipe_ctx *new_pipe;
1696 	int i;
1697 
1698 	for (i = 0; i < pool->pipe_count; i++) {
1699 		new_pipe = &new_res_ctx->pipe_ctx[i];
1700 
1701 		if (resource_is_pipe_type(new_pipe, FREE_PIPE)) {
1702 			free_pipe_idx = i;
1703 			break;
1704 		}
1705 	}
1706 
1707 	return free_pipe_idx;
1708 }
1709 
resource_is_pipe_type(const struct pipe_ctx * pipe_ctx,enum pipe_type type)1710 bool resource_is_pipe_type(const struct pipe_ctx *pipe_ctx, enum pipe_type type)
1711 {
1712 #ifdef DBG
1713 	if (pipe_ctx->stream == NULL) {
1714 		/* a free pipe with dangling states */
1715 		ASSERT(!pipe_ctx->plane_state);
1716 		ASSERT(!pipe_ctx->prev_odm_pipe);
1717 		ASSERT(!pipe_ctx->next_odm_pipe);
1718 		ASSERT(!pipe_ctx->top_pipe);
1719 		ASSERT(!pipe_ctx->bottom_pipe);
1720 	} else if (pipe_ctx->top_pipe) {
1721 		/* a secondary DPP pipe must be signed to a plane */
1722 		ASSERT(pipe_ctx->plane_state)
1723 	}
1724 	/* Add more checks here to prevent corrupted pipe ctx. It is very hard
1725 	 * to debug this issue afterwards because we can't pinpoint the code
1726 	 * location causing inconsistent pipe context states.
1727 	 */
1728 #endif
1729 	switch (type) {
1730 	case OTG_MASTER:
1731 		return !pipe_ctx->prev_odm_pipe &&
1732 				!pipe_ctx->top_pipe &&
1733 				pipe_ctx->stream;
1734 	case OPP_HEAD:
1735 		return !pipe_ctx->top_pipe && pipe_ctx->stream;
1736 	case DPP_PIPE:
1737 		return pipe_ctx->plane_state && pipe_ctx->stream;
1738 	case FREE_PIPE:
1739 		return !pipe_ctx->plane_state && !pipe_ctx->stream;
1740 	default:
1741 		return false;
1742 	}
1743 }
1744 
resource_is_for_mpcc_combine(const struct pipe_ctx * pipe_ctx)1745 bool resource_is_for_mpcc_combine(const struct pipe_ctx *pipe_ctx)
1746 {
1747 	return resource_get_num_mpc_splits(pipe_ctx) > 0;
1748 }
1749 
resource_get_otg_master_for_stream(struct resource_context * res_ctx,struct dc_stream_state * stream)1750 struct pipe_ctx *resource_get_otg_master_for_stream(
1751 		struct resource_context *res_ctx,
1752 		struct dc_stream_state *stream)
1753 {
1754 	int i;
1755 
1756 	for (i = 0; i < MAX_PIPES; i++) {
1757 		if (res_ctx->pipe_ctx[i].stream == stream &&
1758 				resource_is_pipe_type(&res_ctx->pipe_ctx[i], OTG_MASTER))
1759 			return &res_ctx->pipe_ctx[i];
1760 	}
1761 	return NULL;
1762 }
1763 
resource_get_otg_master(const struct pipe_ctx * pipe_ctx)1764 struct pipe_ctx *resource_get_otg_master(const struct pipe_ctx *pipe_ctx)
1765 {
1766 	struct pipe_ctx *otg_master = resource_get_opp_head(pipe_ctx);
1767 
1768 	while (otg_master->prev_odm_pipe)
1769 		otg_master = otg_master->prev_odm_pipe;
1770 	return otg_master;
1771 }
1772 
resource_get_opp_head(const struct pipe_ctx * pipe_ctx)1773 struct pipe_ctx *resource_get_opp_head(const struct pipe_ctx *pipe_ctx)
1774 {
1775 	struct pipe_ctx *opp_head = (struct pipe_ctx *) pipe_ctx;
1776 
1777 	ASSERT(!resource_is_pipe_type(opp_head, FREE_PIPE));
1778 	while (opp_head->top_pipe)
1779 		opp_head = opp_head->top_pipe;
1780 	return opp_head;
1781 }
1782 
get_tail_pipe(struct pipe_ctx * head_pipe)1783 static struct pipe_ctx *get_tail_pipe(
1784 		struct pipe_ctx *head_pipe)
1785 {
1786 	struct pipe_ctx *tail_pipe = head_pipe->bottom_pipe;
1787 
1788 	while (tail_pipe) {
1789 		head_pipe = tail_pipe;
1790 		tail_pipe = tail_pipe->bottom_pipe;
1791 	}
1792 
1793 	return head_pipe;
1794 }
1795 
acquire_first_split_pipe(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)1796 static int acquire_first_split_pipe(
1797 		struct resource_context *res_ctx,
1798 		const struct resource_pool *pool,
1799 		struct dc_stream_state *stream)
1800 {
1801 	int i;
1802 
1803 	for (i = 0; i < pool->pipe_count; i++) {
1804 		struct pipe_ctx *split_pipe = &res_ctx->pipe_ctx[i];
1805 
1806 		if (split_pipe->top_pipe &&
1807 				split_pipe->top_pipe->plane_state == split_pipe->plane_state) {
1808 			split_pipe->top_pipe->bottom_pipe = split_pipe->bottom_pipe;
1809 			if (split_pipe->bottom_pipe)
1810 				split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe;
1811 
1812 			if (split_pipe->top_pipe->plane_state)
1813 				resource_build_scaling_params(split_pipe->top_pipe);
1814 
1815 			memset(split_pipe, 0, sizeof(*split_pipe));
1816 			split_pipe->stream_res.tg = pool->timing_generators[i];
1817 			split_pipe->plane_res.hubp = pool->hubps[i];
1818 			split_pipe->plane_res.ipp = pool->ipps[i];
1819 			split_pipe->plane_res.dpp = pool->dpps[i];
1820 			split_pipe->stream_res.opp = pool->opps[i];
1821 			split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
1822 			split_pipe->pipe_idx = i;
1823 
1824 			split_pipe->stream = stream;
1825 			return i;
1826 		}
1827 	}
1828 	return UNABLE_TO_SPLIT;
1829 }
1830 
add_plane_to_opp_head_pipes(struct pipe_ctx * otg_master_pipe,struct dc_plane_state * plane_state,struct dc_state * context)1831 static bool add_plane_to_opp_head_pipes(struct pipe_ctx *otg_master_pipe,
1832 		struct dc_plane_state *plane_state,
1833 		struct dc_state *context)
1834 {
1835 	struct pipe_ctx *opp_head_pipe = otg_master_pipe;
1836 
1837 	while (opp_head_pipe) {
1838 		if (opp_head_pipe->plane_state) {
1839 			ASSERT(0);
1840 			return false;
1841 		}
1842 		opp_head_pipe->plane_state = plane_state;
1843 		opp_head_pipe = opp_head_pipe->next_odm_pipe;
1844 	}
1845 
1846 	return true;
1847 }
1848 
insert_secondary_dpp_pipe_with_plane(struct pipe_ctx * opp_head_pipe,struct pipe_ctx * sec_pipe,struct dc_plane_state * plane_state)1849 static void insert_secondary_dpp_pipe_with_plane(struct pipe_ctx *opp_head_pipe,
1850 		struct pipe_ctx *sec_pipe, struct dc_plane_state *plane_state)
1851 {
1852 	struct pipe_ctx *tail_pipe = get_tail_pipe(opp_head_pipe);
1853 
1854 	tail_pipe->bottom_pipe = sec_pipe;
1855 	sec_pipe->top_pipe = tail_pipe;
1856 	if (tail_pipe->prev_odm_pipe) {
1857 		ASSERT(tail_pipe->prev_odm_pipe->bottom_pipe);
1858 		sec_pipe->prev_odm_pipe = tail_pipe->prev_odm_pipe->bottom_pipe;
1859 		tail_pipe->prev_odm_pipe->bottom_pipe->next_odm_pipe = sec_pipe;
1860 	}
1861 	sec_pipe->plane_state = plane_state;
1862 }
1863 
1864 /* for each opp head pipe of an otg master pipe, acquire a secondary dpp pipe
1865  * and add the plane. So the plane is added to all MPC blend trees associated
1866  * with the otg master pipe.
1867  */
acquire_secondary_dpp_pipes_and_add_plane(struct pipe_ctx * otg_master_pipe,struct dc_plane_state * plane_state,struct dc_state * new_ctx,struct dc_state * cur_ctx,struct resource_pool * pool)1868 static bool acquire_secondary_dpp_pipes_and_add_plane(
1869 		struct pipe_ctx *otg_master_pipe,
1870 		struct dc_plane_state *plane_state,
1871 		struct dc_state *new_ctx,
1872 		struct dc_state *cur_ctx,
1873 		struct resource_pool *pool)
1874 {
1875 	struct pipe_ctx *opp_head_pipe, *sec_pipe;
1876 
1877 	if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe)
1878 		return false;
1879 
1880 	opp_head_pipe = otg_master_pipe;
1881 	while (opp_head_pipe) {
1882 		sec_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
1883 				cur_ctx,
1884 				new_ctx,
1885 				pool,
1886 				opp_head_pipe);
1887 		if (!sec_pipe) {
1888 			/* try tearing down MPCC combine */
1889 			int pipe_idx = acquire_first_split_pipe(
1890 					&new_ctx->res_ctx, pool,
1891 					otg_master_pipe->stream);
1892 
1893 			if (pipe_idx >= 0)
1894 				sec_pipe = &new_ctx->res_ctx.pipe_ctx[pipe_idx];
1895 		}
1896 
1897 		if (!sec_pipe)
1898 			return false;
1899 
1900 		insert_secondary_dpp_pipe_with_plane(opp_head_pipe, sec_pipe,
1901 				plane_state);
1902 		opp_head_pipe = opp_head_pipe->next_odm_pipe;
1903 	}
1904 	return true;
1905 }
1906 
dc_add_plane_to_context(const struct dc * dc,struct dc_stream_state * stream,struct dc_plane_state * plane_state,struct dc_state * context)1907 bool dc_add_plane_to_context(
1908 		const struct dc *dc,
1909 		struct dc_stream_state *stream,
1910 		struct dc_plane_state *plane_state,
1911 		struct dc_state *context)
1912 {
1913 	struct resource_pool *pool = dc->res_pool;
1914 	struct pipe_ctx *otg_master_pipe;
1915 	struct dc_stream_status *stream_status = NULL;
1916 	bool added = false;
1917 
1918 	stream_status = dc_stream_get_status_from_state(context, stream);
1919 	if (stream_status == NULL) {
1920 		dm_error("Existing stream not found; failed to attach surface!\n");
1921 		goto out;
1922 	} else if (stream_status->plane_count == MAX_SURFACE_NUM) {
1923 		dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
1924 				plane_state, MAX_SURFACE_NUM);
1925 		goto out;
1926 	}
1927 
1928 	otg_master_pipe = resource_get_otg_master_for_stream(
1929 			&context->res_ctx, stream);
1930 	if (otg_master_pipe->plane_state == NULL)
1931 		added = add_plane_to_opp_head_pipes(otg_master_pipe,
1932 				plane_state, context);
1933 	else
1934 		added = acquire_secondary_dpp_pipes_and_add_plane(
1935 				otg_master_pipe, plane_state, context,
1936 				dc->current_state, pool);
1937 	if (added) {
1938 		stream_status->plane_states[stream_status->plane_count] =
1939 				plane_state;
1940 		stream_status->plane_count++;
1941 		dc_plane_state_retain(plane_state);
1942 	}
1943 
1944 out:
1945 	return added;
1946 }
1947 
dc_remove_plane_from_context(const struct dc * dc,struct dc_stream_state * stream,struct dc_plane_state * plane_state,struct dc_state * context)1948 bool dc_remove_plane_from_context(
1949 		const struct dc *dc,
1950 		struct dc_stream_state *stream,
1951 		struct dc_plane_state *plane_state,
1952 		struct dc_state *context)
1953 {
1954 	int i;
1955 	struct dc_stream_status *stream_status = NULL;
1956 	struct resource_pool *pool = dc->res_pool;
1957 
1958 	if (!plane_state)
1959 		return true;
1960 
1961 	for (i = 0; i < context->stream_count; i++)
1962 		if (context->streams[i] == stream) {
1963 			stream_status = &context->stream_status[i];
1964 			break;
1965 		}
1966 
1967 	if (stream_status == NULL) {
1968 		dm_error("Existing stream not found; failed to remove plane.\n");
1969 		return false;
1970 	}
1971 
1972 	/* release pipe for plane*/
1973 	for (i = pool->pipe_count - 1; i >= 0; i--) {
1974 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1975 
1976 		if (pipe_ctx->plane_state == plane_state) {
1977 			if (pipe_ctx->top_pipe)
1978 				pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe;
1979 
1980 			/* Second condition is to avoid setting NULL to top pipe
1981 			 * of tail pipe making it look like head pipe in subsequent
1982 			 * deletes
1983 			 */
1984 			if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe)
1985 				pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe;
1986 
1987 			/*
1988 			 * For head pipe detach surfaces from pipe for tail
1989 			 * pipe just zero it out
1990 			 */
1991 			if (!pipe_ctx->top_pipe)
1992 				pipe_ctx->plane_state = NULL;
1993 			else
1994 				memset(pipe_ctx, 0, sizeof(*pipe_ctx));
1995 		}
1996 	}
1997 
1998 
1999 	for (i = 0; i < stream_status->plane_count; i++) {
2000 		if (stream_status->plane_states[i] == plane_state) {
2001 			dc_plane_state_release(stream_status->plane_states[i]);
2002 			break;
2003 		}
2004 	}
2005 
2006 	if (i == stream_status->plane_count) {
2007 		dm_error("Existing plane_state not found; failed to detach it!\n");
2008 		return false;
2009 	}
2010 
2011 	stream_status->plane_count--;
2012 
2013 	/* Start at the plane we've just released, and move all the planes one index forward to "trim" the array */
2014 	for (; i < stream_status->plane_count; i++)
2015 		stream_status->plane_states[i] = stream_status->plane_states[i + 1];
2016 
2017 	stream_status->plane_states[stream_status->plane_count] = NULL;
2018 
2019 	return true;
2020 }
2021 
2022 /**
2023  * dc_rem_all_planes_for_stream - Remove planes attached to the target stream.
2024  *
2025  * @dc: Current dc state.
2026  * @stream: Target stream, which we want to remove the attached plans.
2027  * @context: New context.
2028  *
2029  * Return:
2030  * Return true if DC was able to remove all planes from the target
2031  * stream, otherwise, return false.
2032  */
dc_rem_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,struct dc_state * context)2033 bool dc_rem_all_planes_for_stream(
2034 		const struct dc *dc,
2035 		struct dc_stream_state *stream,
2036 		struct dc_state *context)
2037 {
2038 	int i, old_plane_count;
2039 	struct dc_stream_status *stream_status = NULL;
2040 	struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 };
2041 
2042 	for (i = 0; i < context->stream_count; i++)
2043 			if (context->streams[i] == stream) {
2044 				stream_status = &context->stream_status[i];
2045 				break;
2046 			}
2047 
2048 	if (stream_status == NULL) {
2049 		dm_error("Existing stream %p not found!\n", stream);
2050 		return false;
2051 	}
2052 
2053 	old_plane_count = stream_status->plane_count;
2054 
2055 	for (i = 0; i < old_plane_count; i++)
2056 		del_planes[i] = stream_status->plane_states[i];
2057 
2058 	for (i = 0; i < old_plane_count; i++)
2059 		if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context))
2060 			return false;
2061 
2062 	return true;
2063 }
2064 
add_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,const struct dc_validation_set set[],int set_count,struct dc_state * context)2065 static bool add_all_planes_for_stream(
2066 		const struct dc *dc,
2067 		struct dc_stream_state *stream,
2068 		const struct dc_validation_set set[],
2069 		int set_count,
2070 		struct dc_state *context)
2071 {
2072 	int i, j;
2073 
2074 	for (i = 0; i < set_count; i++)
2075 		if (set[i].stream == stream)
2076 			break;
2077 
2078 	if (i == set_count) {
2079 		dm_error("Stream %p not found in set!\n", stream);
2080 		return false;
2081 	}
2082 
2083 	for (j = 0; j < set[i].plane_count; j++)
2084 		if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context))
2085 			return false;
2086 
2087 	return true;
2088 }
2089 
dc_add_all_planes_for_stream(const struct dc * dc,struct dc_stream_state * stream,struct dc_plane_state * const * plane_states,int plane_count,struct dc_state * context)2090 bool dc_add_all_planes_for_stream(
2091 		const struct dc *dc,
2092 		struct dc_stream_state *stream,
2093 		struct dc_plane_state * const *plane_states,
2094 		int plane_count,
2095 		struct dc_state *context)
2096 {
2097 	struct dc_validation_set set;
2098 	int i;
2099 
2100 	set.stream = stream;
2101 	set.plane_count = plane_count;
2102 
2103 	for (i = 0; i < plane_count; i++)
2104 		set.plane_states[i] = plane_states[i];
2105 
2106 	return add_all_planes_for_stream(dc, stream, &set, 1, context);
2107 }
2108 
dc_is_timing_changed(struct dc_stream_state * cur_stream,struct dc_stream_state * new_stream)2109 bool dc_is_timing_changed(struct dc_stream_state *cur_stream,
2110 		       struct dc_stream_state *new_stream)
2111 {
2112 	if (cur_stream == NULL)
2113 		return true;
2114 
2115 	/* If output color space is changed, need to reprogram info frames */
2116 	if (cur_stream->output_color_space != new_stream->output_color_space)
2117 		return true;
2118 
2119 	return memcmp(
2120 		&cur_stream->timing,
2121 		&new_stream->timing,
2122 		sizeof(struct dc_crtc_timing)) != 0;
2123 }
2124 
are_stream_backends_same(struct dc_stream_state * stream_a,struct dc_stream_state * stream_b)2125 static bool are_stream_backends_same(
2126 	struct dc_stream_state *stream_a, struct dc_stream_state *stream_b)
2127 {
2128 	if (stream_a == stream_b)
2129 		return true;
2130 
2131 	if (stream_a == NULL || stream_b == NULL)
2132 		return false;
2133 
2134 	if (dc_is_timing_changed(stream_a, stream_b))
2135 		return false;
2136 
2137 	if (stream_a->signal != stream_b->signal)
2138 		return false;
2139 
2140 	if (stream_a->dpms_off != stream_b->dpms_off)
2141 		return false;
2142 
2143 	return true;
2144 }
2145 
2146 /*
2147  * dc_is_stream_unchanged() - Compare two stream states for equivalence.
2148  *
2149  * Checks if there a difference between the two states
2150  * that would require a mode change.
2151  *
2152  * Does not compare cursor position or attributes.
2153  */
dc_is_stream_unchanged(struct dc_stream_state * old_stream,struct dc_stream_state * stream)2154 bool dc_is_stream_unchanged(
2155 	struct dc_stream_state *old_stream, struct dc_stream_state *stream)
2156 {
2157 	if (!old_stream || !stream)
2158 		return false;
2159 
2160 	if (!are_stream_backends_same(old_stream, stream))
2161 		return false;
2162 
2163 	if (old_stream->ignore_msa_timing_param != stream->ignore_msa_timing_param)
2164 		return false;
2165 
2166 	/*compare audio info*/
2167 	if (memcmp(&old_stream->audio_info, &stream->audio_info, sizeof(stream->audio_info)) != 0)
2168 		return false;
2169 
2170 	return true;
2171 }
2172 
2173 /*
2174  * dc_is_stream_scaling_unchanged() - Compare scaling rectangles of two streams.
2175  */
dc_is_stream_scaling_unchanged(struct dc_stream_state * old_stream,struct dc_stream_state * stream)2176 bool dc_is_stream_scaling_unchanged(struct dc_stream_state *old_stream,
2177 				    struct dc_stream_state *stream)
2178 {
2179 	if (old_stream == stream)
2180 		return true;
2181 
2182 	if (old_stream == NULL || stream == NULL)
2183 		return false;
2184 
2185 	if (memcmp(&old_stream->src,
2186 			&stream->src,
2187 			sizeof(struct rect)) != 0)
2188 		return false;
2189 
2190 	if (memcmp(&old_stream->dst,
2191 			&stream->dst,
2192 			sizeof(struct rect)) != 0)
2193 		return false;
2194 
2195 	return true;
2196 }
2197 
update_stream_engine_usage(struct resource_context * res_ctx,const struct resource_pool * pool,struct stream_encoder * stream_enc,bool acquired)2198 static void update_stream_engine_usage(
2199 		struct resource_context *res_ctx,
2200 		const struct resource_pool *pool,
2201 		struct stream_encoder *stream_enc,
2202 		bool acquired)
2203 {
2204 	int i;
2205 
2206 	for (i = 0; i < pool->stream_enc_count; i++) {
2207 		if (pool->stream_enc[i] == stream_enc)
2208 			res_ctx->is_stream_enc_acquired[i] = acquired;
2209 	}
2210 }
2211 
update_hpo_dp_stream_engine_usage(struct resource_context * res_ctx,const struct resource_pool * pool,struct hpo_dp_stream_encoder * hpo_dp_stream_enc,bool acquired)2212 static void update_hpo_dp_stream_engine_usage(
2213 		struct resource_context *res_ctx,
2214 		const struct resource_pool *pool,
2215 		struct hpo_dp_stream_encoder *hpo_dp_stream_enc,
2216 		bool acquired)
2217 {
2218 	int i;
2219 
2220 	for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
2221 		if (pool->hpo_dp_stream_enc[i] == hpo_dp_stream_enc)
2222 			res_ctx->is_hpo_dp_stream_enc_acquired[i] = acquired;
2223 	}
2224 }
2225 
find_acquired_hpo_dp_link_enc_for_link(const struct resource_context * res_ctx,const struct dc_link * link)2226 static inline int find_acquired_hpo_dp_link_enc_for_link(
2227 		const struct resource_context *res_ctx,
2228 		const struct dc_link *link)
2229 {
2230 	int i;
2231 
2232 	for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_to_link_idx); i++)
2233 		if (res_ctx->hpo_dp_link_enc_ref_cnts[i] > 0 &&
2234 				res_ctx->hpo_dp_link_enc_to_link_idx[i] == link->link_index)
2235 			return i;
2236 
2237 	return -1;
2238 }
2239 
find_free_hpo_dp_link_enc(const struct resource_context * res_ctx,const struct resource_pool * pool)2240 static inline int find_free_hpo_dp_link_enc(const struct resource_context *res_ctx,
2241 		const struct resource_pool *pool)
2242 {
2243 	int i;
2244 
2245 	for (i = 0; i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts); i++)
2246 		if (res_ctx->hpo_dp_link_enc_ref_cnts[i] == 0)
2247 			break;
2248 
2249 	return (i < ARRAY_SIZE(res_ctx->hpo_dp_link_enc_ref_cnts) &&
2250 			i < pool->hpo_dp_link_enc_count) ? i : -1;
2251 }
2252 
acquire_hpo_dp_link_enc(struct resource_context * res_ctx,unsigned int link_index,int enc_index)2253 static inline void acquire_hpo_dp_link_enc(
2254 		struct resource_context *res_ctx,
2255 		unsigned int link_index,
2256 		int enc_index)
2257 {
2258 	res_ctx->hpo_dp_link_enc_to_link_idx[enc_index] = link_index;
2259 	res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] = 1;
2260 }
2261 
retain_hpo_dp_link_enc(struct resource_context * res_ctx,int enc_index)2262 static inline void retain_hpo_dp_link_enc(
2263 		struct resource_context *res_ctx,
2264 		int enc_index)
2265 {
2266 	res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]++;
2267 }
2268 
release_hpo_dp_link_enc(struct resource_context * res_ctx,int enc_index)2269 static inline void release_hpo_dp_link_enc(
2270 		struct resource_context *res_ctx,
2271 		int enc_index)
2272 {
2273 	ASSERT(res_ctx->hpo_dp_link_enc_ref_cnts[enc_index] > 0);
2274 	res_ctx->hpo_dp_link_enc_ref_cnts[enc_index]--;
2275 }
2276 
add_hpo_dp_link_enc_to_ctx(struct resource_context * res_ctx,const struct resource_pool * pool,struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream)2277 static bool add_hpo_dp_link_enc_to_ctx(struct resource_context *res_ctx,
2278 		const struct resource_pool *pool,
2279 		struct pipe_ctx *pipe_ctx,
2280 		struct dc_stream_state *stream)
2281 {
2282 	int enc_index;
2283 
2284 	enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
2285 
2286 	if (enc_index >= 0) {
2287 		retain_hpo_dp_link_enc(res_ctx, enc_index);
2288 	} else {
2289 		enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
2290 		if (enc_index >= 0)
2291 			acquire_hpo_dp_link_enc(res_ctx, stream->link->link_index, enc_index);
2292 	}
2293 
2294 	if (enc_index >= 0)
2295 		pipe_ctx->link_res.hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
2296 
2297 	return pipe_ctx->link_res.hpo_dp_link_enc != NULL;
2298 }
2299 
remove_hpo_dp_link_enc_from_ctx(struct resource_context * res_ctx,struct pipe_ctx * pipe_ctx,struct dc_stream_state * stream)2300 static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
2301 		struct pipe_ctx *pipe_ctx,
2302 		struct dc_stream_state *stream)
2303 {
2304 	int enc_index;
2305 
2306 	enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, stream->link);
2307 
2308 	if (enc_index >= 0) {
2309 		release_hpo_dp_link_enc(res_ctx, enc_index);
2310 		pipe_ctx->link_res.hpo_dp_link_enc = NULL;
2311 	}
2312 }
2313 
2314 /* TODO: release audio object */
update_audio_usage(struct resource_context * res_ctx,const struct resource_pool * pool,struct audio * audio,bool acquired)2315 void update_audio_usage(
2316 		struct resource_context *res_ctx,
2317 		const struct resource_pool *pool,
2318 		struct audio *audio,
2319 		bool acquired)
2320 {
2321 	int i;
2322 	for (i = 0; i < pool->audio_count; i++) {
2323 		if (pool->audios[i] == audio)
2324 			res_ctx->is_audio_acquired[i] = acquired;
2325 	}
2326 }
2327 
acquire_first_free_pipe(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)2328 static int acquire_first_free_pipe(
2329 		struct resource_context *res_ctx,
2330 		const struct resource_pool *pool,
2331 		struct dc_stream_state *stream)
2332 {
2333 	int i;
2334 
2335 	for (i = 0; i < pool->pipe_count; i++) {
2336 		if (!res_ctx->pipe_ctx[i].stream) {
2337 			struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i];
2338 
2339 			pipe_ctx->stream_res.tg = pool->timing_generators[i];
2340 			pipe_ctx->plane_res.mi = pool->mis[i];
2341 			pipe_ctx->plane_res.hubp = pool->hubps[i];
2342 			pipe_ctx->plane_res.ipp = pool->ipps[i];
2343 			pipe_ctx->plane_res.xfm = pool->transforms[i];
2344 			pipe_ctx->plane_res.dpp = pool->dpps[i];
2345 			pipe_ctx->stream_res.opp = pool->opps[i];
2346 			if (pool->dpps[i])
2347 				pipe_ctx->plane_res.mpcc_inst = pool->dpps[i]->inst;
2348 			pipe_ctx->pipe_idx = i;
2349 
2350 			if (i >= pool->timing_generator_count) {
2351 				int tg_inst = pool->timing_generator_count - 1;
2352 
2353 				pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
2354 				pipe_ctx->stream_res.opp = pool->opps[tg_inst];
2355 			}
2356 
2357 			pipe_ctx->stream = stream;
2358 			return i;
2359 		}
2360 	}
2361 	return -1;
2362 }
2363 
find_first_free_match_hpo_dp_stream_enc_for_link(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)2364 static struct hpo_dp_stream_encoder *find_first_free_match_hpo_dp_stream_enc_for_link(
2365 		struct resource_context *res_ctx,
2366 		const struct resource_pool *pool,
2367 		struct dc_stream_state *stream)
2368 {
2369 	int i;
2370 
2371 	for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {
2372 		if (!res_ctx->is_hpo_dp_stream_enc_acquired[i] &&
2373 				pool->hpo_dp_stream_enc[i]) {
2374 
2375 			return pool->hpo_dp_stream_enc[i];
2376 		}
2377 	}
2378 
2379 	return NULL;
2380 }
2381 
find_first_free_audio(struct resource_context * res_ctx,const struct resource_pool * pool,enum engine_id id,enum dce_version dc_version)2382 static struct audio *find_first_free_audio(
2383 		struct resource_context *res_ctx,
2384 		const struct resource_pool *pool,
2385 		enum engine_id id,
2386 		enum dce_version dc_version)
2387 {
2388 	int i, available_audio_count;
2389 
2390 	if (id == ENGINE_ID_UNKNOWN)
2391 		return NULL;
2392 
2393 	available_audio_count = pool->audio_count;
2394 
2395 	for (i = 0; i < available_audio_count; i++) {
2396 		if ((res_ctx->is_audio_acquired[i] == false) && (res_ctx->is_stream_enc_acquired[i] == true)) {
2397 			/*we have enough audio endpoint, find the matching inst*/
2398 			if (id != i)
2399 				continue;
2400 			return pool->audios[i];
2401 		}
2402 	}
2403 
2404 	/* use engine id to find free audio */
2405 	if ((id < available_audio_count) && (res_ctx->is_audio_acquired[id] == false)) {
2406 		return pool->audios[id];
2407 	}
2408 	/*not found the matching one, first come first serve*/
2409 	for (i = 0; i < available_audio_count; i++) {
2410 		if (res_ctx->is_audio_acquired[i] == false) {
2411 			return pool->audios[i];
2412 		}
2413 	}
2414 	return NULL;
2415 }
2416 
2417 /*
2418  * dc_add_stream_to_ctx() - Add a new dc_stream_state to a dc_state.
2419  */
dc_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * stream)2420 enum dc_status dc_add_stream_to_ctx(
2421 		struct dc *dc,
2422 		struct dc_state *new_ctx,
2423 		struct dc_stream_state *stream)
2424 {
2425 	enum dc_status res;
2426 	DC_LOGGER_INIT(dc->ctx->logger);
2427 
2428 	if (new_ctx->stream_count >= dc->res_pool->timing_generator_count) {
2429 		DC_LOG_WARNING("Max streams reached, can't add stream %p !\n", stream);
2430 		return DC_ERROR_UNEXPECTED;
2431 	}
2432 
2433 	new_ctx->streams[new_ctx->stream_count] = stream;
2434 	dc_stream_retain(stream);
2435 	new_ctx->stream_count++;
2436 
2437 	res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream);
2438 	if (res != DC_OK)
2439 		DC_LOG_WARNING("Adding stream %p to context failed with err %d!\n", stream, res);
2440 
2441 	return res;
2442 }
2443 
2444 /*
2445  * dc_remove_stream_from_ctx() - Remove a stream from a dc_state.
2446  */
dc_remove_stream_from_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * stream)2447 enum dc_status dc_remove_stream_from_ctx(
2448 			struct dc *dc,
2449 			struct dc_state *new_ctx,
2450 			struct dc_stream_state *stream)
2451 {
2452 	int i;
2453 	struct dc_context *dc_ctx = dc->ctx;
2454 	struct pipe_ctx *del_pipe = resource_get_otg_master_for_stream(&new_ctx->res_ctx, stream);
2455 	struct pipe_ctx *odm_pipe;
2456 
2457 	if (!del_pipe) {
2458 		DC_ERROR("Pipe not found for stream %p !\n", stream);
2459 		return DC_ERROR_UNEXPECTED;
2460 	}
2461 
2462 	odm_pipe = del_pipe->next_odm_pipe;
2463 
2464 	/* Release primary pipe */
2465 	ASSERT(del_pipe->stream_res.stream_enc);
2466 	update_stream_engine_usage(
2467 			&new_ctx->res_ctx,
2468 				dc->res_pool,
2469 			del_pipe->stream_res.stream_enc,
2470 			false);
2471 
2472 	if (dc->link_srv->dp_is_128b_132b_signal(del_pipe)) {
2473 		update_hpo_dp_stream_engine_usage(
2474 			&new_ctx->res_ctx, dc->res_pool,
2475 			del_pipe->stream_res.hpo_dp_stream_enc,
2476 			false);
2477 		remove_hpo_dp_link_enc_from_ctx(&new_ctx->res_ctx, del_pipe, del_pipe->stream);
2478 	}
2479 
2480 	if (del_pipe->stream_res.audio)
2481 		update_audio_usage(
2482 			&new_ctx->res_ctx,
2483 			dc->res_pool,
2484 			del_pipe->stream_res.audio,
2485 			false);
2486 
2487 	resource_unreference_clock_source(&new_ctx->res_ctx,
2488 					  dc->res_pool,
2489 					  del_pipe->clock_source);
2490 
2491 	if (dc->res_pool->funcs->remove_stream_from_ctx)
2492 		dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream);
2493 
2494 	while (odm_pipe) {
2495 		struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2496 
2497 		memset(odm_pipe, 0, sizeof(*odm_pipe));
2498 		odm_pipe = next_odm_pipe;
2499 	}
2500 	memset(del_pipe, 0, sizeof(*del_pipe));
2501 
2502 	for (i = 0; i < new_ctx->stream_count; i++)
2503 		if (new_ctx->streams[i] == stream)
2504 			break;
2505 
2506 	if (new_ctx->streams[i] != stream) {
2507 		DC_ERROR("Context doesn't have stream %p !\n", stream);
2508 		return DC_ERROR_UNEXPECTED;
2509 	}
2510 
2511 	dc_stream_release(new_ctx->streams[i]);
2512 	new_ctx->stream_count--;
2513 
2514 	/* Trim back arrays */
2515 	for (; i < new_ctx->stream_count; i++) {
2516 		new_ctx->streams[i] = new_ctx->streams[i + 1];
2517 		new_ctx->stream_status[i] = new_ctx->stream_status[i + 1];
2518 	}
2519 
2520 	new_ctx->streams[new_ctx->stream_count] = NULL;
2521 	memset(
2522 			&new_ctx->stream_status[new_ctx->stream_count],
2523 			0,
2524 			sizeof(new_ctx->stream_status[0]));
2525 
2526 	return DC_OK;
2527 }
2528 
find_pll_sharable_stream(struct dc_stream_state * stream_needs_pll,struct dc_state * context)2529 static struct dc_stream_state *find_pll_sharable_stream(
2530 		struct dc_stream_state *stream_needs_pll,
2531 		struct dc_state *context)
2532 {
2533 	int i;
2534 
2535 	for (i = 0; i < context->stream_count; i++) {
2536 		struct dc_stream_state *stream_has_pll = context->streams[i];
2537 
2538 		/* We are looking for non dp, non virtual stream */
2539 		if (resource_are_streams_timing_synchronizable(
2540 			stream_needs_pll, stream_has_pll)
2541 			&& !dc_is_dp_signal(stream_has_pll->signal)
2542 			&& stream_has_pll->link->connector_signal
2543 			!= SIGNAL_TYPE_VIRTUAL)
2544 			return stream_has_pll;
2545 
2546 	}
2547 
2548 	return NULL;
2549 }
2550 
get_norm_pix_clk(const struct dc_crtc_timing * timing)2551 static int get_norm_pix_clk(const struct dc_crtc_timing *timing)
2552 {
2553 	uint32_t pix_clk = timing->pix_clk_100hz;
2554 	uint32_t normalized_pix_clk = pix_clk;
2555 
2556 	if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2557 		pix_clk /= 2;
2558 	if (timing->pixel_encoding != PIXEL_ENCODING_YCBCR422) {
2559 		switch (timing->display_color_depth) {
2560 		case COLOR_DEPTH_666:
2561 		case COLOR_DEPTH_888:
2562 			normalized_pix_clk = pix_clk;
2563 			break;
2564 		case COLOR_DEPTH_101010:
2565 			normalized_pix_clk = (pix_clk * 30) / 24;
2566 			break;
2567 		case COLOR_DEPTH_121212:
2568 			normalized_pix_clk = (pix_clk * 36) / 24;
2569 		break;
2570 		case COLOR_DEPTH_161616:
2571 			normalized_pix_clk = (pix_clk * 48) / 24;
2572 		break;
2573 		default:
2574 			ASSERT(0);
2575 		break;
2576 		}
2577 	}
2578 	return normalized_pix_clk;
2579 }
2580 
calculate_phy_pix_clks(struct dc_stream_state * stream)2581 static void calculate_phy_pix_clks(struct dc_stream_state *stream)
2582 {
2583 	/* update actual pixel clock on all streams */
2584 	if (dc_is_hdmi_signal(stream->signal))
2585 		stream->phy_pix_clk = get_norm_pix_clk(
2586 			&stream->timing) / 10;
2587 	else
2588 		stream->phy_pix_clk =
2589 			stream->timing.pix_clk_100hz / 10;
2590 
2591 	if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2592 		stream->phy_pix_clk *= 2;
2593 }
2594 
acquire_resource_from_hw_enabled_state(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)2595 static int acquire_resource_from_hw_enabled_state(
2596 		struct resource_context *res_ctx,
2597 		const struct resource_pool *pool,
2598 		struct dc_stream_state *stream)
2599 {
2600 	struct dc_link *link = stream->link;
2601 	unsigned int i, inst, tg_inst = 0;
2602 	uint32_t numPipes = 1;
2603 	uint32_t id_src[4] = {0};
2604 
2605 	/* Check for enabled DIG to identify enabled display */
2606 	if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
2607 		return -1;
2608 
2609 	inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
2610 
2611 	if (inst == ENGINE_ID_UNKNOWN)
2612 		return -1;
2613 
2614 	for (i = 0; i < pool->stream_enc_count; i++) {
2615 		if (pool->stream_enc[i]->id == inst) {
2616 			tg_inst = pool->stream_enc[i]->funcs->dig_source_otg(
2617 				pool->stream_enc[i]);
2618 			break;
2619 		}
2620 	}
2621 
2622 	// tg_inst not found
2623 	if (i == pool->stream_enc_count)
2624 		return -1;
2625 
2626 	if (tg_inst >= pool->timing_generator_count)
2627 		return -1;
2628 
2629 	if (!res_ctx->pipe_ctx[tg_inst].stream) {
2630 		struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[tg_inst];
2631 
2632 		pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
2633 		id_src[0] = tg_inst;
2634 
2635 		if (pipe_ctx->stream_res.tg->funcs->get_optc_source)
2636 			pipe_ctx->stream_res.tg->funcs->get_optc_source(pipe_ctx->stream_res.tg,
2637 						&numPipes, &id_src[0], &id_src[1]);
2638 
2639 		if (id_src[0] == 0xf && id_src[1] == 0xf) {
2640 			id_src[0] = tg_inst;
2641 			numPipes = 1;
2642 		}
2643 
2644 		for (i = 0; i < numPipes; i++) {
2645 			//Check if src id invalid
2646 			if (id_src[i] == 0xf)
2647 				return -1;
2648 
2649 			pipe_ctx = &res_ctx->pipe_ctx[id_src[i]];
2650 
2651 			pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];
2652 			pipe_ctx->plane_res.mi = pool->mis[id_src[i]];
2653 			pipe_ctx->plane_res.hubp = pool->hubps[id_src[i]];
2654 			pipe_ctx->plane_res.ipp = pool->ipps[id_src[i]];
2655 			pipe_ctx->plane_res.xfm = pool->transforms[id_src[i]];
2656 			pipe_ctx->plane_res.dpp = pool->dpps[id_src[i]];
2657 			pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
2658 
2659 			if (pool->dpps[id_src[i]]) {
2660 				pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst;
2661 
2662 				if (pool->mpc->funcs->read_mpcc_state) {
2663 					struct mpcc_state s = {0};
2664 
2665 					pool->mpc->funcs->read_mpcc_state(pool->mpc, pipe_ctx->plane_res.mpcc_inst, &s);
2666 
2667 					if (s.dpp_id < MAX_MPCC)
2668 						pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].dpp_id =
2669 								s.dpp_id;
2670 
2671 					if (s.bot_mpcc_id < MAX_MPCC)
2672 						pool->mpc->mpcc_array[pipe_ctx->plane_res.mpcc_inst].mpcc_bot =
2673 								&pool->mpc->mpcc_array[s.bot_mpcc_id];
2674 
2675 					if (s.opp_id < MAX_OPP)
2676 						pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
2677 				}
2678 			}
2679 			pipe_ctx->pipe_idx = id_src[i];
2680 
2681 			if (id_src[i] >= pool->timing_generator_count) {
2682 				id_src[i] = pool->timing_generator_count - 1;
2683 
2684 				pipe_ctx->stream_res.tg = pool->timing_generators[id_src[i]];
2685 				pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
2686 			}
2687 
2688 			pipe_ctx->stream = stream;
2689 		}
2690 
2691 		if (numPipes == 2) {
2692 			stream->apply_boot_odm_mode = dm_odm_combine_policy_2to1;
2693 			res_ctx->pipe_ctx[id_src[0]].next_odm_pipe = &res_ctx->pipe_ctx[id_src[1]];
2694 			res_ctx->pipe_ctx[id_src[0]].prev_odm_pipe = NULL;
2695 			res_ctx->pipe_ctx[id_src[1]].next_odm_pipe = NULL;
2696 			res_ctx->pipe_ctx[id_src[1]].prev_odm_pipe = &res_ctx->pipe_ctx[id_src[0]];
2697 		} else
2698 			stream->apply_boot_odm_mode = dm_odm_combine_mode_disabled;
2699 
2700 		return id_src[0];
2701 	}
2702 
2703 	return -1;
2704 }
2705 
mark_seamless_boot_stream(const struct dc * dc,struct dc_stream_state * stream)2706 static void mark_seamless_boot_stream(
2707 		const struct dc  *dc,
2708 		struct dc_stream_state *stream)
2709 {
2710 	struct dc_bios *dcb = dc->ctx->dc_bios;
2711 
2712 	if (dc->config.allow_seamless_boot_optimization &&
2713 			!dcb->funcs->is_accelerated_mode(dcb)) {
2714 		if (dc_validate_boot_timing(dc, stream->sink, &stream->timing))
2715 			stream->apply_seamless_boot_optimization = true;
2716 	}
2717 }
2718 
resource_map_pool_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)2719 enum dc_status resource_map_pool_resources(
2720 		const struct dc  *dc,
2721 		struct dc_state *context,
2722 		struct dc_stream_state *stream)
2723 {
2724 	const struct resource_pool *pool = dc->res_pool;
2725 	int i;
2726 	struct dc_context *dc_ctx = dc->ctx;
2727 	struct pipe_ctx *pipe_ctx = NULL;
2728 	int pipe_idx = -1;
2729 
2730 	calculate_phy_pix_clks(stream);
2731 
2732 	mark_seamless_boot_stream(dc, stream);
2733 
2734 	if (stream->apply_seamless_boot_optimization) {
2735 		pipe_idx = acquire_resource_from_hw_enabled_state(
2736 				&context->res_ctx,
2737 				pool,
2738 				stream);
2739 		if (pipe_idx < 0)
2740 			/* hw resource was assigned to other stream */
2741 			stream->apply_seamless_boot_optimization = false;
2742 	}
2743 
2744 	if (pipe_idx < 0)
2745 		/* acquire new resources */
2746 		pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream);
2747 
2748 	if (pipe_idx < 0)
2749 		pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
2750 
2751 	if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
2752 		return DC_NO_CONTROLLER_RESOURCE;
2753 
2754 	pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2755 
2756 	pipe_ctx->stream_res.stream_enc =
2757 		dc->res_pool->funcs->find_first_free_match_stream_enc_for_link(
2758 			&context->res_ctx, pool, stream);
2759 
2760 	if (!pipe_ctx->stream_res.stream_enc)
2761 		return DC_NO_STREAM_ENC_RESOURCE;
2762 
2763 	update_stream_engine_usage(
2764 		&context->res_ctx, pool,
2765 		pipe_ctx->stream_res.stream_enc,
2766 		true);
2767 
2768 	/* Allocate DP HPO Stream Encoder based on signal, hw capabilities
2769 	 * and link settings
2770 	 */
2771 	if (dc_is_dp_signal(stream->signal)) {
2772 		if (!dc->link_srv->dp_decide_link_settings(stream, &pipe_ctx->link_config.dp_link_settings))
2773 			return DC_FAIL_DP_LINK_BANDWIDTH;
2774 		if (dc->link_srv->dp_get_encoding_format(
2775 				&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {
2776 			pipe_ctx->stream_res.hpo_dp_stream_enc =
2777 					find_first_free_match_hpo_dp_stream_enc_for_link(
2778 							&context->res_ctx, pool, stream);
2779 
2780 			if (!pipe_ctx->stream_res.hpo_dp_stream_enc)
2781 				return DC_NO_STREAM_ENC_RESOURCE;
2782 
2783 			update_hpo_dp_stream_engine_usage(
2784 					&context->res_ctx, pool,
2785 					pipe_ctx->stream_res.hpo_dp_stream_enc,
2786 					true);
2787 			if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, pool, pipe_ctx, stream))
2788 				return DC_NO_LINK_ENC_RESOURCE;
2789 		}
2790 	}
2791 
2792 	/* TODO: Add check if ASIC support and EDID audio */
2793 	if (!stream->converter_disable_audio &&
2794 	    dc_is_audio_capable_signal(pipe_ctx->stream->signal) &&
2795 	    stream->audio_info.mode_count && stream->audio_info.flags.all) {
2796 		pipe_ctx->stream_res.audio = find_first_free_audio(
2797 		&context->res_ctx, pool, pipe_ctx->stream_res.stream_enc->id, dc_ctx->dce_version);
2798 
2799 		/*
2800 		 * Audio assigned in order first come first get.
2801 		 * There are asics which has number of audio
2802 		 * resources less then number of pipes
2803 		 */
2804 		if (pipe_ctx->stream_res.audio)
2805 			update_audio_usage(&context->res_ctx, pool,
2806 					   pipe_ctx->stream_res.audio, true);
2807 	}
2808 
2809 	/* Add ABM to the resource if on EDP */
2810 	if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) {
2811 		if (pool->abm)
2812 			pipe_ctx->stream_res.abm = pool->abm;
2813 		else
2814 			pipe_ctx->stream_res.abm = pool->multiple_abms[pipe_ctx->stream_res.tg->inst];
2815 	}
2816 
2817 	for (i = 0; i < context->stream_count; i++)
2818 		if (context->streams[i] == stream) {
2819 			context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst;
2820 			context->stream_status[i].stream_enc_inst = pipe_ctx->stream_res.stream_enc->stream_enc_inst;
2821 			context->stream_status[i].audio_inst =
2822 				pipe_ctx->stream_res.audio ? pipe_ctx->stream_res.audio->inst : -1;
2823 
2824 			return DC_OK;
2825 		}
2826 
2827 	DC_ERROR("Stream %p not found in new ctx!\n", stream);
2828 	return DC_ERROR_UNEXPECTED;
2829 }
2830 
2831 /**
2832  * dc_resource_state_copy_construct_current() - Creates a new dc_state from existing state
2833  *
2834  * @dc: copy out of dc->current_state
2835  * @dst_ctx: copy into this
2836  *
2837  * This function makes a shallow copy of the current DC state and increments
2838  * refcounts on existing streams and planes.
2839  */
dc_resource_state_copy_construct_current(const struct dc * dc,struct dc_state * dst_ctx)2840 void dc_resource_state_copy_construct_current(
2841 		const struct dc *dc,
2842 		struct dc_state *dst_ctx)
2843 {
2844 	dc_resource_state_copy_construct(dc->current_state, dst_ctx);
2845 }
2846 
2847 
dc_resource_state_construct(const struct dc * dc,struct dc_state * dst_ctx)2848 void dc_resource_state_construct(
2849 		const struct dc *dc,
2850 		struct dc_state *dst_ctx)
2851 {
2852 	dst_ctx->clk_mgr = dc->clk_mgr;
2853 
2854 	/* Initialise DIG link encoder resource tracking variables. */
2855 	link_enc_cfg_init(dc, dst_ctx);
2856 }
2857 
2858 
dc_resource_is_dsc_encoding_supported(const struct dc * dc)2859 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc)
2860 {
2861 	if (dc->res_pool == NULL)
2862 		return false;
2863 
2864 	return dc->res_pool->res_cap->num_dsc > 0;
2865 }
2866 
planes_changed_for_existing_stream(struct dc_state * context,struct dc_stream_state * stream,const struct dc_validation_set set[],int set_count)2867 static bool planes_changed_for_existing_stream(struct dc_state *context,
2868 					       struct dc_stream_state *stream,
2869 					       const struct dc_validation_set set[],
2870 					       int set_count)
2871 {
2872 	int i, j;
2873 	struct dc_stream_status *stream_status = NULL;
2874 
2875 	for (i = 0; i < context->stream_count; i++) {
2876 		if (context->streams[i] == stream) {
2877 			stream_status = &context->stream_status[i];
2878 			break;
2879 		}
2880 	}
2881 
2882 	if (!stream_status) {
2883 		ASSERT(0);
2884 		return false;
2885 	}
2886 
2887 	for (i = 0; i < set_count; i++)
2888 		if (set[i].stream == stream)
2889 			break;
2890 
2891 	if (i == set_count)
2892 		ASSERT(0);
2893 
2894 	if (set[i].plane_count != stream_status->plane_count)
2895 		return true;
2896 
2897 	for (j = 0; j < set[i].plane_count; j++)
2898 		if (set[i].plane_states[j] != stream_status->plane_states[j])
2899 			return true;
2900 
2901 	return false;
2902 }
2903 
2904 /**
2905  * dc_validate_with_context - Validate and update the potential new stream in the context object
2906  *
2907  * @dc: Used to get the current state status
2908  * @set: An array of dc_validation_set with all the current streams reference
2909  * @set_count: Total of streams
2910  * @context: New context
2911  * @fast_validate: Enable or disable fast validation
2912  *
2913  * This function updates the potential new stream in the context object. It
2914  * creates multiple lists for the add, remove, and unchanged streams. In
2915  * particular, if the unchanged streams have a plane that changed, it is
2916  * necessary to remove all planes from the unchanged streams. In summary, this
2917  * function is responsible for validating the new context.
2918  *
2919  * Return:
2920  * In case of success, return DC_OK (1), otherwise, return a DC error.
2921  */
dc_validate_with_context(struct dc * dc,const struct dc_validation_set set[],int set_count,struct dc_state * context,bool fast_validate)2922 enum dc_status dc_validate_with_context(struct dc *dc,
2923 					const struct dc_validation_set set[],
2924 					int set_count,
2925 					struct dc_state *context,
2926 					bool fast_validate)
2927 {
2928 	struct dc_stream_state *unchanged_streams[MAX_PIPES] = { 0 };
2929 	struct dc_stream_state *del_streams[MAX_PIPES] = { 0 };
2930 	struct dc_stream_state *add_streams[MAX_PIPES] = { 0 };
2931 	int old_stream_count = context->stream_count;
2932 	enum dc_status res = DC_ERROR_UNEXPECTED;
2933 	int unchanged_streams_count = 0;
2934 	int del_streams_count = 0;
2935 	int add_streams_count = 0;
2936 	bool found = false;
2937 	int i, j, k;
2938 
2939 	DC_LOGGER_INIT(dc->ctx->logger);
2940 
2941 	/* First build a list of streams to be remove from current context */
2942 	for (i = 0; i < old_stream_count; i++) {
2943 		struct dc_stream_state *stream = context->streams[i];
2944 
2945 		for (j = 0; j < set_count; j++) {
2946 			if (stream == set[j].stream) {
2947 				found = true;
2948 				break;
2949 			}
2950 		}
2951 
2952 		if (!found)
2953 			del_streams[del_streams_count++] = stream;
2954 
2955 		found = false;
2956 	}
2957 
2958 	/* Second, build a list of new streams */
2959 	for (i = 0; i < set_count; i++) {
2960 		struct dc_stream_state *stream = set[i].stream;
2961 
2962 		for (j = 0; j < old_stream_count; j++) {
2963 			if (stream == context->streams[j]) {
2964 				found = true;
2965 				break;
2966 			}
2967 		}
2968 
2969 		if (!found)
2970 			add_streams[add_streams_count++] = stream;
2971 
2972 		found = false;
2973 	}
2974 
2975 	/* Build a list of unchanged streams which is necessary for handling
2976 	 * planes change such as added, removed, and updated.
2977 	 */
2978 	for (i = 0; i < set_count; i++) {
2979 		/* Check if stream is part of the delete list */
2980 		for (j = 0; j < del_streams_count; j++) {
2981 			if (set[i].stream == del_streams[j]) {
2982 				found = true;
2983 				break;
2984 			}
2985 		}
2986 
2987 		if (!found) {
2988 			/* Check if stream is part of the add list */
2989 			for (j = 0; j < add_streams_count; j++) {
2990 				if (set[i].stream == add_streams[j]) {
2991 					found = true;
2992 					break;
2993 				}
2994 			}
2995 		}
2996 
2997 		if (!found)
2998 			unchanged_streams[unchanged_streams_count++] = set[i].stream;
2999 
3000 		found = false;
3001 	}
3002 
3003 	/* Remove all planes for unchanged streams if planes changed */
3004 	for (i = 0; i < unchanged_streams_count; i++) {
3005 		if (planes_changed_for_existing_stream(context,
3006 						       unchanged_streams[i],
3007 						       set,
3008 						       set_count)) {
3009 			if (!dc_rem_all_planes_for_stream(dc,
3010 							  unchanged_streams[i],
3011 							  context)) {
3012 				res = DC_FAIL_DETACH_SURFACES;
3013 				goto fail;
3014 			}
3015 		}
3016 	}
3017 
3018 	/* Remove all planes for removed streams and then remove the streams */
3019 	for (i = 0; i < del_streams_count; i++) {
3020 		/* Need to cpy the dwb data from the old stream in order to efc to work */
3021 		if (del_streams[i]->num_wb_info > 0) {
3022 			for (j = 0; j < add_streams_count; j++) {
3023 				if (del_streams[i]->sink == add_streams[j]->sink) {
3024 					add_streams[j]->num_wb_info = del_streams[i]->num_wb_info;
3025 					for (k = 0; k < del_streams[i]->num_wb_info; k++)
3026 						add_streams[j]->writeback_info[k] = del_streams[i]->writeback_info[k];
3027 				}
3028 			}
3029 		}
3030 
3031 		if (!dc_rem_all_planes_for_stream(dc, del_streams[i], context)) {
3032 			res = DC_FAIL_DETACH_SURFACES;
3033 			goto fail;
3034 		}
3035 
3036 		res = dc_remove_stream_from_ctx(dc, context, del_streams[i]);
3037 		if (res != DC_OK)
3038 			goto fail;
3039 	}
3040 
3041 	/* Swap seamless boot stream to pipe 0 (if needed) to ensure pipe_ctx
3042 	 * matches. This may change in the future if seamless_boot_stream can be
3043 	 * multiple.
3044 	 */
3045 	for (i = 0; i < add_streams_count; i++) {
3046 		mark_seamless_boot_stream(dc, add_streams[i]);
3047 		if (add_streams[i]->apply_seamless_boot_optimization && i != 0) {
3048 			struct dc_stream_state *temp = add_streams[0];
3049 
3050 			add_streams[0] = add_streams[i];
3051 			add_streams[i] = temp;
3052 			break;
3053 		}
3054 	}
3055 
3056 	/* Add new streams and then add all planes for the new stream */
3057 	for (i = 0; i < add_streams_count; i++) {
3058 		calculate_phy_pix_clks(add_streams[i]);
3059 		res = dc_add_stream_to_ctx(dc, context, add_streams[i]);
3060 		if (res != DC_OK)
3061 			goto fail;
3062 
3063 		if (!add_all_planes_for_stream(dc, add_streams[i], set, set_count, context)) {
3064 			res = DC_FAIL_ATTACH_SURFACES;
3065 			goto fail;
3066 		}
3067 	}
3068 
3069 	/* Add all planes for unchanged streams if planes changed */
3070 	for (i = 0; i < unchanged_streams_count; i++) {
3071 		if (planes_changed_for_existing_stream(context,
3072 						       unchanged_streams[i],
3073 						       set,
3074 						       set_count)) {
3075 			if (!add_all_planes_for_stream(dc, unchanged_streams[i], set, set_count, context)) {
3076 				res = DC_FAIL_ATTACH_SURFACES;
3077 				goto fail;
3078 			}
3079 		}
3080 	}
3081 
3082 	res = dc_validate_global_state(dc, context, fast_validate);
3083 
3084 fail:
3085 	if (res != DC_OK)
3086 		DC_LOG_WARNING("%s:resource validation failed, dc_status:%d\n",
3087 			       __func__,
3088 			       res);
3089 
3090 	return res;
3091 }
3092 
3093 /**
3094  * dc_validate_global_state() - Determine if hardware can support a given state
3095  *
3096  * @dc: dc struct for this driver
3097  * @new_ctx: state to be validated
3098  * @fast_validate: set to true if only yes/no to support matters
3099  *
3100  * Checks hardware resource availability and bandwidth requirement.
3101  *
3102  * Return:
3103  * DC_OK if the result can be programmed. Otherwise, an error code.
3104  */
dc_validate_global_state(struct dc * dc,struct dc_state * new_ctx,bool fast_validate)3105 enum dc_status dc_validate_global_state(
3106 		struct dc *dc,
3107 		struct dc_state *new_ctx,
3108 		bool fast_validate)
3109 {
3110 	enum dc_status result = DC_ERROR_UNEXPECTED;
3111 	int i, j;
3112 
3113 	if (!new_ctx)
3114 		return DC_ERROR_UNEXPECTED;
3115 
3116 	if (dc->res_pool->funcs->validate_global) {
3117 		result = dc->res_pool->funcs->validate_global(dc, new_ctx);
3118 		if (result != DC_OK)
3119 			return result;
3120 	}
3121 
3122 	for (i = 0; i < new_ctx->stream_count; i++) {
3123 		struct dc_stream_state *stream = new_ctx->streams[i];
3124 
3125 		for (j = 0; j < dc->res_pool->pipe_count; j++) {
3126 			struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j];
3127 
3128 			if (pipe_ctx->stream != stream)
3129 				continue;
3130 
3131 			if (dc->res_pool->funcs->patch_unknown_plane_state &&
3132 					pipe_ctx->plane_state &&
3133 					pipe_ctx->plane_state->tiling_info.gfx9.swizzle == DC_SW_UNKNOWN) {
3134 				result = dc->res_pool->funcs->patch_unknown_plane_state(pipe_ctx->plane_state);
3135 				if (result != DC_OK)
3136 					return result;
3137 			}
3138 
3139 			/* Switch to dp clock source only if there is
3140 			 * no non dp stream that shares the same timing
3141 			 * with the dp stream.
3142 			 */
3143 			if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
3144 				!find_pll_sharable_stream(stream, new_ctx)) {
3145 
3146 				resource_unreference_clock_source(
3147 						&new_ctx->res_ctx,
3148 						dc->res_pool,
3149 						pipe_ctx->clock_source);
3150 
3151 				pipe_ctx->clock_source = dc->res_pool->dp_clock_source;
3152 				resource_reference_clock_source(
3153 						&new_ctx->res_ctx,
3154 						dc->res_pool,
3155 						 pipe_ctx->clock_source);
3156 			}
3157 		}
3158 	}
3159 
3160 	result = resource_build_scaling_params_for_context(dc, new_ctx);
3161 
3162 	if (result == DC_OK)
3163 		if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate))
3164 			result = DC_FAIL_BANDWIDTH_VALIDATE;
3165 
3166 	/*
3167 	 * Only update link encoder to stream assignment after bandwidth validation passed.
3168 	 * TODO: Split out assignment and validation.
3169 	 */
3170 	if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false)
3171 		dc->res_pool->funcs->link_encs_assign(
3172 			dc, new_ctx, new_ctx->streams, new_ctx->stream_count);
3173 
3174 	return result;
3175 }
3176 
patch_gamut_packet_checksum(struct dc_info_packet * gamut_packet)3177 static void patch_gamut_packet_checksum(
3178 		struct dc_info_packet *gamut_packet)
3179 {
3180 	/* For gamut we recalc checksum */
3181 	if (gamut_packet->valid) {
3182 		uint8_t chk_sum = 0;
3183 		uint8_t *ptr;
3184 		uint8_t i;
3185 
3186 		/*start of the Gamut data. */
3187 		ptr = &gamut_packet->sb[3];
3188 
3189 		for (i = 0; i <= gamut_packet->sb[1]; i++)
3190 			chk_sum += ptr[i];
3191 
3192 		gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
3193 	}
3194 }
3195 
set_avi_info_frame(struct dc_info_packet * info_packet,struct pipe_ctx * pipe_ctx)3196 static void set_avi_info_frame(
3197 		struct dc_info_packet *info_packet,
3198 		struct pipe_ctx *pipe_ctx)
3199 {
3200 	struct dc_stream_state *stream = pipe_ctx->stream;
3201 	enum dc_color_space color_space = COLOR_SPACE_UNKNOWN;
3202 	uint32_t pixel_encoding = 0;
3203 	enum scanning_type scan_type = SCANNING_TYPE_NODATA;
3204 	enum dc_aspect_ratio aspect = ASPECT_RATIO_NO_DATA;
3205 	bool itc = false;
3206 	uint8_t itc_value = 0;
3207 	uint8_t cn0_cn1 = 0;
3208 	unsigned int cn0_cn1_value = 0;
3209 	uint8_t *check_sum = NULL;
3210 	uint8_t byte_index = 0;
3211 	union hdmi_info_packet hdmi_info;
3212 	union display_content_support support = {0};
3213 	unsigned int vic = pipe_ctx->stream->timing.vic;
3214 	unsigned int rid = pipe_ctx->stream->timing.rid;
3215 	unsigned int fr_ind = pipe_ctx->stream->timing.fr_index;
3216 	enum dc_timing_3d_format format;
3217 
3218 	memset(&hdmi_info, 0, sizeof(union hdmi_info_packet));
3219 
3220 	color_space = pipe_ctx->stream->output_color_space;
3221 	if (color_space == COLOR_SPACE_UNKNOWN)
3222 		color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ?
3223 			COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709;
3224 
3225 	/* Initialize header */
3226 	hdmi_info.bits.header.info_frame_type = HDMI_INFOFRAME_TYPE_AVI;
3227 	/* InfoFrameVersion_3 is defined by CEA861F (Section 6.4), but shall
3228 	* not be used in HDMI 2.0 (Section 10.1) */
3229 	hdmi_info.bits.header.version = 2;
3230 	hdmi_info.bits.header.length = HDMI_AVI_INFOFRAME_SIZE;
3231 
3232 	/*
3233 	 * IDO-defined (Y2,Y1,Y0 = 1,1,1) shall not be used by devices built
3234 	 * according to HDMI 2.0 spec (Section 10.1)
3235 	 */
3236 
3237 	switch (stream->timing.pixel_encoding) {
3238 	case PIXEL_ENCODING_YCBCR422:
3239 		pixel_encoding = 1;
3240 		break;
3241 
3242 	case PIXEL_ENCODING_YCBCR444:
3243 		pixel_encoding = 2;
3244 		break;
3245 	case PIXEL_ENCODING_YCBCR420:
3246 		pixel_encoding = 3;
3247 		break;
3248 
3249 	case PIXEL_ENCODING_RGB:
3250 	default:
3251 		pixel_encoding = 0;
3252 	}
3253 
3254 	/* Y0_Y1_Y2 : The pixel encoding */
3255 	/* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
3256 	hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
3257 
3258 	/* A0 = 1 Active Format Information valid */
3259 	hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
3260 
3261 	/* B0, B1 = 3; Bar info data is valid */
3262 	hdmi_info.bits.B0_B1 = BAR_INFO_BOTH_VALID;
3263 
3264 	hdmi_info.bits.SC0_SC1 = PICTURE_SCALING_UNIFORM;
3265 
3266 	/* S0, S1 : Underscan / Overscan */
3267 	/* TODO: un-hardcode scan type */
3268 	scan_type = SCANNING_TYPE_UNDERSCAN;
3269 	hdmi_info.bits.S0_S1 = scan_type;
3270 
3271 	/* C0, C1 : Colorimetry */
3272 	switch (color_space) {
3273 	case COLOR_SPACE_YCBCR709:
3274 	case COLOR_SPACE_YCBCR709_LIMITED:
3275 		hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
3276 		break;
3277 	case COLOR_SPACE_YCBCR601:
3278 	case COLOR_SPACE_YCBCR601_LIMITED:
3279 		hdmi_info.bits.C0_C1 = COLORIMETRY_ITU601;
3280 		break;
3281 	case COLOR_SPACE_2020_RGB_FULLRANGE:
3282 	case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
3283 	case COLOR_SPACE_2020_YCBCR:
3284 		hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_BT2020RGBYCBCR;
3285 		hdmi_info.bits.C0_C1   = COLORIMETRY_EXTENDED;
3286 		break;
3287 	case COLOR_SPACE_ADOBERGB:
3288 		hdmi_info.bits.EC0_EC2 = COLORIMETRYEX_ADOBERGB;
3289 		hdmi_info.bits.C0_C1   = COLORIMETRY_EXTENDED;
3290 		break;
3291 	case COLOR_SPACE_SRGB:
3292 	default:
3293 		hdmi_info.bits.C0_C1 = COLORIMETRY_NO_DATA;
3294 		break;
3295 	}
3296 
3297 	if (pixel_encoding && color_space == COLOR_SPACE_2020_YCBCR &&
3298 			stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
3299 		hdmi_info.bits.EC0_EC2 = 0;
3300 		hdmi_info.bits.C0_C1 = COLORIMETRY_ITU709;
3301 	}
3302 
3303 	/* TODO: un-hardcode aspect ratio */
3304 	aspect = stream->timing.aspect_ratio;
3305 
3306 	switch (aspect) {
3307 	case ASPECT_RATIO_4_3:
3308 	case ASPECT_RATIO_16_9:
3309 		hdmi_info.bits.M0_M1 = aspect;
3310 		break;
3311 
3312 	case ASPECT_RATIO_NO_DATA:
3313 	case ASPECT_RATIO_64_27:
3314 	case ASPECT_RATIO_256_135:
3315 	default:
3316 		hdmi_info.bits.M0_M1 = 0;
3317 	}
3318 
3319 	/* Active Format Aspect ratio - same as Picture Aspect Ratio. */
3320 	hdmi_info.bits.R0_R3 = ACTIVE_FORMAT_ASPECT_RATIO_SAME_AS_PICTURE;
3321 
3322 	/* TODO: un-hardcode cn0_cn1 and itc */
3323 
3324 	cn0_cn1 = 0;
3325 	cn0_cn1_value = 0;
3326 
3327 	itc = true;
3328 	itc_value = 1;
3329 
3330 	support = stream->content_support;
3331 
3332 	if (itc) {
3333 		if (!support.bits.valid_content_type) {
3334 			cn0_cn1_value = 0;
3335 		} else {
3336 			if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GRAPHICS) {
3337 				if (support.bits.graphics_content == 1) {
3338 					cn0_cn1_value = 0;
3339 				}
3340 			} else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_PHOTO) {
3341 				if (support.bits.photo_content == 1) {
3342 					cn0_cn1_value = 1;
3343 				} else {
3344 					cn0_cn1_value = 0;
3345 					itc_value = 0;
3346 				}
3347 			} else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_CINEMA) {
3348 				if (support.bits.cinema_content == 1) {
3349 					cn0_cn1_value = 2;
3350 				} else {
3351 					cn0_cn1_value = 0;
3352 					itc_value = 0;
3353 				}
3354 			} else if (cn0_cn1 == DISPLAY_CONTENT_TYPE_GAME) {
3355 				if (support.bits.game_content == 1) {
3356 					cn0_cn1_value = 3;
3357 				} else {
3358 					cn0_cn1_value = 0;
3359 					itc_value = 0;
3360 				}
3361 			}
3362 		}
3363 		hdmi_info.bits.CN0_CN1 = cn0_cn1_value;
3364 		hdmi_info.bits.ITC = itc_value;
3365 	}
3366 
3367 	if (stream->qs_bit == 1) {
3368 		if (color_space == COLOR_SPACE_SRGB ||
3369 			color_space == COLOR_SPACE_2020_RGB_FULLRANGE)
3370 			hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_FULL_RANGE;
3371 		else if (color_space == COLOR_SPACE_SRGB_LIMITED ||
3372 					color_space == COLOR_SPACE_2020_RGB_LIMITEDRANGE)
3373 			hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_LIMITED_RANGE;
3374 		else
3375 			hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_DEFAULT_RANGE;
3376 	} else
3377 		hdmi_info.bits.Q0_Q1   = RGB_QUANTIZATION_DEFAULT_RANGE;
3378 
3379 	/* TODO : We should handle YCC quantization */
3380 	/* but we do not have matrix calculation */
3381 	hdmi_info.bits.YQ0_YQ1 = YYC_QUANTIZATION_LIMITED_RANGE;
3382 
3383 	///VIC
3384 	if (pipe_ctx->stream->timing.hdmi_vic != 0)
3385 		vic = 0;
3386 	format = stream->timing.timing_3d_format;
3387 	/*todo, add 3DStereo support*/
3388 	if (format != TIMING_3D_FORMAT_NONE) {
3389 		// Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled
3390 		switch (pipe_ctx->stream->timing.hdmi_vic) {
3391 		case 1:
3392 			vic = 95;
3393 			break;
3394 		case 2:
3395 			vic = 94;
3396 			break;
3397 		case 3:
3398 			vic = 93;
3399 			break;
3400 		case 4:
3401 			vic = 98;
3402 			break;
3403 		default:
3404 			break;
3405 		}
3406 	}
3407 	/* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
3408 	hdmi_info.bits.VIC0_VIC7 = vic;
3409 	if (vic >= 128)
3410 		hdmi_info.bits.header.version = 3;
3411 	/* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
3412 	 * the Source shall use 20 AVI InfoFrame Version 4
3413 	 */
3414 	if (hdmi_info.bits.C0_C1 == COLORIMETRY_EXTENDED &&
3415 			hdmi_info.bits.EC0_EC2 == COLORIMETRYEX_RESERVED) {
3416 		hdmi_info.bits.header.version = 4;
3417 		hdmi_info.bits.header.length = 14;
3418 	}
3419 
3420 	if (rid != 0 && fr_ind != 0) {
3421 		hdmi_info.bits.header.version = 5;
3422 		hdmi_info.bits.header.length = 15;
3423 
3424 		hdmi_info.bits.FR0_FR3 = fr_ind & 0xF;
3425 		hdmi_info.bits.FR4 = (fr_ind >> 4) & 0x1;
3426 		hdmi_info.bits.RID0_RID5 = rid;
3427 	}
3428 
3429 	/* pixel repetition
3430 	 * PR0 - PR3 start from 0 whereas pHwPathMode->mode.timing.flags.pixel
3431 	 * repetition start from 1 */
3432 	hdmi_info.bits.PR0_PR3 = 0;
3433 
3434 	/* Bar Info
3435 	 * barTop:    Line Number of End of Top Bar.
3436 	 * barBottom: Line Number of Start of Bottom Bar.
3437 	 * barLeft:   Pixel Number of End of Left Bar.
3438 	 * barRight:  Pixel Number of Start of Right Bar. */
3439 	hdmi_info.bits.bar_top = stream->timing.v_border_top;
3440 	hdmi_info.bits.bar_bottom = (stream->timing.v_total
3441 			- stream->timing.v_border_bottom + 1);
3442 	hdmi_info.bits.bar_left  = stream->timing.h_border_left;
3443 	hdmi_info.bits.bar_right = (stream->timing.h_total
3444 			- stream->timing.h_border_right + 1);
3445 
3446     /* Additional Colorimetry Extension
3447      * Used in conduction with C0-C1 and EC0-EC2
3448      * 0 = DCI-P3 RGB (D65)
3449      * 1 = DCI-P3 RGB (theater)
3450      */
3451 	hdmi_info.bits.ACE0_ACE3 = 0;
3452 
3453 	/* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */
3454 	check_sum = &hdmi_info.packet_raw_data.sb[0];
3455 
3456 	*check_sum = HDMI_INFOFRAME_TYPE_AVI + hdmi_info.bits.header.length + hdmi_info.bits.header.version;
3457 
3458 	for (byte_index = 1; byte_index <= hdmi_info.bits.header.length; byte_index++)
3459 		*check_sum += hdmi_info.packet_raw_data.sb[byte_index];
3460 
3461 	/* one byte complement */
3462 	*check_sum = (uint8_t) (0x100 - *check_sum);
3463 
3464 	/* Store in hw_path_mode */
3465 	info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
3466 	info_packet->hb1 = hdmi_info.packet_raw_data.hb1;
3467 	info_packet->hb2 = hdmi_info.packet_raw_data.hb2;
3468 
3469 	for (byte_index = 0; byte_index < sizeof(hdmi_info.packet_raw_data.sb); byte_index++)
3470 		info_packet->sb[byte_index] = hdmi_info.packet_raw_data.sb[byte_index];
3471 
3472 	info_packet->valid = true;
3473 }
3474 
set_vendor_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)3475 static void set_vendor_info_packet(
3476 		struct dc_info_packet *info_packet,
3477 		struct dc_stream_state *stream)
3478 {
3479 	/* SPD info packet for FreeSync */
3480 
3481 	/* Check if Freesync is supported. Return if false. If true,
3482 	 * set the corresponding bit in the info packet
3483 	 */
3484 	if (!stream->vsp_infopacket.valid)
3485 		return;
3486 
3487 	*info_packet = stream->vsp_infopacket;
3488 }
3489 
set_spd_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)3490 static void set_spd_info_packet(
3491 		struct dc_info_packet *info_packet,
3492 		struct dc_stream_state *stream)
3493 {
3494 	/* SPD info packet for FreeSync */
3495 
3496 	/* Check if Freesync is supported. Return if false. If true,
3497 	 * set the corresponding bit in the info packet
3498 	 */
3499 	if (!stream->vrr_infopacket.valid)
3500 		return;
3501 
3502 	*info_packet = stream->vrr_infopacket;
3503 }
3504 
set_hdr_static_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)3505 static void set_hdr_static_info_packet(
3506 		struct dc_info_packet *info_packet,
3507 		struct dc_stream_state *stream)
3508 {
3509 	/* HDR Static Metadata info packet for HDR10 */
3510 
3511 	if (!stream->hdr_static_metadata.valid ||
3512 			stream->use_dynamic_meta)
3513 		return;
3514 
3515 	*info_packet = stream->hdr_static_metadata;
3516 }
3517 
set_vsc_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)3518 static void set_vsc_info_packet(
3519 		struct dc_info_packet *info_packet,
3520 		struct dc_stream_state *stream)
3521 {
3522 	if (!stream->vsc_infopacket.valid)
3523 		return;
3524 
3525 	*info_packet = stream->vsc_infopacket;
3526 }
set_hfvs_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)3527 static void set_hfvs_info_packet(
3528 		struct dc_info_packet *info_packet,
3529 		struct dc_stream_state *stream)
3530 {
3531 	if (!stream->hfvsif_infopacket.valid)
3532 		return;
3533 
3534 	*info_packet = stream->hfvsif_infopacket;
3535 }
3536 
adaptive_sync_override_dp_info_packets_sdp_line_num(const struct dc_crtc_timing * timing,struct enc_sdp_line_num * sdp_line_num,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dlg_param)3537 static void adaptive_sync_override_dp_info_packets_sdp_line_num(
3538 		const struct dc_crtc_timing *timing,
3539 		struct enc_sdp_line_num *sdp_line_num,
3540 		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param)
3541 {
3542 	uint32_t asic_blank_start = 0;
3543 	uint32_t asic_blank_end   = 0;
3544 	uint32_t v_update = 0;
3545 
3546 	const struct dc_crtc_timing *tg = timing;
3547 
3548 	/* blank_start = frame end - front porch */
3549 	asic_blank_start = tg->v_total - tg->v_front_porch;
3550 
3551 	/* blank_end = blank_start - active */
3552 	asic_blank_end = (asic_blank_start - tg->v_border_bottom -
3553 						tg->v_addressable - tg->v_border_top);
3554 
3555 	if (pipe_dlg_param->vstartup_start > asic_blank_end) {
3556 		v_update = (tg->v_total - (pipe_dlg_param->vstartup_start - asic_blank_end));
3557 		sdp_line_num->adaptive_sync_line_num_valid = true;
3558 		sdp_line_num->adaptive_sync_line_num = (tg->v_total - v_update - 1);
3559 	} else {
3560 		sdp_line_num->adaptive_sync_line_num_valid = false;
3561 		sdp_line_num->adaptive_sync_line_num = 0;
3562 	}
3563 }
3564 
set_adaptive_sync_info_packet(struct dc_info_packet * info_packet,const struct dc_stream_state * stream,struct encoder_info_frame * info_frame,struct _vcs_dpi_display_pipe_dest_params_st * pipe_dlg_param)3565 static void set_adaptive_sync_info_packet(
3566 		struct dc_info_packet *info_packet,
3567 		const struct dc_stream_state *stream,
3568 		struct encoder_info_frame *info_frame,
3569 		struct _vcs_dpi_display_pipe_dest_params_st *pipe_dlg_param)
3570 {
3571 	if (!stream->adaptive_sync_infopacket.valid)
3572 		return;
3573 
3574 	adaptive_sync_override_dp_info_packets_sdp_line_num(
3575 			&stream->timing,
3576 			&info_frame->sdp_line_num,
3577 			pipe_dlg_param);
3578 
3579 	*info_packet = stream->adaptive_sync_infopacket;
3580 }
3581 
set_vtem_info_packet(struct dc_info_packet * info_packet,struct dc_stream_state * stream)3582 static void set_vtem_info_packet(
3583 		struct dc_info_packet *info_packet,
3584 		struct dc_stream_state *stream)
3585 {
3586 	if (!stream->vtem_infopacket.valid)
3587 		return;
3588 
3589 	*info_packet = stream->vtem_infopacket;
3590 }
3591 
dc_resource_state_destruct(struct dc_state * context)3592 void dc_resource_state_destruct(struct dc_state *context)
3593 {
3594 	int i, j;
3595 
3596 	for (i = 0; i < context->stream_count; i++) {
3597 		for (j = 0; j < context->stream_status[i].plane_count; j++)
3598 			dc_plane_state_release(
3599 				context->stream_status[i].plane_states[j]);
3600 
3601 		context->stream_status[i].plane_count = 0;
3602 		dc_stream_release(context->streams[i]);
3603 		context->streams[i] = NULL;
3604 	}
3605 	context->stream_count = 0;
3606 }
3607 
dc_resource_state_copy_construct(const struct dc_state * src_ctx,struct dc_state * dst_ctx)3608 void dc_resource_state_copy_construct(
3609 		const struct dc_state *src_ctx,
3610 		struct dc_state *dst_ctx)
3611 {
3612 	int i, j;
3613 	struct kref refcount = dst_ctx->refcount;
3614 
3615 	*dst_ctx = *src_ctx;
3616 
3617 	for (i = 0; i < MAX_PIPES; i++) {
3618 		struct pipe_ctx *cur_pipe = &dst_ctx->res_ctx.pipe_ctx[i];
3619 
3620 		if (cur_pipe->top_pipe)
3621 			cur_pipe->top_pipe =  &dst_ctx->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx];
3622 
3623 		if (cur_pipe->bottom_pipe)
3624 			cur_pipe->bottom_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->bottom_pipe->pipe_idx];
3625 
3626 		if (cur_pipe->next_odm_pipe)
3627 			cur_pipe->next_odm_pipe =  &dst_ctx->res_ctx.pipe_ctx[cur_pipe->next_odm_pipe->pipe_idx];
3628 
3629 		if (cur_pipe->prev_odm_pipe)
3630 			cur_pipe->prev_odm_pipe = &dst_ctx->res_ctx.pipe_ctx[cur_pipe->prev_odm_pipe->pipe_idx];
3631 	}
3632 
3633 	for (i = 0; i < dst_ctx->stream_count; i++) {
3634 		dc_stream_retain(dst_ctx->streams[i]);
3635 		for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++)
3636 			dc_plane_state_retain(
3637 				dst_ctx->stream_status[i].plane_states[j]);
3638 	}
3639 
3640 	/* context refcount should not be overridden */
3641 	dst_ctx->refcount = refcount;
3642 
3643 }
3644 
dc_resource_find_first_free_pll(struct resource_context * res_ctx,const struct resource_pool * pool)3645 struct clock_source *dc_resource_find_first_free_pll(
3646 		struct resource_context *res_ctx,
3647 		const struct resource_pool *pool)
3648 {
3649 	int i;
3650 
3651 	for (i = 0; i < pool->clk_src_count; ++i) {
3652 		if (res_ctx->clock_source_ref_count[i] == 0)
3653 			return pool->clock_sources[i];
3654 	}
3655 
3656 	return NULL;
3657 }
3658 
resource_build_info_frame(struct pipe_ctx * pipe_ctx)3659 void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
3660 {
3661 	enum signal_type signal = SIGNAL_TYPE_NONE;
3662 	struct encoder_info_frame *info = &pipe_ctx->stream_res.encoder_info_frame;
3663 
3664 	/* default all packets to invalid */
3665 	info->avi.valid = false;
3666 	info->gamut.valid = false;
3667 	info->vendor.valid = false;
3668 	info->spd.valid = false;
3669 	info->hdrsmd.valid = false;
3670 	info->vsc.valid = false;
3671 	info->hfvsif.valid = false;
3672 	info->vtem.valid = false;
3673 	info->adaptive_sync.valid = false;
3674 	signal = pipe_ctx->stream->signal;
3675 
3676 	/* HDMi and DP have different info packets*/
3677 	if (dc_is_hdmi_signal(signal)) {
3678 		set_avi_info_frame(&info->avi, pipe_ctx);
3679 
3680 		set_vendor_info_packet(&info->vendor, pipe_ctx->stream);
3681 		set_hfvs_info_packet(&info->hfvsif, pipe_ctx->stream);
3682 		set_vtem_info_packet(&info->vtem, pipe_ctx->stream);
3683 
3684 		set_spd_info_packet(&info->spd, pipe_ctx->stream);
3685 
3686 		set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
3687 
3688 	} else if (dc_is_dp_signal(signal)) {
3689 		set_vsc_info_packet(&info->vsc, pipe_ctx->stream);
3690 
3691 		set_spd_info_packet(&info->spd, pipe_ctx->stream);
3692 
3693 		set_hdr_static_info_packet(&info->hdrsmd, pipe_ctx->stream);
3694 		set_adaptive_sync_info_packet(&info->adaptive_sync,
3695 										pipe_ctx->stream,
3696 										info,
3697 										&pipe_ctx->pipe_dlg_param);
3698 	}
3699 
3700 	patch_gamut_packet_checksum(&info->gamut);
3701 }
3702 
resource_map_clock_resources(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)3703 enum dc_status resource_map_clock_resources(
3704 		const struct dc  *dc,
3705 		struct dc_state *context,
3706 		struct dc_stream_state *stream)
3707 {
3708 	/* acquire new resources */
3709 	const struct resource_pool *pool = dc->res_pool;
3710 	struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(
3711 				&context->res_ctx, stream);
3712 
3713 	if (!pipe_ctx)
3714 		return DC_ERROR_UNEXPECTED;
3715 
3716 	if (dc_is_dp_signal(pipe_ctx->stream->signal)
3717 		|| pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
3718 		pipe_ctx->clock_source = pool->dp_clock_source;
3719 	else {
3720 		pipe_ctx->clock_source = NULL;
3721 
3722 		if (!dc->config.disable_disp_pll_sharing)
3723 			pipe_ctx->clock_source = resource_find_used_clk_src_for_sharing(
3724 				&context->res_ctx,
3725 				pipe_ctx);
3726 
3727 		if (pipe_ctx->clock_source == NULL)
3728 			pipe_ctx->clock_source =
3729 				dc_resource_find_first_free_pll(
3730 					&context->res_ctx,
3731 					pool);
3732 	}
3733 
3734 	if (pipe_ctx->clock_source == NULL)
3735 		return DC_NO_CLOCK_SOURCE_RESOURCE;
3736 
3737 	resource_reference_clock_source(
3738 		&context->res_ctx, pool,
3739 		pipe_ctx->clock_source);
3740 
3741 	return DC_OK;
3742 }
3743 
3744 /*
3745  * Note: We need to disable output if clock sources change,
3746  * since bios does optimization and doesn't apply if changing
3747  * PHY when not already disabled.
3748  */
pipe_need_reprogram(struct pipe_ctx * pipe_ctx_old,struct pipe_ctx * pipe_ctx)3749 bool pipe_need_reprogram(
3750 		struct pipe_ctx *pipe_ctx_old,
3751 		struct pipe_ctx *pipe_ctx)
3752 {
3753 	if (!pipe_ctx_old->stream)
3754 		return false;
3755 
3756 	if (pipe_ctx_old->stream->sink != pipe_ctx->stream->sink)
3757 		return true;
3758 
3759 	if (pipe_ctx_old->stream->signal != pipe_ctx->stream->signal)
3760 		return true;
3761 
3762 	if (pipe_ctx_old->stream_res.audio != pipe_ctx->stream_res.audio)
3763 		return true;
3764 
3765 	if (pipe_ctx_old->clock_source != pipe_ctx->clock_source
3766 			&& pipe_ctx_old->stream != pipe_ctx->stream)
3767 		return true;
3768 
3769 	if (pipe_ctx_old->stream_res.stream_enc != pipe_ctx->stream_res.stream_enc)
3770 		return true;
3771 
3772 	if (dc_is_timing_changed(pipe_ctx_old->stream, pipe_ctx->stream))
3773 		return true;
3774 
3775 	if (pipe_ctx_old->stream->dpms_off != pipe_ctx->stream->dpms_off)
3776 		return true;
3777 
3778 	if (false == pipe_ctx_old->stream->link->link_state_valid &&
3779 		false == pipe_ctx_old->stream->dpms_off)
3780 		return true;
3781 
3782 	if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc)
3783 		return true;
3784 
3785 	if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc)
3786 		return true;
3787 	if (pipe_ctx_old->link_res.hpo_dp_link_enc != pipe_ctx->link_res.hpo_dp_link_enc)
3788 		return true;
3789 
3790 	/* DIG link encoder resource assignment for stream changed. */
3791 	if (pipe_ctx_old->stream->ctx->dc->res_pool->funcs->link_encs_assign) {
3792 		bool need_reprogram = false;
3793 		struct dc *dc = pipe_ctx_old->stream->ctx->dc;
3794 		struct link_encoder *link_enc_prev =
3795 			link_enc_cfg_get_link_enc_used_by_stream_current(dc, pipe_ctx_old->stream);
3796 
3797 		if (link_enc_prev != pipe_ctx->stream->link_enc)
3798 			need_reprogram = true;
3799 
3800 		return need_reprogram;
3801 	}
3802 
3803 	return false;
3804 }
3805 
resource_build_bit_depth_reduction_params(struct dc_stream_state * stream,struct bit_depth_reduction_params * fmt_bit_depth)3806 void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
3807 		struct bit_depth_reduction_params *fmt_bit_depth)
3808 {
3809 	enum dc_dither_option option = stream->dither_option;
3810 	enum dc_pixel_encoding pixel_encoding =
3811 			stream->timing.pixel_encoding;
3812 
3813 	memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth));
3814 
3815 	if (option == DITHER_OPTION_DEFAULT) {
3816 		switch (stream->timing.display_color_depth) {
3817 		case COLOR_DEPTH_666:
3818 			option = DITHER_OPTION_SPATIAL6;
3819 			break;
3820 		case COLOR_DEPTH_888:
3821 			option = DITHER_OPTION_SPATIAL8;
3822 			break;
3823 		case COLOR_DEPTH_101010:
3824 			option = DITHER_OPTION_SPATIAL10;
3825 			break;
3826 		default:
3827 			option = DITHER_OPTION_DISABLE;
3828 		}
3829 	}
3830 
3831 	if (option == DITHER_OPTION_DISABLE)
3832 		return;
3833 
3834 	if (option == DITHER_OPTION_TRUN6) {
3835 		fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
3836 		fmt_bit_depth->flags.TRUNCATE_DEPTH = 0;
3837 	} else if (option == DITHER_OPTION_TRUN8 ||
3838 			option == DITHER_OPTION_TRUN8_SPATIAL6 ||
3839 			option == DITHER_OPTION_TRUN8_FM6) {
3840 		fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
3841 		fmt_bit_depth->flags.TRUNCATE_DEPTH = 1;
3842 	} else if (option == DITHER_OPTION_TRUN10        ||
3843 			option == DITHER_OPTION_TRUN10_SPATIAL6   ||
3844 			option == DITHER_OPTION_TRUN10_SPATIAL8   ||
3845 			option == DITHER_OPTION_TRUN10_FM8     ||
3846 			option == DITHER_OPTION_TRUN10_FM6     ||
3847 			option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
3848 		fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
3849 		fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
3850 	}
3851 
3852 	/* special case - Formatter can only reduce by 4 bits at most.
3853 	 * When reducing from 12 to 6 bits,
3854 	 * HW recommends we use trunc with round mode
3855 	 * (if we did nothing, trunc to 10 bits would be used)
3856 	 * note that any 12->10 bit reduction is ignored prior to DCE8,
3857 	 * as the input was 10 bits.
3858 	 */
3859 	if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM ||
3860 			option == DITHER_OPTION_SPATIAL6 ||
3861 			option == DITHER_OPTION_FM6) {
3862 		fmt_bit_depth->flags.TRUNCATE_ENABLED = 1;
3863 		fmt_bit_depth->flags.TRUNCATE_DEPTH = 2;
3864 		fmt_bit_depth->flags.TRUNCATE_MODE = 1;
3865 	}
3866 
3867 	/* spatial dither
3868 	 * note that spatial modes 1-3 are never used
3869 	 */
3870 	if (option == DITHER_OPTION_SPATIAL6_FRAME_RANDOM            ||
3871 			option == DITHER_OPTION_SPATIAL6 ||
3872 			option == DITHER_OPTION_TRUN10_SPATIAL6      ||
3873 			option == DITHER_OPTION_TRUN8_SPATIAL6) {
3874 		fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
3875 		fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 0;
3876 		fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
3877 		fmt_bit_depth->flags.RGB_RANDOM =
3878 				(pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
3879 	} else if (option == DITHER_OPTION_SPATIAL8_FRAME_RANDOM            ||
3880 			option == DITHER_OPTION_SPATIAL8 ||
3881 			option == DITHER_OPTION_SPATIAL8_FM6        ||
3882 			option == DITHER_OPTION_TRUN10_SPATIAL8      ||
3883 			option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
3884 		fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
3885 		fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 1;
3886 		fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
3887 		fmt_bit_depth->flags.RGB_RANDOM =
3888 				(pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
3889 	} else if (option == DITHER_OPTION_SPATIAL10_FRAME_RANDOM ||
3890 			option == DITHER_OPTION_SPATIAL10 ||
3891 			option == DITHER_OPTION_SPATIAL10_FM8 ||
3892 			option == DITHER_OPTION_SPATIAL10_FM6) {
3893 		fmt_bit_depth->flags.SPATIAL_DITHER_ENABLED = 1;
3894 		fmt_bit_depth->flags.SPATIAL_DITHER_DEPTH = 2;
3895 		fmt_bit_depth->flags.HIGHPASS_RANDOM = 1;
3896 		fmt_bit_depth->flags.RGB_RANDOM =
3897 				(pixel_encoding == PIXEL_ENCODING_RGB) ? 1 : 0;
3898 	}
3899 
3900 	if (option == DITHER_OPTION_SPATIAL6 ||
3901 			option == DITHER_OPTION_SPATIAL8 ||
3902 			option == DITHER_OPTION_SPATIAL10) {
3903 		fmt_bit_depth->flags.FRAME_RANDOM = 0;
3904 	} else {
3905 		fmt_bit_depth->flags.FRAME_RANDOM = 1;
3906 	}
3907 
3908 	//////////////////////
3909 	//// temporal dither
3910 	//////////////////////
3911 	if (option == DITHER_OPTION_FM6           ||
3912 			option == DITHER_OPTION_SPATIAL8_FM6     ||
3913 			option == DITHER_OPTION_SPATIAL10_FM6     ||
3914 			option == DITHER_OPTION_TRUN10_FM6     ||
3915 			option == DITHER_OPTION_TRUN8_FM6      ||
3916 			option == DITHER_OPTION_TRUN10_SPATIAL8_FM6) {
3917 		fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
3918 		fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 0;
3919 	} else if (option == DITHER_OPTION_FM8        ||
3920 			option == DITHER_OPTION_SPATIAL10_FM8  ||
3921 			option == DITHER_OPTION_TRUN10_FM8) {
3922 		fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
3923 		fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 1;
3924 	} else if (option == DITHER_OPTION_FM10) {
3925 		fmt_bit_depth->flags.FRAME_MODULATION_ENABLED = 1;
3926 		fmt_bit_depth->flags.FRAME_MODULATION_DEPTH = 2;
3927 	}
3928 
3929 	fmt_bit_depth->pixel_encoding = pixel_encoding;
3930 }
3931 
dc_validate_stream(struct dc * dc,struct dc_stream_state * stream)3932 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
3933 {
3934 	if (dc == NULL || stream == NULL)
3935 		return DC_ERROR_UNEXPECTED;
3936 
3937 	struct dc_link *link = stream->link;
3938 	struct timing_generator *tg = dc->res_pool->timing_generators[0];
3939 	enum dc_status res = DC_OK;
3940 
3941 	calculate_phy_pix_clks(stream);
3942 
3943 	if (!tg->funcs->validate_timing(tg, &stream->timing))
3944 		res = DC_FAIL_CONTROLLER_VALIDATE;
3945 
3946 	if (res == DC_OK) {
3947 		if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
3948 				!link->link_enc->funcs->validate_output_with_stream(
3949 						link->link_enc, stream))
3950 			res = DC_FAIL_ENC_VALIDATE;
3951 	}
3952 
3953 	/* TODO: validate audio ASIC caps, encoder */
3954 
3955 	if (res == DC_OK)
3956 		res = dc->link_srv->validate_mode_timing(stream,
3957 		      link,
3958 		      &stream->timing);
3959 
3960 	return res;
3961 }
3962 
dc_validate_plane(struct dc * dc,const struct dc_plane_state * plane_state)3963 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
3964 {
3965 	enum dc_status res = DC_OK;
3966 
3967 	/* check if surface has invalid dimensions */
3968 	if (plane_state->src_rect.width == 0 || plane_state->src_rect.height == 0 ||
3969 		plane_state->dst_rect.width == 0 || plane_state->dst_rect.height == 0)
3970 		return DC_FAIL_SURFACE_VALIDATE;
3971 
3972 	/* TODO For now validates pixel format only */
3973 	if (dc->res_pool->funcs->validate_plane)
3974 		return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps);
3975 
3976 	return res;
3977 }
3978 
resource_pixel_format_to_bpp(enum surface_pixel_format format)3979 unsigned int resource_pixel_format_to_bpp(enum surface_pixel_format format)
3980 {
3981 	switch (format) {
3982 	case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
3983 		return 8;
3984 	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
3985 	case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
3986 		return 12;
3987 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
3988 	case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
3989 	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
3990 	case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
3991 		return 16;
3992 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
3993 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
3994 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
3995 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
3996 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
3997 	case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
3998 	case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
3999 		return 32;
4000 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
4001 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
4002 	case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
4003 	case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
4004 		return 64;
4005 	default:
4006 		ASSERT_CRITICAL(false);
4007 		return -1;
4008 	}
4009 }
get_max_audio_sample_rate(struct audio_mode * modes)4010 static unsigned int get_max_audio_sample_rate(struct audio_mode *modes)
4011 {
4012 	if (modes) {
4013 		if (modes->sample_rates.rate.RATE_192)
4014 			return 192000;
4015 		if (modes->sample_rates.rate.RATE_176_4)
4016 			return 176400;
4017 		if (modes->sample_rates.rate.RATE_96)
4018 			return 96000;
4019 		if (modes->sample_rates.rate.RATE_88_2)
4020 			return 88200;
4021 		if (modes->sample_rates.rate.RATE_48)
4022 			return 48000;
4023 		if (modes->sample_rates.rate.RATE_44_1)
4024 			return 44100;
4025 		if (modes->sample_rates.rate.RATE_32)
4026 			return 32000;
4027 	}
4028 	/*original logic when no audio info*/
4029 	return 441000;
4030 }
4031 
get_audio_check(struct audio_info * aud_modes,struct audio_check * audio_chk)4032 void get_audio_check(struct audio_info *aud_modes,
4033 	struct audio_check *audio_chk)
4034 {
4035 	unsigned int i;
4036 	unsigned int max_sample_rate = 0;
4037 
4038 	if (aud_modes) {
4039 		audio_chk->audio_packet_type = 0x2;/*audio sample packet AP = .25 for layout0, 1 for layout1*/
4040 
4041 		audio_chk->max_audiosample_rate = 0;
4042 		for (i = 0; i < aud_modes->mode_count; i++) {
4043 			max_sample_rate = get_max_audio_sample_rate(&aud_modes->modes[i]);
4044 			if (audio_chk->max_audiosample_rate < max_sample_rate)
4045 				audio_chk->max_audiosample_rate = max_sample_rate;
4046 			/*dts takes the same as type 2: AP = 0.25*/
4047 		}
4048 		/*check which one take more bandwidth*/
4049 		if (audio_chk->max_audiosample_rate > 192000)
4050 			audio_chk->audio_packet_type = 0x9;/*AP =1*/
4051 		audio_chk->acat = 0;/*not support*/
4052 	}
4053 }
4054 
get_temp_hpo_dp_link_enc(const struct resource_context * res_ctx,const struct resource_pool * const pool,const struct dc_link * link)4055 static struct hpo_dp_link_encoder *get_temp_hpo_dp_link_enc(
4056 		const struct resource_context *res_ctx,
4057 		const struct resource_pool *const pool,
4058 		const struct dc_link *link)
4059 {
4060 	struct hpo_dp_link_encoder *hpo_dp_link_enc = NULL;
4061 	int enc_index;
4062 
4063 	enc_index = find_acquired_hpo_dp_link_enc_for_link(res_ctx, link);
4064 
4065 	if (enc_index < 0)
4066 		enc_index = find_free_hpo_dp_link_enc(res_ctx, pool);
4067 
4068 	if (enc_index >= 0)
4069 		hpo_dp_link_enc = pool->hpo_dp_link_enc[enc_index];
4070 
4071 	return hpo_dp_link_enc;
4072 }
4073 
get_temp_dp_link_res(struct dc_link * link,struct link_resource * link_res,struct dc_link_settings * link_settings)4074 bool get_temp_dp_link_res(struct dc_link *link,
4075 		struct link_resource *link_res,
4076 		struct dc_link_settings *link_settings)
4077 {
4078 	const struct dc *dc  = link->dc;
4079 	const struct resource_context *res_ctx = &dc->current_state->res_ctx;
4080 
4081 	memset(link_res, 0, sizeof(*link_res));
4082 
4083 	if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) {
4084 		link_res->hpo_dp_link_enc = get_temp_hpo_dp_link_enc(res_ctx,
4085 				dc->res_pool, link);
4086 		if (!link_res->hpo_dp_link_enc)
4087 			return false;
4088 	}
4089 	return true;
4090 }
4091 
reset_syncd_pipes_from_disabled_pipes(struct dc * dc,struct dc_state * context)4092 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
4093 		struct dc_state *context)
4094 {
4095 	int i, j;
4096 	struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd;
4097 
4098 	/* If pipe backend is reset, need to reset pipe syncd status */
4099 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
4100 		pipe_ctx_old =	&dc->current_state->res_ctx.pipe_ctx[i];
4101 		pipe_ctx = &context->res_ctx.pipe_ctx[i];
4102 
4103 		if (!resource_is_pipe_type(pipe_ctx_old, OTG_MASTER))
4104 			continue;
4105 
4106 		if (!pipe_ctx->stream ||
4107 				pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
4108 
4109 			/* Reset all the syncd pipes from the disabled pipe */
4110 			for (j = 0; j < dc->res_pool->pipe_count; j++) {
4111 				pipe_ctx_syncd = &context->res_ctx.pipe_ctx[j];
4112 				if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_syncd) == pipe_ctx_old->pipe_idx) ||
4113 					!IS_PIPE_SYNCD_VALID(pipe_ctx_syncd))
4114 					SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_syncd, j);
4115 			}
4116 		}
4117 	}
4118 }
4119 
check_syncd_pipes_for_disabled_master_pipe(struct dc * dc,struct dc_state * context,uint8_t disabled_master_pipe_idx)4120 void check_syncd_pipes_for_disabled_master_pipe(struct dc *dc,
4121 	struct dc_state *context,
4122 	uint8_t disabled_master_pipe_idx)
4123 {
4124 	int i;
4125 	struct pipe_ctx *pipe_ctx, *pipe_ctx_check;
4126 
4127 	pipe_ctx = &context->res_ctx.pipe_ctx[disabled_master_pipe_idx];
4128 	if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx) != disabled_master_pipe_idx) ||
4129 		!IS_PIPE_SYNCD_VALID(pipe_ctx))
4130 		SET_PIPE_SYNCD_TO_PIPE(pipe_ctx, disabled_master_pipe_idx);
4131 
4132 	/* for the pipe disabled, check if any slave pipe exists and assert */
4133 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
4134 		pipe_ctx_check = &context->res_ctx.pipe_ctx[i];
4135 
4136 		if ((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_check) == disabled_master_pipe_idx) &&
4137 		    IS_PIPE_SYNCD_VALID(pipe_ctx_check) && (i != disabled_master_pipe_idx)) {
4138 			struct pipe_ctx *first_pipe = pipe_ctx_check;
4139 
4140 			while (first_pipe->prev_odm_pipe)
4141 				first_pipe = first_pipe->prev_odm_pipe;
4142 			/* When ODM combine is enabled, this case is expected. If the disabled pipe
4143 			 * is part of the ODM tree, then we should not print an error.
4144 			 * */
4145 			if (first_pipe->pipe_idx == disabled_master_pipe_idx)
4146 				continue;
4147 
4148 			DC_ERR("DC: Failure: pipe_idx[%d] syncd with disabled master pipe_idx[%d]\n",
4149 				   i, disabled_master_pipe_idx);
4150 		}
4151 	}
4152 }
4153 
reset_sync_context_for_pipe(const struct dc * dc,struct dc_state * context,uint8_t pipe_idx)4154 void reset_sync_context_for_pipe(const struct dc *dc,
4155 	struct dc_state *context,
4156 	uint8_t pipe_idx)
4157 {
4158 	int i;
4159 	struct pipe_ctx *pipe_ctx_reset;
4160 
4161 	/* reset the otg sync context for the pipe and its slave pipes if any */
4162 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
4163 		pipe_ctx_reset = &context->res_ctx.pipe_ctx[i];
4164 
4165 		if (((GET_PIPE_SYNCD_FROM_PIPE(pipe_ctx_reset) == pipe_idx) &&
4166 			IS_PIPE_SYNCD_VALID(pipe_ctx_reset)) || (i == pipe_idx))
4167 			SET_PIPE_SYNCD_TO_PIPE(pipe_ctx_reset, i);
4168 	}
4169 }
4170 
resource_transmitter_to_phy_idx(const struct dc * dc,enum transmitter transmitter)4171 uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter)
4172 {
4173 	/* TODO - get transmitter to phy idx mapping from DMUB */
4174 	uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A;
4175 
4176 	if (dc->ctx->dce_version == DCN_VERSION_3_1 &&
4177 			dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
4178 		switch (transmitter) {
4179 		case TRANSMITTER_UNIPHY_A:
4180 			phy_idx = 0;
4181 			break;
4182 		case TRANSMITTER_UNIPHY_B:
4183 			phy_idx = 1;
4184 			break;
4185 		case TRANSMITTER_UNIPHY_C:
4186 			phy_idx = 5;
4187 			break;
4188 		case TRANSMITTER_UNIPHY_D:
4189 			phy_idx = 6;
4190 			break;
4191 		case TRANSMITTER_UNIPHY_E:
4192 			phy_idx = 4;
4193 			break;
4194 		default:
4195 			phy_idx = 0;
4196 			break;
4197 		}
4198 	}
4199 
4200 	return phy_idx;
4201 }
4202 
get_link_hwss(const struct dc_link * link,const struct link_resource * link_res)4203 const struct link_hwss *get_link_hwss(const struct dc_link *link,
4204 		const struct link_resource *link_res)
4205 {
4206 	/* Link_hwss is only accessible by getter function instead of accessing
4207 	 * by pointers in dc with the intent to protect against breaking polymorphism.
4208 	 */
4209 	if (can_use_hpo_dp_link_hwss(link, link_res))
4210 		/* TODO: some assumes that if decided link settings is 128b/132b
4211 		 * channel coding format hpo_dp_link_enc should be used.
4212 		 * Others believe that if hpo_dp_link_enc is available in link
4213 		 * resource then hpo_dp_link_enc must be used. This bound between
4214 		 * hpo_dp_link_enc != NULL and decided link settings is loosely coupled
4215 		 * with a premise that both hpo_dp_link_enc pointer and decided link
4216 		 * settings are determined based on single policy function like
4217 		 * "decide_link_settings" from upper layer. This "convention"
4218 		 * cannot be maintained and enforced at current level.
4219 		 * Therefore a refactor is due so we can enforce a strong bound
4220 		 * between those two parameters at this level.
4221 		 *
4222 		 * To put it simple, we want to make enforcement at low level so that
4223 		 * we will not return link hwss if caller plans to do 8b/10b
4224 		 * with an hpo encoder. Or we can return a very dummy one that doesn't
4225 		 * do work for all functions
4226 		 */
4227 		return (requires_fixed_vs_pe_retimer_hpo_link_hwss(link) ?
4228 				get_hpo_fixed_vs_pe_retimer_dp_link_hwss() : get_hpo_dp_link_hwss());
4229 	else if (can_use_dpia_link_hwss(link, link_res))
4230 		return get_dpia_link_hwss();
4231 	else if (can_use_dio_link_hwss(link, link_res))
4232 		return (requires_fixed_vs_pe_retimer_dio_link_hwss(link)) ?
4233 				get_dio_fixed_vs_pe_retimer_link_hwss() : get_dio_link_hwss();
4234 	else
4235 		return get_virtual_link_hwss();
4236 }
4237 
is_h_timing_divisible_by_2(struct dc_stream_state * stream)4238 bool is_h_timing_divisible_by_2(struct dc_stream_state *stream)
4239 {
4240 	bool divisible = false;
4241 	uint16_t h_blank_start = 0;
4242 	uint16_t h_blank_end = 0;
4243 
4244 	if (stream) {
4245 		h_blank_start = stream->timing.h_total - stream->timing.h_front_porch;
4246 		h_blank_end = h_blank_start - stream->timing.h_addressable;
4247 
4248 		/* HTOTAL, Hblank start/end, and Hsync start/end all must be
4249 		 * divisible by 2 in order for the horizontal timing params
4250 		 * to be considered divisible by 2. Hsync start is always 0.
4251 		 */
4252 		divisible = (stream->timing.h_total % 2 == 0) &&
4253 				(h_blank_start % 2 == 0) &&
4254 				(h_blank_end % 2 == 0) &&
4255 				(stream->timing.h_sync_width % 2 == 0);
4256 	}
4257 	return divisible;
4258 }
4259 
dc_resource_acquire_secondary_pipe_for_mpc_odm(const struct dc * dc,struct dc_state * state,struct pipe_ctx * pri_pipe,struct pipe_ctx * sec_pipe,bool odm)4260 bool dc_resource_acquire_secondary_pipe_for_mpc_odm(
4261 		const struct dc *dc,
4262 		struct dc_state *state,
4263 		struct pipe_ctx *pri_pipe,
4264 		struct pipe_ctx *sec_pipe,
4265 		bool odm)
4266 {
4267 	int pipe_idx = sec_pipe->pipe_idx;
4268 	struct pipe_ctx *sec_top, *sec_bottom, *sec_next, *sec_prev;
4269 	const struct resource_pool *pool = dc->res_pool;
4270 
4271 	sec_top = sec_pipe->top_pipe;
4272 	sec_bottom = sec_pipe->bottom_pipe;
4273 	sec_next = sec_pipe->next_odm_pipe;
4274 	sec_prev = sec_pipe->prev_odm_pipe;
4275 
4276 	*sec_pipe = *pri_pipe;
4277 
4278 	sec_pipe->top_pipe = sec_top;
4279 	sec_pipe->bottom_pipe = sec_bottom;
4280 	sec_pipe->next_odm_pipe = sec_next;
4281 	sec_pipe->prev_odm_pipe = sec_prev;
4282 
4283 	sec_pipe->pipe_idx = pipe_idx;
4284 	sec_pipe->plane_res.mi = pool->mis[pipe_idx];
4285 	sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
4286 	sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
4287 	sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
4288 	sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
4289 	sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
4290 	sec_pipe->stream_res.dsc = NULL;
4291 	if (odm) {
4292 		if (!sec_pipe->top_pipe)
4293 			sec_pipe->stream_res.opp = pool->opps[pipe_idx];
4294 		else
4295 			sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
4296 		if (sec_pipe->stream->timing.flags.DSC == 1) {
4297 #if defined(CONFIG_DRM_AMD_DC_FP)
4298 			dcn20_acquire_dsc(dc, &state->res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
4299 #endif
4300 			ASSERT(sec_pipe->stream_res.dsc);
4301 			if (sec_pipe->stream_res.dsc == NULL)
4302 				return false;
4303 		}
4304 #if defined(CONFIG_DRM_AMD_DC_FP)
4305 		dcn20_build_mapped_resource(dc, state, sec_pipe->stream);
4306 #endif
4307 	}
4308 
4309 	return true;
4310 }
4311 
update_dp_encoder_resources_for_test_harness(const struct dc * dc,struct dc_state * context,struct pipe_ctx * pipe_ctx)4312 enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc,
4313 		struct dc_state *context,
4314 		struct pipe_ctx *pipe_ctx)
4315 {
4316 	if (dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings) == DP_128b_132b_ENCODING) {
4317 		if (pipe_ctx->stream_res.hpo_dp_stream_enc == NULL) {
4318 			pipe_ctx->stream_res.hpo_dp_stream_enc =
4319 					find_first_free_match_hpo_dp_stream_enc_for_link(
4320 							&context->res_ctx, dc->res_pool, pipe_ctx->stream);
4321 
4322 			if (!pipe_ctx->stream_res.hpo_dp_stream_enc)
4323 				return DC_NO_STREAM_ENC_RESOURCE;
4324 
4325 			update_hpo_dp_stream_engine_usage(
4326 					&context->res_ctx, dc->res_pool,
4327 					pipe_ctx->stream_res.hpo_dp_stream_enc,
4328 					true);
4329 		}
4330 
4331 		if (pipe_ctx->link_res.hpo_dp_link_enc == NULL) {
4332 			if (!add_hpo_dp_link_enc_to_ctx(&context->res_ctx, dc->res_pool, pipe_ctx, pipe_ctx->stream))
4333 				return DC_NO_LINK_ENC_RESOURCE;
4334 		}
4335 	} else {
4336 		if (pipe_ctx->stream_res.hpo_dp_stream_enc) {
4337 			update_hpo_dp_stream_engine_usage(
4338 					&context->res_ctx, dc->res_pool,
4339 					pipe_ctx->stream_res.hpo_dp_stream_enc,
4340 					false);
4341 			pipe_ctx->stream_res.hpo_dp_stream_enc = NULL;
4342 		}
4343 		if (pipe_ctx->link_res.hpo_dp_link_enc)
4344 			remove_hpo_dp_link_enc_from_ctx(&context->res_ctx, pipe_ctx, pipe_ctx->stream);
4345 	}
4346 
4347 	return DC_OK;
4348 }
4349 
4350