| /openbmc/qemu/include/qemu/ |
| H A D | log.h | 54 #define qemu_log_mask(MASK, FMT, ...) \ argument
68 #define qemu_log_mask_and_addr(MASK, ADDR, FMT, ...) \ argument
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| /openbmc/u-boot/board/micronas/vct/ |
| H A D | gpio.c | 22 #define MASK(pin) (1 << ((pin) & 0x1F)) macro
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | iwmmxt_helper.c | 301 #define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((a >> SHR) & MASK) OPER \ argument
307 #define CMP(SHR, TYPE, OPER, MASK) ((((TYPE) ((a >> SHR) & MASK) OPER \ argument
314 #define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((a >> SHR) & MASK) \ argument
320 #define CMP(SHR, TYPE, OPER, MASK) ((uint64_t) (((TYPE) ((a >> SHR) & MASK) \ argument
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| H A D | sve_helper.c | 3790 #define DO_CMP_PPZZ(NAME, TYPE, OP, H, MASK) \ argument
3858 #define DO_CMP_PPZW(NAME, TYPE, TYPEW, OP, H, MASK) \ argument
3935 #define DO_CMP_PPZI(NAME, TYPE, OP, H, MASK) \ argument
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| /openbmc/qemu/target/hexagon/mmvec/ |
| H A D | macros.h | 50 #define LOG_VTCM_BYTE(VA, MASK, VAL, IDX) \ argument
70 #define fGETQBITS(REG, WIDTH, MASK, BITNO) \ argument
96 #define fSETQBITS(REG, WIDTH, MASK, BITNO, VAL) \ argument
110 #define fV_AL_CHECK(EA, MASK) \ argument
295 #define fSTOREMMVQ(EA, SRC, MASK) \ argument
299 #define fSTOREMMVNQ(EA, SRC, MASK) \ argument
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| /openbmc/u-boot/test/lib/ |
| H A D | string.c | 19 #define MASK 0xA5 macro
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| /openbmc/u-boot/include/ |
| H A D | lattice.h | 130 #define MASK 0x15 /* The following data stream is used as mask. */ macro
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| H A D | sym53c8xx.h | 529 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) macro
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| /openbmc/qemu/target/loongarch/tcg/ |
| H A D | vec_helper.c | 2326 #define VFRSTP(NAME, BIT, MASK, E) \ argument
3165 #define XVINSVE0(NAME, E, MASK) \ argument
3176 #define XVPICKVE(NAME, E, BIT, MASK) \ argument
3474 #define VEXTRINS(NAME, BIT, E, MASK) \ argument
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| /openbmc/qemu/hw/scsi/ |
| H A D | vmw_pvscsi.h | 30 #define MASK(n) ((1 << (n)) - 1) /* make an n-bit mask */ macro
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| /openbmc/qemu/tests/qtest/libqos/ |
| H A D | ahci.c | 1261 #define RSET(REG, MASK) (BITSET(ahci_px_rreg(ahci, cmd->port, (REG)), (MASK))) in ahci_command_wait() argument
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| /openbmc/qemu/target/riscv/ |
| H A D | vector_helper.c | 1342 #define GEN_VEXT_SHIFT_VV(NAME, TS1, TS2, HS1, HS2, OP, MASK) \ argument
1389 #define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \ argument
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| /openbmc/qemu/tcg/ |
| H A D | tcg.c | 3408 #define CONST(CASE, MASK) \ in process_constraint_sets() argument
3410 #define REGS(CASE, MASK) \ in process_constraint_sets() argument
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