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/openbmc/linux/fs/unicode/
H A Dutf8data.c_shipped96 0xe1,0x8d,0xa9,0x10,0x08,0x01,0xff,0xe8,0xb1,0x88,0x00,0x01,0xff,0xe6,0x9b,0xb4,
98 0xab,0x10,0x08,0x01,0xff,0xe9,0xb9,0xbf,0x00,0x01,0xff,0xe8,0xab,0x96,0x00,0xe3,
99 0x09,0xac,0xe2,0xe8,0xab,0xe1,0xd7,0xab,0x10,0x08,0x01,0xff,0xe7,0xb8,0xb7,0x00,
109 0x4e,0xe3,0xe2,0x2d,0xe3,0xe1,0x1b,0xe3,0x10,0x08,0x05,0xff,0xe4,0xb8,0xbd,0x00,
111 0xe2,0x0e,0xe5,0xe1,0xfd,0xe4,0x10,0x08,0x05,0xff,0xe5,0x92,0xa2,0x00,0x05,0xff,
112 0xe5,0x93,0xb6,0x00,0xd4,0x34,0xd3,0x18,0xe2,0xf7,0xe5,0xe1,0xe6,0xe5,0x10,0x09,
114 0xe6,0x91,0x11,0x10,0x09,0x05,0xff,0xf0,0xa1,0x8d,0xaa,0x00,0x05,0xff,0xe5,0xac,
116 0x10,0x08,0x05,0xff,0xe5,0xaf,0xb3,0x00,0x05,0xff,0xf0,0xa1,0xac,0x98,0x00,0xe1,
117 0x38,0xe6,0x10,0x08,0x05,0xff,0xe5,0xbc,0xb3,0x00,0x05,0xff,0xe5,0xb0,0xa2,0x00,
119 0xea,0xe1,0x93,0xea,0x10,0x08,0x05,0xff,0xe6,0xb4,0xbe,0x00,0x05,0xff,0xe6,0xb5,
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-skov-revc-lt2.dtsi69 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
70 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
71 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
72 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
73 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
74 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
75 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
76 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
77 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
78 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
H A Dimx6dl-skov-revc-lt6.dts76 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
77 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
78 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
79 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
80 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
81 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
82 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
83 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
84 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
85 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
H A Dimx6qdl-phytec-mira-peb-av-02.dtsi77 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
78 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
79 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
81 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
82 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
83 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
84 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
85 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
86 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
87 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
[all …]
H A Dimx6q-skov-revc-lt6.dts98 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
99 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
100 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
101 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
102 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
103 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
104 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
105 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
106 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
107 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
H A Dimx6qdl-aristainetos.dtsi296 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x10
323 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
324 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
325 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
326 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
328 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
329 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
330 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
331 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
332 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
[all …]
H A Dimx6q-kp.dtsi287 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
288 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
289 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
290 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
291 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
292 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
293 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
294 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
295 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
296 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
H A Dimx6qdl-tx6.dtsi378 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
379 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
380 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
381 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
383 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
384 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
385 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
386 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
387 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
388 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
[all …]
H A Dimx6ul-tx6ul.dtsi597 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
598 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
599 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
600 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
602 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10
603 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
604 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
605 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
606 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
607 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
[all …]
H A Dimx6ul-tx6ul-mainboard.dts203 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */
204 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */
205 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */
206 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */
207 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10
208 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10
209 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10
210 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10
211 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10
212 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10
[all …]
H A Dimx6dl-mamoj.dts401 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 /* VDOUT_PCLK */
402 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
403 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 /* VDOUT_HSYNC */
404 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 /* VDOUT_VSYNC */
405 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10 /* VDOUT_RESET */
406 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
407 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
408 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
409 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
410 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
[all …]
H A Dimx6qdl-pico.dtsi476 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
477 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
478 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
479 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
480 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x10
481 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
482 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
483 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
484 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
485 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
[all …]
H A Dimx6dl-yapp43-common.dtsi427 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
428 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
429 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
430 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
431 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
432 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
433 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
434 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
435 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
436 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
[all …]
H A Dimx6dl-yapp4-common.dtsi122 reg = <0x10>;
426 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
427 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
428 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
429 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
430 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
431 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
432 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
433 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
434 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
H A Dimx6qdl-nitrogen6x.dtsi450 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
451 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
452 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
453 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
454 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
455 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
456 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
457 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
458 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
459 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
H A Dimx6qdl-emcon.dtsi576 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
577 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
578 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
579 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
580 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
581 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
582 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
583 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
584 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
585 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
H A Dimx6qdl-nitrogen6_som2.dtsi444 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
445 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
446 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
447 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
448 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
449 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
450 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
451 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
452 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
453 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
H A Dimx6qdl-sabrelite.dtsi511 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
512 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
513 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
514 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
515 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
516 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
517 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
518 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
519 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
520 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
[all …]
/openbmc/u-boot/arch/arm/lib/
H A Dgic_64.S82 mrs x10, mpidr_el1
83 lsr x9, x10, #32
84 bfi x10, x9, #24, #8 /* w10 is aff3:aff2:aff1:aff0 */
103 add x10, x9, #(1 << 16) /* SGI_Base */
105 str w11, [x10, GICR_IGROUPRn]
106 str wzr, [x10, GICR_IGROUPMODRn] /* SGIs|PPIs Group1NS */
108 str w11, [x10, GICR_ISENABLERn]
110 switch_el x10, 3f, 2f, 1f
113 mrs x10, ICC_SRE_EL3
114 orr x10, x10, #0xf /* SRE & Disable IRQ/FIQ Bypass & */
[all …]
H A Dccn504.S30 1: ldr x10, [x0, x2]
31 mvn x11, x10
32 tst x11, x10 /* Wait for domain addition to complete */
54 mov x10, x1
55 orr x9, x9, x10
75 mov x10, x1
76 orr x9, x9, x10
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam335x-pocketbeagle.dts221 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
222 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
230 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
231 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
239 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
240 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
248 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
249 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
257 pinctrl-single,bias-pullup = < 0x10 0x10 0x00 0x18>;
258 pinctrl-single,bias-pulldown = < 0x10 0x00 0x10 0x18>;
[all …]
/openbmc/linux/drivers/scsi/aic7xxx/
H A Daic79xx_reg_print.c_shipped16 { "PCIINT", 0x10, 0x10 },
47 { "SEQ_SWTMRTO", 0x10, 0x10 }
62 { "AUTOCLRCMDINT", 0x10, 0x10 },
101 { "MREQPEND", 0x10, 0x10 },
129 { "FORCEBUSFREE", 0x10, 0x10 },
146 { "ENRSELI", 0x10, 0x10 },
162 { "FIFO0FREE", 0x10, 0x10 },
187 { "ATNI", 0x10, 0x10 },
207 { "COMMAND_PHASE", 0x10, 0x10 },
242 { "ENSELINGO", 0x10, 0x10 },
[all …]
H A Daic7xxx_reg_print.c_shipped16 { "ENRSELI", 0x10, 0x10 },
33 { "CLRSTCNT", 0x10, 0x10 },
51 { "ATNI", 0x10, 0x10 },
74 { "SINGLE_EDGE", 0x10, 0x10 },
95 { "SELINGO", 0x10, 0x10 },
113 { "PHASEMIS", 0x10, 0x10 },
131 { "EXP_ACTIVE", 0x10, 0x10 },
163 { "ENSELINGO", 0x10, 0x10 },
172 0x10, regvalue, cur_col, wrap));
180 { "ENPHASEMIS", 0x10, 0x10 },
[all …]
/openbmc/qemu/tests/tcg/arm/
H A Dfcvt.ref33 14 HALF: 0x400 (0x10 => INEXACT )
41 18 HALF: 0x4170 (0x10 => INEXACT )
43 19 HALF: 0x4248 (0x10 => INEXACT )
45 20 HALF: 0x7bff (0x10 => INEXACT )
49 22 HALF: 0x7bff (0x10 => INEXACT )
151 10 HALF: 0000 (0x10 => INEXACT )
153 11 HALF: 0000 (0x10 => INEXACT )
157 13 HALF: 0000 (0x10 => INEXACT )
159 14 HALF: 0000 (0x10 => INEXACT )
161 15 HALF: 0000 (0x10 => INEXACT )
[all …]
/openbmc/qemu/target/ppc/translate/
H A Dvsx-ops.c.inc73 GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x10, opc4 | 0x0, inval), \
77 GEN_VSX_XFORM_300_EO(name, opc2, opc3 | 0x10, opc4 | 0x1, inval), \
83 GEN_VSX_XFORM_300(xssubqp, 0x04, 0x10, 0x0),
92 GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
129 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
130 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
131 GEN_XX2FORM_EO(xscvhpdp, 0x16, 0x15, 0x10, PPC2_ISA300),
134 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
135 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
136 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
[all …]

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