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Searched refs:writel_bits (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/drivers/video/meson/
H A Dmeson_vpu_init.c156 writel_bits(3 << 30, m[21] << 30, in meson_viu_set_osd_matrix()
159 writel_bits(7 << 16, m[22] << 16, in meson_viu_set_osd_matrix()
164 writel_bits(BIT(0), csc_on ? BIT(0) : 0, in meson_viu_set_osd_matrix()
166 writel_bits(BIT(1), 0, in meson_viu_set_osd_matrix()
177 writel_bits(BIT(30), csc_on ? BIT(30) : 0, in meson_viu_set_osd_matrix()
179 writel_bits(BIT(31), csc_on ? BIT(31) : 0, in meson_viu_set_osd_matrix()
232 writel_bits(0x7 << 29, 7 << 29, in meson_viu_set_osd_lut()
235 writel_bits(0x7 << 29, 0, in meson_viu_set_osd_lut()
259 writel_bits(7 << 27, 7 << 27, in meson_viu_set_osd_lut()
262 writel_bits(7 << 27, 0, in meson_viu_set_osd_lut()
[all …]
H A Dmeson_plane.c115 writel_bits(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE, in meson_vpu_setup_plane()
133 writel_bits(OSD_REPLACE_EN, OSD_REPLACE_EN, in meson_vpu_setup_plane()
175 writel_bits(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND, in meson_vpu_setup_plane()
H A Dmeson_vpu.h48 writel_bits(mask, value, priv->hhi_base + offset)
57 writel_bits(mask, value, priv->dmc_base + offset)
H A Dmeson_dw_hdmi.c404 writel_bits(BIT(15), BIT(15), priv->hdmi.ioaddr + HDMITX_TOP_CTRL_REG); in meson_dw_hdmi_probe()
405 writel_bits(BIT(15), BIT(15), priv->hdmi.ioaddr + HDMITX_DWC_CTRL_REG); in meson_dw_hdmi_probe()
H A Dmeson_venc.c840 writel_bits(0xff, 0xff, in meson_venc_hdmi_mode_set()
1180 writel_bits(BIT(14), BIT(14), in meson_venc_hdmi_mode_set()
1444 writel_bits(BIT(5), 0, priv->io_base + _REG(VENC_VDAC_DACSEL0)); in meson_venci_cvbs_mode_set()
H A Dmeson_vclk.c14 #define writel_bits(mask, val, addr) \ macro
H A Dmeson_registers.h12 #define writel_bits(mask, val, addr) \ macro