1*3bed4220SNeil Armstrong /* SPDX-License-Identifier: GPL-2.0 */
2*3bed4220SNeil Armstrong /*
3*3bed4220SNeil Armstrong * Amlogic Meson Video Processing Unit driver
4*3bed4220SNeil Armstrong *
5*3bed4220SNeil Armstrong * Copyright (c) 2018 BayLibre, SAS.
6*3bed4220SNeil Armstrong * Author: Neil Armstrong <narmstrong@baylibre.com>
7*3bed4220SNeil Armstrong */
8*3bed4220SNeil Armstrong
9*3bed4220SNeil Armstrong #ifndef __MESON_VPU_H__
10*3bed4220SNeil Armstrong #define __MESON_VPU_H__
11*3bed4220SNeil Armstrong
12*3bed4220SNeil Armstrong #include <common.h>
13*3bed4220SNeil Armstrong #include <dm.h>
14*3bed4220SNeil Armstrong #include <video.h>
15*3bed4220SNeil Armstrong #include <display.h>
16*3bed4220SNeil Armstrong #include <linux/io.h>
17*3bed4220SNeil Armstrong #include "meson_registers.h"
18*3bed4220SNeil Armstrong
19*3bed4220SNeil Armstrong enum {
20*3bed4220SNeil Armstrong /* Maximum size we support */
21*3bed4220SNeil Armstrong VPU_MAX_WIDTH = 3840,
22*3bed4220SNeil Armstrong VPU_MAX_HEIGHT = 2160,
23*3bed4220SNeil Armstrong VPU_MAX_LOG2_BPP = VIDEO_BPP32,
24*3bed4220SNeil Armstrong };
25*3bed4220SNeil Armstrong
26*3bed4220SNeil Armstrong enum vpu_compatible {
27*3bed4220SNeil Armstrong VPU_COMPATIBLE_GXBB = 0,
28*3bed4220SNeil Armstrong VPU_COMPATIBLE_GXL = 1,
29*3bed4220SNeil Armstrong VPU_COMPATIBLE_GXM = 2,
30*3bed4220SNeil Armstrong };
31*3bed4220SNeil Armstrong
32*3bed4220SNeil Armstrong struct meson_vpu_priv {
33*3bed4220SNeil Armstrong struct udevice *dev;
34*3bed4220SNeil Armstrong void __iomem *io_base;
35*3bed4220SNeil Armstrong void __iomem *hhi_base;
36*3bed4220SNeil Armstrong void __iomem *dmc_base;
37*3bed4220SNeil Armstrong };
38*3bed4220SNeil Armstrong
meson_vpu_is_compatible(struct meson_vpu_priv * priv,enum vpu_compatible family)39*3bed4220SNeil Armstrong static inline bool meson_vpu_is_compatible(struct meson_vpu_priv *priv,
40*3bed4220SNeil Armstrong enum vpu_compatible family)
41*3bed4220SNeil Armstrong {
42*3bed4220SNeil Armstrong enum vpu_compatible compat = dev_get_driver_data(priv->dev);
43*3bed4220SNeil Armstrong
44*3bed4220SNeil Armstrong return compat == family;
45*3bed4220SNeil Armstrong }
46*3bed4220SNeil Armstrong
47*3bed4220SNeil Armstrong #define hhi_update_bits(offset, mask, value) \
48*3bed4220SNeil Armstrong writel_bits(mask, value, priv->hhi_base + offset)
49*3bed4220SNeil Armstrong
50*3bed4220SNeil Armstrong #define hhi_write(offset, value) \
51*3bed4220SNeil Armstrong writel(value, priv->hhi_base + offset)
52*3bed4220SNeil Armstrong
53*3bed4220SNeil Armstrong #define hhi_read(offset) \
54*3bed4220SNeil Armstrong readl(priv->hhi_base + offset)
55*3bed4220SNeil Armstrong
56*3bed4220SNeil Armstrong #define dmc_update_bits(offset, mask, value) \
57*3bed4220SNeil Armstrong writel_bits(mask, value, priv->dmc_base + offset)
58*3bed4220SNeil Armstrong
59*3bed4220SNeil Armstrong #define dmc_write(offset, value) \
60*3bed4220SNeil Armstrong writel(value, priv->dmc_base + offset)
61*3bed4220SNeil Armstrong
62*3bed4220SNeil Armstrong #define dmc_read(offset) \
63*3bed4220SNeil Armstrong readl(priv->dmc_base + offset)
64*3bed4220SNeil Armstrong
65*3bed4220SNeil Armstrong #define MESON_CANVAS_ID_OSD1 0x4e
66*3bed4220SNeil Armstrong
67*3bed4220SNeil Armstrong /* Canvas configuration. */
68*3bed4220SNeil Armstrong #define MESON_CANVAS_WRAP_NONE 0x00
69*3bed4220SNeil Armstrong #define MESON_CANVAS_WRAP_X 0x01
70*3bed4220SNeil Armstrong #define MESON_CANVAS_WRAP_Y 0x02
71*3bed4220SNeil Armstrong
72*3bed4220SNeil Armstrong #define MESON_CANVAS_BLKMODE_LINEAR 0x00
73*3bed4220SNeil Armstrong #define MESON_CANVAS_BLKMODE_32x32 0x01
74*3bed4220SNeil Armstrong #define MESON_CANVAS_BLKMODE_64x64 0x02
75*3bed4220SNeil Armstrong
76*3bed4220SNeil Armstrong void meson_canvas_setup(struct meson_vpu_priv *priv,
77*3bed4220SNeil Armstrong u32 canvas_index, u32 addr,
78*3bed4220SNeil Armstrong u32 stride, u32 height,
79*3bed4220SNeil Armstrong unsigned int wrap,
80*3bed4220SNeil Armstrong unsigned int blkmode);
81*3bed4220SNeil Armstrong
82*3bed4220SNeil Armstrong /* Mux VIU/VPP to ENCI */
83*3bed4220SNeil Armstrong #define MESON_VIU_VPP_MUX_ENCI 0x5
84*3bed4220SNeil Armstrong /* Mux VIU/VPP to ENCP */
85*3bed4220SNeil Armstrong #define MESON_VIU_VPP_MUX_ENCP 0xA
86*3bed4220SNeil Armstrong
87*3bed4220SNeil Armstrong void meson_vpp_setup_mux(struct meson_vpu_priv *priv, unsigned int mux);
88*3bed4220SNeil Armstrong void meson_vpu_init(struct udevice *dev);
89*3bed4220SNeil Armstrong void meson_vpu_setup_plane(struct udevice *dev, bool is_interlaced);
90*3bed4220SNeil Armstrong bool meson_venc_hdmi_supported_mode(const struct display_timing *mode);
91*3bed4220SNeil Armstrong void meson_vpu_setup_venc(struct udevice *dev,
92*3bed4220SNeil Armstrong const struct display_timing *mode, bool is_cvbs);
93*3bed4220SNeil Armstrong bool meson_vclk_dmt_supported_freq(struct meson_vpu_priv *priv,
94*3bed4220SNeil Armstrong unsigned int freq);
95*3bed4220SNeil Armstrong void meson_vpu_setup_vclk(struct udevice *dev,
96*3bed4220SNeil Armstrong const struct display_timing *mode, bool is_cvbs);
97*3bed4220SNeil Armstrong #endif
98