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Searched refs:writel_be (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/sound/pci/mixart/
H A Dmixart_core.c56 writel_be(tailptr, MIXART_MEM(mgr, MSG_OUTBOUND_POST_TAIL)); in retrieve_msg_frame()
109 writel_be(msg_frame_address, MIXART_MEM(mgr, headptr)); in get_msg()
116 writel_be(headptr, MIXART_MEM(mgr, MSG_OUTBOUND_FREE_HEAD)); in get_msg()
161 writel_be(tailptr, MIXART_MEM(mgr, MSG_INBOUND_FREE_TAIL)); in send_msg()
166 …writel_be( msg->size + MSG_DESCRIPTOR_SIZE, MIXART_MEM(mgr, msg_frame_address) ); /* siz… in send_msg()
167 …writel_be( msg->message_id , MIXART_MEM(mgr, msg_frame_address + 4) ); /* dwM… in send_msg()
168 …writel_be( msg->uid.object_id, MIXART_MEM(mgr, msg_frame_address + 8) ); /* uid… in send_msg()
169 writel_be( msg->uid.desc, MIXART_MEM(mgr, msg_frame_address + 12) ); /* */ in send_msg()
170 …writel_be( MSG_DESCRIPTOR_SIZE, MIXART_MEM(mgr, msg_frame_address + 16) ); /* Siz… in send_msg()
171 …writel_be( MSG_DESCRIPTOR_SIZE, MIXART_MEM(mgr, msg_frame_address + 20) ); /* Off… in send_msg()
[all …]
H A Dmixart_hwdep.c379 writel_be( 1, MIXART_MEM( mgr, MIXART_PSEUDOREG_MXLX_STATUS_OFFSET )); in mixart_dsp_load()
382 …writel_be( MIXART_MOTHERBOARD_XLX_BASE_ADDRESS, MIXART_MEM( mgr,MIXART_PSEUDOREG_MXLX_BASE_ADDR_OF… in mixart_dsp_load()
384 writel_be( dsp->size, MIXART_MEM( mgr, MIXART_PSEUDOREG_MXLX_SIZE_OFFSET )); in mixart_dsp_load()
390 writel_be( 2, MIXART_MEM( mgr, MIXART_PSEUDOREG_MXLX_STATUS_OFFSET )); in mixart_dsp_load()
419 writel_be( 0, MIXART_MEM( mgr, MIXART_PSEUDOREG_BOARDNUMBER ) ); /* set miXart boardnumber to 0 */ in mixart_dsp_load()
420 …writel_be( 0, MIXART_MEM( mgr, MIXART_FLOWTABLE_PTR ) ); /* reset pointer to flow table on… in mixart_dsp_load()
423 writel_be( 1, MIXART_MEM( mgr, MIXART_PSEUDOREG_ELF_STATUS_OFFSET )); in mixart_dsp_load()
430 writel_be( 2, MIXART_MEM( mgr, MIXART_PSEUDOREG_ELF_STATUS_OFFSET )); in mixart_dsp_load()
440 …writel_be( (u32)mgr->flowinfo.addr, MIXART_MEM( mgr, MIXART_FLOWTABLE_PTR ) ); /* give pointer of … in mixart_dsp_load()
486 writel_be( dsp->size, MIXART_MEM( mgr, MIXART_PSEUDOREG_DXLX_SIZE_OFFSET )); in mixart_dsp_load()
[all …]
H A Dmixart_hwdep.h19 #ifndef writel_be
20 #define writel_be(data,addr) __raw_writel((__force u32)cpu_to_be32(data),addr) macro
/openbmc/u-boot/drivers/net/
H A Dbcm6348-eth.c138 writel_be(ETH_CTL_RESET_MASK, priv->base + ETH_CTL_REG); in bcm6348_eth_mac_reset()
225 writel_be(0, MIB_REG(i)); in bcm6348_eth_start()
231 writel_be((ETH_MAX_MTU_SIZE << ETH_RXMAXLEN_SHIFT) & in bcm6348_eth_start()
233 writel_be((ETH_MAX_MTU_SIZE << ETH_TXMAXLEN_SHIFT) & in bcm6348_eth_start()
237 writel_be((ETH_TX_WATERMARK << ETH_TXWMARK_WM_SHIFT) & in bcm6348_eth_start()
244 writel_be(0, priv->base + ETH_IRMASK_REG); in bcm6348_eth_start()
278 writel_be((pdata->enetaddr[2] << 24) | (pdata->enetaddr[3]) << 16 | in bcm6348_eth_write_hwaddr()
281 writel_be((pdata->enetaddr[1]) | (pdata->enetaddr[0] << 8) | in bcm6348_eth_write_hwaddr()
308 writel_be(ETH_IR_MII_MASK, base + ETH_IR_REG); in bcm6348_mdio_op()
311 writel_be(data, base + MII_DAT_REG); in bcm6348_mdio_op()
[all …]
H A Dbcm6368-eth.c150 writel_be(0, priv->base + MII_SC_REG); in bcm6368_mdio_read()
159 writel_be(val, priv->base + MII_SC_REG); in bcm6368_mdio_read()
170 writel_be(0, priv->base + MII_SC_REG); in bcm6368_mdio_write()
181 writel_be(val, priv->base + MII_SC_REG); in bcm6368_mdio_write()
626 writel_be(0x1ff, priv->base + ETH_JMBCTL_PORT_REG); in bcm6368_eth_probe()
/openbmc/u-boot/drivers/dma/
H A Dbcm6348-iudma.c163 writel_be(halt, priv->chan + DMAC_CFG_REG(ch)); in bcm6348_iudma_chan_stop()
193 writel_be(DMA_FLOWC_ALLOC_FORCE_MASK, in bcm6348_iudma_disable()
239 writel_be(0, priv->sram + DMAS_STATE_DATA_REG(dma->id)); in bcm6348_iudma_enable()
240 writel_be(0, priv->sram + DMAS_DESC_LEN_STATUS_REG(dma->id)); in bcm6348_iudma_enable()
241 writel_be(0, priv->sram + DMAS_DESC_BASE_BUFPTR_REG(dma->id)); in bcm6348_iudma_enable()
244 writel_be(virt_to_phys(ch_priv->dma_ring), in bcm6348_iudma_enable()
255 writel_be(val, priv->base + DMA_FLOWC_THR_LO_REG(dma->id)); in bcm6348_iudma_enable()
258 writel_be(val, priv->base + DMA_FLOWC_THR_HI_REG(dma->id)); in bcm6348_iudma_enable()
260 writel_be(0, priv->base + DMA_FLOWC_ALLOC_REG(dma->id)); in bcm6348_iudma_enable()
264 writel_be(ch_priv->desc_cnt, in bcm6348_iudma_enable()
[all …]
/openbmc/u-boot/drivers/spi/
H A Dbcm63xx_hsspi.c149 writel_be(set, priv->regs + SPI_PFL_CLK_REG(plat->cs)); in bcm63xx_hsspi_activate_cs()
250 writel_be(val, priv->regs + SPI_PFL_MODE_REG(plat->cs)); in bcm63xx_hsspi_xfer()
274 writel_be(val, priv->regs + SPI_CMD_REG); in bcm63xx_hsspi_xfer()
384 writel_be(0, priv->regs + SPI_IR_MASK_REG); in bcm63xx_hsspi_probe()
387 writel_be(SPI_IR_CLEAR_ALL, priv->regs + SPI_IR_STAT_REG); in bcm63xx_hsspi_probe()
/openbmc/linux/drivers/misc/ocxl/
H A Dmmio.c70 writel_be(val, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_write32()
126 writel_be(tmp, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_set32()
188 writel_be(tmp, (char *)afu->global_mmio_ptr + offset); in ocxl_global_mmio_clear32()
/openbmc/linux/arch/sparc/include/asm/
H A Dio.h19 #define writel_be(__w, __addr) __raw_writel(__w, __addr) macro
/openbmc/linux/drivers/usb/host/
H A Dehci-ps3.c31 writel_be(0x01000020, (void __iomem *)ehci->regs + in ps3_ehci_setup_insnreg()
36 writel_be(0x00000001, (void __iomem *)ehci->regs + in ps3_ehci_setup_insnreg()
H A Dehci.h748 #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) macro
780 writel_be(val, regs) : in ehci_writel()
806 writel_be(hc_control, ehci->ohci_hcctrl_reg); in set_ohci_hcfs()
H A Dohci-ppc-of.c163 writel_be((readl_be(&ohci->regs->control) | in ohci_hcd_ppc_of_probe()
H A Duhci-hcd.h617 writel_be(val, uhci->regs + reg); in uhci_writel()
H A Dohci.h578 writel_be (val, regs) : in _ohci_writel()
/openbmc/u-boot/drivers/phy/
H A Dbcm6358-usbh-phy.c42 writel_be(USBH_TEST_PORT_CTL, priv->regs + USBH_TEST_REG); in bcm6358_usbh_init()
H A Dbcm6348-usbh-phy.c28 writel_be(USBH_SETUP_PORT1_EN, priv->regs); in bcm6348_usbh_init()
/openbmc/linux/arch/microblaze/include/asm/
H A Dio.h44 #define writel_be(v, a) out_be32((__force unsigned *)a, v) macro
/openbmc/linux/arch/powerpc/include/asm/
H A Dio-defs.h14 DEF_PCI_AC_NORET(writel_be, (u32 val, PCI_IO_ADDR addr), (val, addr), mem, addr)
H A Dio.h786 writel_be(val, addr); in iowrite32be()
932 #define mmio_write32be(val, addr) writel_be(val, addr)
/openbmc/linux/arch/mips/include/asm/
H A Dio.h410 #define writel_be(val, addr) \ in BUILDIO_MEM() macro
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dio.h298 #define writel_be(val, addr) \ macro
/openbmc/u-boot/arch/mips/include/asm/
H A Dio.h383 #define writel_be(val, addr) \ in BUILDIO_MEM() macro