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Searched refs:vecbase (Results 1 – 22 of 22) sorted by relevance

/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_sr.S223 test_sr vecbase, 1
225 wsr a2, vecbase
/openbmc/qemu/target/xtensa/core-lx106/
H A Dgdb-config.c.inc64 XTREG( 41,164,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc6247 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
6250 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
6253 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dgdb-config.c.inc203 XTREG(91, 364, 32, 4, 4, 0x02e7, 0x0007, -2, 2, 0x1000, vecbase,
H A Dxtensa-modules.c.inc11404 { "rsr.vecbase", 175 /* xt_iclass_rsr.vecbase */,
11407 { "wsr.vecbase", 176 /* xt_iclass_wsr.vecbase */,
11410 { "xsr.vecbase", 177 /* xt_iclass_xsr.vecbase */,
12427 return 219; /* xsr.vecbase */
12625 return 217; /* rsr.vecbase */
12762 return 218; /* wsr.vecbase */
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dgdb-config.c.inc100 XTREG( 76,304,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc9246 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
9249 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
9252 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dgdb-config.c.inc117 XTREG(92, 368, 32, 4, 4, 0x02e7, 0x0007, -2, 2, 0x1000, vecbase, 0, 0, 0, 0, 0, 0)
H A Dxtensa-modules.c.inc12050 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
12053 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
12056 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
/openbmc/qemu/target/xtensa/
H A Doverlay_tool.h329 .vecbase = XCHAL_VECBASE_RESET_VADDR, \
H A Dcpu.h438 uint32_t vecbase; member
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dgdb-config.c.inc114 XTREG( 79,364,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc27287 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
27290 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
27293 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
/openbmc/qemu/target/xtensa/core-de212/
H A Dgdb-config.c.inc109 XTREG( 85,340,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc11419 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
11422 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
11425 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
/openbmc/qemu/target/xtensa/core-test_kc705_be/
H A Dgdb-config.c.inc146 XTREG(111,492,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc33563 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
33566 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
33569 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dgdb-config.c.inc150 XTREG(111,508,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc16672 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
16675 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
16678 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dgdb-config.c.inc284 XTREG(205,1940,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
H A Dxtensa-modules.c.inc75920 { "rsr.vecbase", ICLASS_xt_iclass_rsr_vecbase,
75923 { "wsr.vecbase", ICLASS_xt_iclass_wsr_vecbase,
75926 { "xsr.vecbase", ICLASS_xt_iclass_xsr_vecbase,
/openbmc/qemu/hw/intc/
H A Darmv7m_nvic.c1087 return cpu->env.v7m.vecbase[attrs.secure]; in nvic_readl()
1605 cpu->env.v7m.vecbase[attrs.secure] = value & 0xffffff80; in nvic_writel()