Searched refs:vc_regs (Results 1 – 2 of 2) sorted by relevance
446 blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, xive->vc_regs[spec_reg]); in pnv_xive2_end_update()447 idx = GETFIELD(VC_ENDC_WATCH_INDEX, xive->vc_regs[spec_reg]); in pnv_xive2_end_update()450 endc_watch[i] = cpu_to_be64(xive->vc_regs[data_reg + i]); in pnv_xive2_end_update()468 blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, xive->vc_regs[spec_reg]); in pnv_xive2_end_cache_load()469 idx = GETFIELD(VC_ENDC_WATCH_INDEX, xive->vc_regs[spec_reg]); in pnv_xive2_end_cache_load()476 xive->vc_regs[data_reg + i] = be64_to_cpu(endc_watch[i]); in pnv_xive2_end_cache_load()894 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); in pnv_xive2_vc_vst_set_data()896 xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]); in pnv_xive2_vc_vst_set_data()1174 xive->vc_regs[VC_ENDC_CFG >> 3]); in pnv_xive2_endc_cache_watch_assign()1175 uint64_t state = xive->vc_regs[VC_ENDC_WATCH_ASSIGN >> 3]; in pnv_xive2_endc_cache_watch_assign()[all …]
137 uint64_t vc_regs[0x100]; member