446     blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, xive->vc_regs[spec_reg]);  in pnv_xive2_end_update()
447     idx = GETFIELD(VC_ENDC_WATCH_INDEX, xive->vc_regs[spec_reg]);  in pnv_xive2_end_update()
450         endc_watch[i] = cpu_to_be64(xive->vc_regs[data_reg + i]);  in pnv_xive2_end_update()
468     blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID, xive->vc_regs[spec_reg]);  in pnv_xive2_end_cache_load()
469     idx = GETFIELD(VC_ENDC_WATCH_INDEX, xive->vc_regs[spec_reg]);  in pnv_xive2_end_cache_load()
476         xive->vc_regs[data_reg + i] = be64_to_cpu(endc_watch[i]);  in pnv_xive2_end_cache_load()
877                             xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]);  in pnv_xive2_vc_vst_set_data()
879                            xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]);  in pnv_xive2_vc_vst_set_data()
1157                                     xive->vc_regs[VC_ENDC_CFG >> 3]);  in pnv_xive2_endc_cache_watch_assign()
1158     uint64_t state = xive->vc_regs[VC_ENDC_WATCH_ASSIGN >> 3];  in pnv_xive2_endc_cache_watch_assign()
1170         xive->vc_regs[VC_ENDC_WATCH_ASSIGN >> 3] = state;  in pnv_xive2_endc_cache_watch_assign()
1178     uint64_t state = xive->vc_regs[VC_ENDC_WATCH_ASSIGN >> 3];  in pnv_xive2_endc_cache_watch_release()
1181     xive->vc_regs[VC_ENDC_WATCH_ASSIGN >> 3] = state;  in pnv_xive2_endc_cache_watch_release()
1198         val = xive->vc_regs[reg];  in pnv_xive2_ic_vc_read()
1205         xive->vc_regs[reg] &= ~VC_ESBC_FLUSH_CTRL_POLL_VALID;  in pnv_xive2_ic_vc_read()
1206         val = xive->vc_regs[reg];  in pnv_xive2_ic_vc_read()
1210         val = xive->vc_regs[reg];  in pnv_xive2_ic_vc_read()
1217         xive->vc_regs[reg] &= ~VC_EASC_FLUSH_CTRL_POLL_VALID;  in pnv_xive2_ic_vc_read()
1218         val = xive->vc_regs[reg];  in pnv_xive2_ic_vc_read()
1226         val = xive->vc_regs[reg];  in pnv_xive2_ic_vc_read()
1237         xive->vc_regs[reg] &= ~(VC_ENDC_WATCH_FULL | VC_ENDC_WATCH_CONFLICT);  in pnv_xive2_ic_vc_read()
1239         val = xive->vc_regs[reg];  in pnv_xive2_ic_vc_read()
1252         val = xive->vc_regs[reg];  in pnv_xive2_ic_vc_read()
1259         val = xive->vc_regs[reg];  in pnv_xive2_ic_vc_read()
1263         xive->vc_regs[reg] &= ~VC_ENDC_FLUSH_CTRL_POLL_VALID;  in pnv_xive2_ic_vc_read()
1264         val = xive->vc_regs[reg];  in pnv_xive2_ic_vc_read()
1271         val = xive->vc_regs[reg];  in pnv_xive2_ic_vc_read()
1275         xive->vc_regs[reg] &= ~VC_AT_MACRO_KILL_VALID;  in pnv_xive2_ic_vc_read()
1276         val = xive->vc_regs[reg];  in pnv_xive2_ic_vc_read()
1283         val = xive->vc_regs[reg];  in pnv_xive2_ic_vc_read()
1321         xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |= VC_ESBC_FLUSH_CTRL_POLL_VALID;  in pnv_xive2_ic_vc_write()
1337         xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |= VC_EASC_FLUSH_CTRL_POLL_VALID;  in pnv_xive2_ic_vc_write()
1369         xive->vc_regs[reg] = val;  in pnv_xive2_ic_vc_write()
1376         xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |= VC_ENDC_FLUSH_CTRL_POLL_VALID;  in pnv_xive2_ic_vc_write()
1407     xive->vc_regs[reg] = val;  in pnv_xive2_ic_vc_write()
2223     xive->vc_regs[VC_ENDC_CFG >> 3] =  in pnv_xive2_reset()