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Searched refs:v_sync_width (Results 1 – 25 of 28) sorted by relevance

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/openbmc/u-boot/drivers/video/
H A Dlogicore_dp_tx.h48 u16 v_sync_width; member
H A Dlogicore_dp_tx.c144 u16 v_sync_width; member
2087 set_reg(dev, REG_MAIN_STREAM_VSWIDTH, msa_config->v_sync_width); in set_msa_values()
2136 dp_tx->main_stream_attributes.v_sync_width = msa->v_sync_width; in logicore_dp_tx_set_msa()
2210 .v_sync_width = 2, in logicore_dp_tx_enable()
2227 .v_sync_width = 2, in logicore_dp_tx_enable()
2244 .v_sync_width = 2, in logicore_dp_tx_enable()
H A Dipu_disp.c832 uint16_t v_sync_width, uint16_t v_end_width, in ipu_init_sync_panel() argument
844 if ((v_sync_width == 0) || (h_sync_width == 0)) in ipu_init_sync_panel()
854 v_total = height + v_sync_width + v_start_width + v_end_width; in ipu_init_sync_panel()
1091 DI_SYNC_INT_HSYNC, 0, v_sync_width * 2); in ipu_init_sync_panel()
1096 v_sync_width + v_start_width, DI_SYNC_HSYNC, in ipu_init_sync_panel()
H A Dipu.h234 uint16_t v_sync_width, uint16_t v_end_width,
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddp_info.h33 unsigned int v_sync_width; member
/openbmc/linux/drivers/video/fbdev/
H A Dacornfb.h67 u_int v_sync_width; member
H A Dacornfb.c129 vidc.v_sync_width = var->vsync_len - 1; in acornfb_set_timing()
130 vidc.v_border_start = vidc.v_sync_width + var->upper_margin; in acornfb_set_timing()
172 vidc_writel(0x91000000 | vidc.v_sync_width); in acornfb_set_timing()
233 printk(KERN_DEBUG " V-sync-width : %d\n", vidc.v_sync_width); in acornfb_set_timing()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c302 v_back_porch = v_blank - timing->v_front_porch - timing->v_sync_width; in get_vertical_back_porch()
347 max(pipes[pipe_cnt].pipe.dest.vblank_nom, timing->v_sync_width + v_back_porch + 2); in dcn314_populate_dml_pipes_from_context_fpu()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce80/
H A Ddce80_timing_generator.c146 if ((timing->v_sync_width + timing->v_front_porch) <= 3) { in dce80_timing_generator_enable_advanced_request()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_optc.c113 timing->v_sync_width < optc1->min_v_sync_width) in optc201_validate_timing()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator_v.c351 timing->v_sync_width, in dce110_timing_generator_v_program_blanking()
392 if ((timing->v_sync_width + timing->v_front_porch) <= 3) { in dce110_timing_generator_v_enable_advanced_request()
H A Ddce110_timing_generator.c318 bp_params.v_sync_width = patched_crtc_timing.v_sync_width; in dce110_timing_generator_program_timing_generator()
1432 if ((timing->v_sync_width + timing->v_front_porch) <= 3) { in dce110_timing_generator_enable_advanced_request()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_timing_generator.c138 if ((timing->v_sync_width + timing->v_front_porch) <= 3) { in dce60_timing_generator_enable_advanced_request()
/openbmc/linux/drivers/gpu/drm/amd/display/include/
H A Dbios_parser_types.h185 uint32_t v_sync_width; member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_hpo_dp_stream_encoder.c422 MSA_DATA_LANE_1, vsp | (hw_crtc_timing.v_sync_width >> 8), in dcn31_hpo_dp_stream_enc_set_stream_attribute()
428 MSA_DATA_LANE_1, hw_crtc_timing.v_sync_width & 0xff, in dcn31_hpo_dp_stream_enc_set_stream_attribute()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_optc.c227 v_sync_end = patched_crtc_timing.v_sync_width; in optc1_program_timing()
629 timing->v_sync_width < optc1->min_v_sync_width) in optc1_validate_timing()
1320 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start; in optc1_get_hw_timing()
H A Ddcn10_stream_encoder.c273 hw_crtc_timing.v_sync_width /= 2; in enc1_stream_encoder_dp_set_stream_attribute()
453 hw_crtc_timing.v_sync_width, in enc1_stream_encoder_dp_set_stream_attribute()
/openbmc/linux/drivers/gpu/drm/msm/dp/
H A Ddp_catalog.c909 u32 v_sync_width; in dp_catalog_panel_tpg_enable() local
930 v_sync_width = drm_mode->vsync_end - drm_mode->vsync_start; in dp_catalog_panel_tpg_enable()
941 dp_write_p0(catalog, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * in dp_catalog_panel_tpg_enable()
/openbmc/u-boot/drivers/video/exynos/
H A Dexynos_dp.c33 disp_info->v_total = disp_info->v_res + disp_info->v_sync_width + in exynos_dp_disp_info()
901 priv->disp_info.v_sync_width = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
H A Dexynos_dp_lowlevel.c1078 writel(priv->disp_info.v_sync_width, &dp_regs->vsw_cfg); in exynos_dp_config_video_bist()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h932 uint32_t v_sync_width; member
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.c294 hw_crtc_timing.v_sync_width /= 2; in dce110_stream_encoder_dp_set_stream_attribute()
490 hw_crtc_timing.v_sync_width, in dce110_stream_encoder_dp_set_stream_attribute()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/bios/
H A Dcommand_table2.c601 params.v_syncwidth = cpu_to_le16((uint16_t)bp_params->v_sync_width); in set_crtc_using_dtd_timing_v3()
H A Dcommand_table.c1844 cpu_to_le16((uint16_t)(bp_params->v_sync_width)); in set_crtc_timing_v1()
1929 params.usV_SyncWidth = cpu_to_le16((uint16_t)bp_params->v_sync_width); in set_crtc_using_dtd_timing_v3()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce120/
H A Ddce120_timing_generator.c122 timing->v_sync_width < tg110->min_v_sync_width) in dce120_timing_generator_validate_timing()

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