Searched refs:update_value (Results 1 – 2 of 2) sorted by relevance
144 u32 update_value, io48_value, ddrioctl; in sdram_mmr_init_full() local244 update_value = hmc_readl(NIOSRESERVED0); in sdram_mmr_init_full()245 hmc_ecc_writel(((update_value & 0xFF) >> 5), DDRIOCTRL); in sdram_mmr_init_full()258 update_value = match_ddr_conf(io48_value); in sdram_mmr_init_full()259 if (update_value) in sdram_mmr_init_full()260 ddr_sch_writel(update_value, DDR_SCH_DDRCONF); in sdram_mmr_init_full()276 update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) + in sdram_mmr_init_full()289 (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) | in sdram_mmr_init_full()
246 u32 update_value, io48_value; in sdram_mmr_init() local273 update_value = readl(&socfpga_io48_mmr_base->niosreserve0); in sdram_mmr_init()274 writel(((update_value & 0xFF) >> 5), in sdram_mmr_init()297 update_value = match_ddr_conf(io48_value); in sdram_mmr_init()298 if (update_value) in sdram_mmr_init()299 writel(update_value, in sdram_mmr_init()358 update_value = (caltim2_cfg_rd_to_pch + caltim4_cfg_pch_to_valid + in sdram_mmr_init()371 (update_value << in sdram_mmr_init()