Searched refs:ucNumDPMLevels (Results 1 – 11 of 11) sorted by relevance
428 UCHAR ucNumDPMLevels; member435 UCHAR clockInfoIndex[] __counted_by(ucNumDPMLevels);
2714 kcalloc(power_state->v2.ucNumDPMLevels ? in radeon_atombios_parse_power_table_6()2715 power_state->v2.ucNumDPMLevels : 1, in radeon_atombios_parse_power_table_6()2720 if (power_state->v2.ucNumDPMLevels) { in radeon_atombios_parse_power_table_6()2721 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in radeon_atombios_parse_power_table_6()2744 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in radeon_atombios_parse_power_table_6()
1741 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in trinity_parse_power_table()1758 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in trinity_parse_power_table()
1508 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in sumo_parse_power_table()1524 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in sumo_parse_power_table()
2483 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in kv_parse_power_table()2500 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in kv_parse_power_table()
5565 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in ci_parse_power_table()5579 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in ci_parse_power_table()
6845 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in si_parse_power_table()6859 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in si_parse_power_table()
469 UCHAR ucNumDPMLevels; member
786 size_of_entry_v2(pstate->ucNumDPMLevels)); in get_state_entry_v2()926 for (i = 0; i < pstate_entry_v2->ucNumDPMLevels; i++) { in pp_tables_get_entry()
2745 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in kv_parse_power_table()2762 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in kv_parse_power_table()
7315 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { in si_parse_power_table()7329 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; in si_parse_power_table()