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Searched refs:timer (Results 1 – 25 of 750) sorted by relevance

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/openbmc/qemu/net/
H A Dannounce.c20 int64_t qemu_announce_timer_step(AnnounceTimer *timer) in qemu_announce_timer_step() argument
24 step = timer->params.initial + in qemu_announce_timer_step()
25 (timer->params.rounds - timer->round - 1) * in qemu_announce_timer_step()
26 timer->params.step; in qemu_announce_timer_step()
28 if (step < 0 || step > timer->params.max) { in qemu_announce_timer_step()
29 step = timer->params.max; in qemu_announce_timer_step()
31 timer_mod(timer->tm, qemu_clock_get_ms(timer->type) + step); in qemu_announce_timer_step()
40 void qemu_announce_timer_del(AnnounceTimer *timer, bool free_named) in qemu_announce_timer_del() argument
43 if (timer->tm) { in qemu_announce_timer_del()
44 timer_free(timer->tm); in qemu_announce_timer_del()
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/openbmc/qemu/hw/sparc64/
H A Dsparc64.c85 CPUTimer *timer = g_new0(CPUTimer, 1); in cpu_timer_create() local
87 timer->name = name; in cpu_timer_create()
88 timer->frequency = frequency; in cpu_timer_create()
89 timer->disabled_mask = disabled_mask; in cpu_timer_create()
90 timer->npt_mask = npt_mask; in cpu_timer_create()
92 timer->disabled = 1; in cpu_timer_create()
93 timer->npt = 1; in cpu_timer_create()
94 timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); in cpu_timer_create()
96 timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu); in cpu_timer_create()
98 return timer; in cpu_timer_create()
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/openbmc/sdeventplus/test/utility/
H A Dtimer.cpp63 std::unique_ptr<TestTimer> timer; member in sdeventplus::utility::__anon9ead1e020111::TimerTest
98 if (timer) in resetTimer()
100 timer.reset(); in resetTimer()
111 EXPECT_TRUE(timer->hasExpired()); in expireTimer()
112 EXPECT_EQ(interval, timer->getInterval()); in expireTimer()
151 timer = std::make_unique<TestTimer>(*event, runCallback, interval); in SetUp()
152 EXPECT_EQ(expected_event, timer->get_event().get()); in SetUp()
175 timer = std::make_unique<TestTimer>(*event, nullptr, interval); in TEST_F()
193 timer = std::make_unique<TestTimer>(*event, nullptr); in TEST_F()
195 EXPECT_EQ(std::nullopt, timer->getInterval()); in TEST_F()
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/openbmc/qemu/hw/timer/
H A Dgrlib_gptimer.c95 static void grlib_gptimer_tx_begin(GPTimer *timer) in grlib_gptimer_tx_begin() argument
97 ptimer_transaction_begin(timer->ptimer); in grlib_gptimer_tx_begin()
100 static void grlib_gptimer_tx_commit(GPTimer *timer) in grlib_gptimer_tx_commit() argument
102 ptimer_transaction_commit(timer->ptimer); in grlib_gptimer_tx_commit()
106 static void grlib_gptimer_enable(GPTimer *timer) in grlib_gptimer_enable() argument
108 assert(timer != NULL); in grlib_gptimer_enable()
111 ptimer_stop(timer->ptimer); in grlib_gptimer_enable()
113 if (!(timer->config & GPTIMER_ENABLE)) { in grlib_gptimer_enable()
115 trace_grlib_gptimer_disabled(timer->id, timer->config); in grlib_gptimer_enable()
122 trace_grlib_gptimer_enable(timer->id, timer->counter); in grlib_gptimer_enable()
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H A Darm_mptimer.c68 static inline void timerblock_set_count(struct ptimer_state *timer, in timerblock_set_count() argument
75 *count = ptimer_get_limit(timer); in timerblock_set_count()
77 ptimer_set_count(timer, *count); in timerblock_set_count()
81 static inline void timerblock_run(struct ptimer_state *timer, in timerblock_run() argument
85 ptimer_run(timer, !(control & 2)); in timerblock_run()
96 ptimer_get_limit(tb->timer) == 0) { in timerblock_tick()
97 ptimer_stop(tb->timer); in timerblock_tick()
109 return ptimer_get_limit(tb->timer); in timerblock_read()
111 return ptimer_get_count(tb->timer); in timerblock_read()
128 ptimer_transaction_begin(tb->timer); in timerblock_write()
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H A Dcmsdk-apb-timer.c86 r = ptimer_get_count(s->timer); in cmsdk_apb_timer_read()
89 r = ptimer_get_limit(s->timer); in cmsdk_apb_timer_read()
124 ptimer_transaction_begin(s->timer); in cmsdk_apb_timer_write()
126 ptimer_run(s->timer, ptimer_get_limit(s->timer) == 0); in cmsdk_apb_timer_write()
128 ptimer_stop(s->timer); in cmsdk_apb_timer_write()
130 ptimer_transaction_commit(s->timer); in cmsdk_apb_timer_write()
134 ptimer_transaction_begin(s->timer); in cmsdk_apb_timer_write()
136 ptimer_stop(s->timer); in cmsdk_apb_timer_write()
138 ptimer_set_limit(s->timer, value, 1); in cmsdk_apb_timer_write()
144 ptimer_run(s->timer, 0); in cmsdk_apb_timer_write()
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H A Dexynos4210_pwm.c117 Exynos4210PWM timer[EXYNOS4210_PWM_TIMERS_NUM]; member
144 VMSTATE_STRUCT_ARRAY(timer, Exynos4210PWMState,
159 freq = s->timer[id].freq; in exynos4210_pwm_update_freq()
161 s->timer[id].freq = 24000000 / in exynos4210_pwm_update_freq()
165 s->timer[id].freq = 24000000 / in exynos4210_pwm_update_freq()
170 if (freq != s->timer[id].freq) { in exynos4210_pwm_update_freq()
171 ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq); in exynos4210_pwm_update_freq()
172 DPRINTF("freq=%uHz\n", s->timer[id].freq); in exynos4210_pwm_update_freq()
194 qemu_irq_raise(p->timer[id].irq); in exynos4210_pwm_tick()
206 p->timer[id].reg_tcntb); in exynos4210_pwm_tick()
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H A Dhpet.c82 HPETTimer timer[HPET_MAX_TIMERS]; member
97 static uint32_t timer_int_route(struct HPETTimer *timer) in timer_int_route() argument
99 return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT; in timer_int_route()
187 static void update_irq(struct HPETTimer *timer, int set) in update_irq() argument
193 if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) { in update_irq()
198 route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ; in update_irq()
200 route = timer_int_route(timer); in update_irq()
202 s = timer->state; in update_irq()
203 mask = 1 << timer->tn; in update_irq()
205 if (set && (timer->config & HPET_TN_TYPE_LEVEL)) { in update_irq()
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H A Darm_timer.c33 ptimer_state *timer; member
62 return ptimer_get_count(s->timer); in arm_timer_read()
96 ptimer_set_limit(s->timer, limit, reload); in arm_timer_recalibrate()
108 ptimer_transaction_begin(s->timer); in arm_timer_write()
110 ptimer_transaction_commit(s->timer); in arm_timer_write()
117 ptimer_transaction_begin(s->timer); in arm_timer_write()
122 ptimer_stop(s->timer); in arm_timer_write()
132 ptimer_set_freq(s->timer, freq); in arm_timer_write()
135 ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0); in arm_timer_write()
137 ptimer_transaction_commit(s->timer); in arm_timer_write()
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H A Dsh_timer.c37 ptimer_state *timer; member
71 return ptimer_get_count(s->timer); in sh_timer_read()
92 ptimer_transaction_begin(s->timer); in sh_timer_write()
93 ptimer_set_limit(s->timer, s->tcor, 0); in sh_timer_write()
94 ptimer_transaction_commit(s->timer); in sh_timer_write()
98 ptimer_transaction_begin(s->timer); in sh_timer_write()
99 ptimer_set_count(s->timer, s->tcnt); in sh_timer_write()
100 ptimer_transaction_commit(s->timer); in sh_timer_write()
103 ptimer_transaction_begin(s->timer); in sh_timer_write()
109 ptimer_stop(s->timer); in sh_timer_write()
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H A Dcmsdk-apb-dualtimer.c131 ptimer_transaction_begin(m->timer); in cmsdk_dualtimermod_write_control()
139 ptimer_stop(m->timer); in cmsdk_dualtimermod_write_control()
165 ptimer_set_period_from_clock(m->timer, m->parent->timclk, divisor); in cmsdk_dualtimermod_write_control()
175 load = ptimer_get_limit(m->timer); in cmsdk_dualtimermod_write_control()
185 ptimer_set_limit(m->timer, load, 0); in cmsdk_dualtimermod_write_control()
192 value = ptimer_get_count(m->timer); in cmsdk_dualtimermod_write_control()
193 load = ptimer_get_limit(m->timer); in cmsdk_dualtimermod_write_control()
219 ptimer_set_count(m->timer, value); in cmsdk_dualtimermod_write_control()
220 ptimer_set_limit(m->timer, load, 0); in cmsdk_dualtimermod_write_control()
230 ptimer_run(m->timer, !!(newctrl & R_CONTROL_ONESHOT_MASK)); in cmsdk_dualtimermod_write_control()
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H A Dslavio_timer.c55 ptimer_state *timer; member
116 count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer)); in slavio_timer_get_out()
215 ptimer_transaction_begin(t->timer); in slavio_timer_mem_writel()
225 ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); in slavio_timer_mem_writel()
231 ptimer_set_limit(t->timer, in slavio_timer_mem_writel()
234 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1); in slavio_timer_mem_writel()
237 ptimer_transaction_commit(t->timer); in slavio_timer_mem_writel()
249 ptimer_transaction_begin(t->timer); in slavio_timer_mem_writel()
250 ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count)); in slavio_timer_mem_writel()
251 ptimer_transaction_commit(t->timer); in slavio_timer_mem_writel()
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H A Dtrace-events9 slavio_timer_mem_writel_limit(unsigned int timer_index, uint64_t count) "processor %d user timer se…
10 slavio_timer_mem_writel_counter_invalid(void) "not user timer"
11 slavio_timer_mem_writel_status_start(unsigned int timer_index) "processor %d user timer started"
12 slavio_timer_mem_writel_status_stop(unsigned int timer_index) "processor %d user timer stopped"
13 …er_mem_writel_mode_user(unsigned int timer_index) "processor %d changed from counter to user timer"
14 …mem_writel_mode_counter(unsigned int timer_index) "processor %d changed from user timer to counter"
15 slavio_timer_mem_writel_mode_invalid(void) "not system timer"
19 grlib_gptimer_enable(int id, uint32_t count) "timer:%d set count 0x%x and run"
20 grlib_gptimer_disabled(int id, uint32_t config) "timer:%d Timer disable config 0x%x"
21 grlib_gptimer_restart(int id, uint32_t reload) "timer:%d reload val: 0x%x"
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H A Dimx_gpt.c69 VMSTATE_PTIMER(timer, IMXGPTState),
151 ptimer_set_freq(s->timer, s->freq); in imx_gpt_set_freq()
166 s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer); in imx_gpt_update_count()
259 ptimer_set_limit(s->timer, limit, 1); in imx_gpt_compute_next_timeout()
328 ptimer_transaction_begin(s->timer); in imx_gpt_reset_common()
330 ptimer_stop(s->timer); in imx_gpt_reset_common()
360 ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); in imx_gpt_reset_common()
364 ptimer_run(s->timer, 1); in imx_gpt_reset_common()
366 ptimer_transaction_commit(s->timer); in imx_gpt_reset_common()
398 ptimer_transaction_begin(s->timer); in imx_gpt_write()
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/openbmc/qemu/target/arm/
H A Dtrace-events4 arm_gt_recalc(int timer, uint64_t nexttick) "gt recalc: timer %d next tick 0x%" PRIx64
5 arm_gt_recalc_disabled(int timer) "gt recalc: timer %d timer disabled"
6 arm_gt_cval_write(int timer, uint64_t value) "gt_cval_write: timer %d value 0x%" PRIx64
7 arm_gt_tval_write(int timer, uint64_t value) "gt_tval_write: timer %d value 0x%" PRIx64
8 arm_gt_ctl_write(int timer, uint64_t value) "gt_ctl_write: timer %d value 0x%" PRIx64
9 arm_gt_imask_toggle(int timer) "gt_ctl_write: timer %d IMASK toggle"
12 arm_gt_update_irq(int timer, int irqstate) "gt_update_irq: timer %d irqstate %d"
/openbmc/u-boot/drivers/timer/
H A DKconfig4 bool "Enable driver model for timer drivers"
7 Enable driver model for timer access. It uses the same API as
8 lib/time.c, but now implemented by the uclass. The first timer
9 will be used. The timer is usually a 32 bits free-running up
10 counter. There may be no real tick, and no timer interrupt.
13 bool "Enable driver model for timer drivers in SPL"
16 Enable support for timer drivers in SPL. These can be used to get
17 a timer value when in SPL, or perhaps for implementing a delay
18 function. This enables the drivers in drivers/timer as part of an
22 bool "Enable driver model for timer drivers in TPL"
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H A Drockchip_timer.c25 struct rk_timer *timer; member
28 static inline int64_t rockchip_timer_get_curr_value(struct rk_timer *timer) in rockchip_timer_get_curr_value() argument
33 timebase_l = readl(&timer->timer_curr_value0); in rockchip_timer_get_curr_value()
34 timebase_h = readl(&timer->timer_curr_value1); in rockchip_timer_get_curr_value()
52 rate = timer_get_rate(gd->timer); in timer_get_boot_us()
53 timer_get_count(gd->timer, &ticks); in timer_get_boot_us()
58 struct rk_timer *timer = NULL; in timer_get_boot_us() local
70 timer = (struct rk_timer *)ofnode_get_addr(node); in timer_get_boot_us()
73 ticks = ~0uLL - rockchip_timer_get_curr_value(timer); in timer_get_boot_us()
91 uint64_t cntr = rockchip_timer_get_curr_value(priv->timer); in rockchip_timer_get_count()
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/openbmc/u-boot/arch/arm/cpu/arm920t/ep93xx/
H A Dtimer.c30 } timer; variable
45 if (now >= timer.last_read) in read_timer()
46 timer.ticks += now - timer.last_read; in read_timer()
49 timer.ticks += TIMER_MAX_VAL - timer.last_read + now; in read_timer()
51 timer.last_read = now; in read_timer()
63 sys_ticks = timer.ticks * CONFIG_SYS_HZ; in get_ticks()
80 target = timer.ticks + usecs_to_ticks(usec); in __udelay()
82 while (timer.ticks < target) in __udelay()
102 timer.ticks = 0; in timer_init()
/openbmc/qemu/hw/watchdog/
H A Dcmsdk-apb-watchdog.c128 r = ptimer_get_limit(s->timer); in cmsdk_apb_watchdog_read()
131 r = ptimer_get_count(s->timer); in cmsdk_apb_watchdog_read()
200 ptimer_transaction_begin(s->timer); in cmsdk_apb_watchdog_write()
201 ptimer_set_limit(s->timer, value, 1); in cmsdk_apb_watchdog_write()
202 ptimer_transaction_commit(s->timer); in cmsdk_apb_watchdog_write()
216 ptimer_transaction_begin(s->timer); in cmsdk_apb_watchdog_write()
223 ptimer_set_count(s->timer, ptimer_get_limit(s->timer)); in cmsdk_apb_watchdog_write()
224 ptimer_run(s->timer, 0); in cmsdk_apb_watchdog_write()
227 ptimer_stop(s->timer); in cmsdk_apb_watchdog_write()
229 ptimer_transaction_commit(s->timer); in cmsdk_apb_watchdog_write()
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/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Dtimer.c24 static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq) in lpc32xx_timer_reset() argument
26 writel(TIMER_TCR_COUNTER_RESET, &timer->tcr); in lpc32xx_timer_reset()
27 writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr); in lpc32xx_timer_reset()
28 writel(0, &timer->tc); in lpc32xx_timer_reset()
29 writel(0, &timer->pr); in lpc32xx_timer_reset()
32 writel(TIMER_CTCR_MODE_TIMER, &timer->ctcr); in lpc32xx_timer_reset()
35 writel((get_periph_clk_rate() / freq) - 1, &timer->pr); in lpc32xx_timer_reset()
38 static void lpc32xx_timer_count(struct timer_regs *timer, int enable) in lpc32xx_timer_count() argument
41 writel(TIMER_TCR_COUNTER_ENABLE, &timer->tcr); in lpc32xx_timer_count()
43 writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr); in lpc32xx_timer_count()
/openbmc/u-boot/arch/arm/mach-rmobile/
H A Dtimer.c20 u64 timer; in get_cpu_global_timer() local
32 timer = high; in get_cpu_global_timer()
33 return (u64)((timer << 32) | low); in get_cpu_global_timer()
38 u64 timer = get_cpu_global_timer(); in get_time_us() local
40 timer = ((timer << 2) + (CLK2MHZ(CONFIG_SYS_CPU_CLK) >> 1)); in get_time_us()
41 do_div(timer, CLK2MHZ(CONFIG_SYS_CPU_CLK)); in get_time_us()
42 return timer; in get_time_us()
/openbmc/u-boot/doc/device-tree-bindings/timer/
H A Darc_timer.txt5 - compatible : should be "snps,arc-timer".
6 - reg : Specifies timer ID, could be either 0 or 1.
11 timer@0 {
12 compatible = "snps,arc-timer";
17 timer@1 {
18 compatible = "snps,arc-timer";
24 as each timer is driven by the same core clock.
H A Datcpit100_timer.txt1 Andestech ATCPIT100 timer
6 This timer is a set of compact multi-function timers, which can be
10 multi-function timer and provide the following usage scenarios:
11 One 32-bit timer
15 One 16-bit timer and one 8-bit PWM
16 Two 8-bit timer and one 8-bit PWM
21 - interrupts : Reference to the timer interrupt
22 - clock-frequency : The rate in HZ in input of the Andestech ATCPIT100 timer
26 timer0: timer@f0400000 {
/openbmc/qemu/scripts/qemugdb/
H A Dtimers.py25 def dump_timers(self, timer): argument
29 timer['expire_time'],
30 timer['scale'],
31 timer['cb'],
32 timer['opaque']))
34 if int(timer['next']) > 0:
35 self.dump_timers(timer['next'])
/openbmc/u-boot/drivers/watchdog/
H A DKconfig52 bool "Enable driver model for watchdog timer drivers"
55 Enable driver model for watchdog timer. At the moment the API
58 What exactly happens when the timer expires is up to a particular
70 bool "Marvell Armada 37xx watchdog timer support"
79 bool "Aspeed ast2400/ast2500 watchdog timer support"
83 Select this to enable watchdog timer for Aspeed ast2500/ast2400 devices.
84 The watchdog timer is stopped when initialized. It performs reset, either
90 bool "BCM6345 watchdog timer support"
93 Select this to enable watchdog timer for BCM6345 SoCs.
94 The watchdog timer is stopped when initialized.
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