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Searched refs:tcr (Results 1 – 25 of 107) sorted by relevance

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/openbmc/linux/Documentation/misc-devices/
H A Doxsemi-tornado.rst45 (tcr), the clock prescaler (cpr) and the divisor (div) produced by the
50 r: 15625000, a: 15625000.00, d: 0.0000%, tcr: 4, cpr: 1.000, div: 1
51 r: 12500000, a: 12500000.00, d: 0.0000%, tcr: 5, cpr: 1.000, div: 1
52 r: 10416666, a: 10416666.67, d: 0.0000%, tcr: 6, cpr: 1.000, div: 1
53 r: 8928571, a: 8928571.43, d: 0.0000%, tcr: 7, cpr: 1.000, div: 1
54 r: 7812500, a: 7812500.00, d: 0.0000%, tcr: 8, cpr: 1.000, div: 1
55 r: 4000000, a: 4000000.00, d: 0.0000%, tcr: 5, cpr: 3.125, div: 1
56 r: 3686400, a: 3676470.59, d: -0.2694%, tcr: 8, cpr: 2.125, div: 1
57 r: 3500000, a: 3496503.50, d: -0.0999%, tcr: 13, cpr: 1.375, div: 1
58 r: 3000000, a: 2976190.48, d: -0.7937%, tcr: 14, cpr: 1.500, div: 1
[all …]
/openbmc/linux/drivers/clocksource/
H A Dtimer-davinci.c87 unsigned int tcr; in davinci_tim12_shutdown() local
89 tcr = DAVINCI_TIMER_ENAMODE_DISABLED << in davinci_tim12_shutdown()
96 tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC << in davinci_tim12_shutdown()
104 unsigned int tcr; in davinci_tim12_set_oneshot() local
106 tcr = DAVINCI_TIMER_ENAMODE_ONESHOT << in davinci_tim12_set_oneshot()
109 tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC << in davinci_tim12_set_oneshot()
198 int tcr; in davinci_clocksource_init_tim34() local
200 tcr = DAVINCI_TIMER_ENAMODE_PERIODIC << in davinci_clocksource_init_tim34()
202 tcr |= DAVINCI_TIMER_ENAMODE_ONESHOT << in davinci_clocksource_init_tim34()
217 unsigned int tcr; in davinci_clocksource_init_tim12() local
[all …]
H A Dtimer-keystone.c76 u32 tcr; in keystone_timer_config() local
79 tcr = keystone_timer_readl(TCR); in keystone_timer_config()
80 off = tcr & ~(TCR_ENAMODE_MASK); in keystone_timer_config()
83 tcr |= mask; in keystone_timer_config()
102 keystone_timer_writel(tcr, TCR); in keystone_timer_config()
108 u32 tcr; in keystone_timer_disable() local
110 tcr = keystone_timer_readl(TCR); in keystone_timer_disable()
113 tcr &= ~(TCR_ENAMODE_MASK); in keystone_timer_disable()
114 keystone_timer_writel(tcr, TCR); in keystone_timer_disable()
/openbmc/linux/include/linux/fsl/bestcomm/
H A Dbestcomm_priv.h264 reg = in_be16(&bcom_eng->regs->tcr[task]); in bcom_enable_task()
265 out_be16(&bcom_eng->regs->tcr[task], reg | TASK_ENABLE); in bcom_enable_task()
271 u16 reg = in_be16(&bcom_eng->regs->tcr[task]); in bcom_disable_task()
272 out_be16(&bcom_eng->regs->tcr[task], reg & ~TASK_ENABLE); in bcom_disable_task()
337 u16 __iomem *tcr = &bcom_eng->regs->tcr[task]; in bcom_set_task_auto_start() local
338 out_be16(tcr, (in_be16(tcr) & ~0xff) | 0x00c0 | next_task); in bcom_set_task_auto_start()
344 u16 __iomem *tcr = &bcom_eng->regs->tcr[task]; in bcom_set_tcr_initiator() local
345 out_be16(tcr, (in_be16(tcr) & ~0x1f00) | ((initiator & 0x1f) << 8)); in bcom_set_tcr_initiator()
/openbmc/linux/drivers/tty/serial/8250/
H A D8250_dwlib.c183 u32 tcr; in dw8250_rs485_config() local
185 tcr = dw8250_readl_ext(p, DW_UART_TCR); in dw8250_rs485_config()
186 tcr &= ~DW_UART_TCR_XFER_MODE; in dw8250_rs485_config()
189 tcr |= DW_UART_TCR_RS485_EN; in dw8250_rs485_config()
194 tcr |= DW_UART_TCR_XFER_MODE_DE_OR_RE; in dw8250_rs485_config()
201 tcr &= ~DW_UART_TCR_RS485_EN; in dw8250_rs485_config()
205 tcr |= DW_UART_TCR_DE_POL; in dw8250_rs485_config()
206 tcr &= ~DW_UART_TCR_RE_POL; in dw8250_rs485_config()
209 tcr &= ~DW_UART_TCR_DE_POL; in dw8250_rs485_config()
211 tcr |= DW_UART_TCR_RE_POL; in dw8250_rs485_config()
[all …]
/openbmc/linux/arch/arm/mach-rpc/
H A Ddma.c207 int tcr, speed; in iomd_set_dma_speed() local
218 tcr = iomd_readb(IOMD_DMATCR); in iomd_set_dma_speed()
223 tcr = (tcr & ~0x03) | speed; in iomd_set_dma_speed()
227 tcr = (tcr & ~0x0c) | (speed << 2); in iomd_set_dma_speed()
231 tcr = (tcr & ~0x30) | (speed << 4); in iomd_set_dma_speed()
235 tcr = (tcr & ~0xc0) | (speed << 6); in iomd_set_dma_speed()
242 iomd_writeb(tcr, IOMD_DMATCR); in iomd_set_dma_speed()
/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Dtimer.c26 writel(TIMER_TCR_COUNTER_RESET, &timer->tcr); in lpc32xx_timer_reset()
27 writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr); in lpc32xx_timer_reset()
41 writel(TIMER_TCR_COUNTER_ENABLE, &timer->tcr); in lpc32xx_timer_count()
43 writel(TIMER_TCR_COUNTER_DISABLE, &timer->tcr); in lpc32xx_timer_count()
/openbmc/u-boot/arch/arm/include/asm/armv8/
H A Dmmu.h106 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) in set_ttbr_tcr_mair() argument
111 asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory"); in set_ttbr_tcr_mair()
115 asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory"); in set_ttbr_tcr_mair()
119 asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory"); in set_ttbr_tcr_mair()
/openbmc/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu.h355 u32 tcr[2]; member
386 u32 tcr = FIELD_PREP(ARM_SMMU_TCR_TG0, cfg->arm_lpae_s1_cfg.tcr.tg) | in arm_smmu_lpae_tcr() local
387 FIELD_PREP(ARM_SMMU_TCR_SH0, cfg->arm_lpae_s1_cfg.tcr.sh) | in arm_smmu_lpae_tcr()
388 FIELD_PREP(ARM_SMMU_TCR_ORGN0, cfg->arm_lpae_s1_cfg.tcr.orgn) | in arm_smmu_lpae_tcr()
389 FIELD_PREP(ARM_SMMU_TCR_IRGN0, cfg->arm_lpae_s1_cfg.tcr.irgn) | in arm_smmu_lpae_tcr()
390 FIELD_PREP(ARM_SMMU_TCR_T0SZ, cfg->arm_lpae_s1_cfg.tcr.tsz); in arm_smmu_lpae_tcr()
397 tcr = (tcr << 16) & ~ARM_SMMU_TCR_A1; in arm_smmu_lpae_tcr()
398 tcr |= ARM_SMMU_TCR_EPD0; in arm_smmu_lpae_tcr()
400 tcr |= ARM_SMMU_TCR_EPD1; in arm_smmu_lpae_tcr()
402 return tcr; in arm_smmu_lpae_tcr()
[all …]
H A Darm-smmu-qcom.c145 if (cb->tcr[0] & ARM_SMMU_TCR_EPD1) in qcom_adreno_smmu_set_ttbr0_cfg()
151 if ((cb->tcr[0] & ARM_SMMU_TCR_EPD0)) in qcom_adreno_smmu_set_ttbr0_cfg()
155 cb->tcr[0] = arm_smmu_lpae_tcr(&pgtable->cfg); in qcom_adreno_smmu_set_ttbr0_cfg()
158 u32 tcr = cb->tcr[0]; in qcom_adreno_smmu_set_ttbr0_cfg() local
161 if (!(cb->tcr[0] & ARM_SMMU_TCR_EPD0)) in qcom_adreno_smmu_set_ttbr0_cfg()
164 tcr |= arm_smmu_lpae_tcr(pgtbl_cfg); in qcom_adreno_smmu_set_ttbr0_cfg()
165 tcr &= ~(ARM_SMMU_TCR_EPD0 | ARM_SMMU_TCR_EPD1); in qcom_adreno_smmu_set_ttbr0_cfg()
167 cb->tcr[0] = tcr; in qcom_adreno_smmu_set_ttbr0_cfg()
/openbmc/linux/arch/mips/kernel/
H A Dcevt-txx9.c63 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9_clocksource_init()
68 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9_clocksource_init()
83 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9tmr_stop_and_clear()
100 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9tmr_set_state_periodic()
148 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9tmr_set_next_event()
211 __raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9_tmr_init()
213 __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr); in txx9_tmr_init()
/openbmc/u-boot/arch/arm/mach-davinci/
H A Dtimer.c40 writel(0x0, &timer->tcr); in timer_init()
45 writel(2 << 22, &timer->tcr); in timer_init()
107 writel(0x0, &wdttimer->tcr); in davinci_hw_watchdog_enable()
113 writel(2 << 22, &wdttimer->tcr); in davinci_hw_watchdog_enable()
H A Dreset.c24 writel(readl(&wdttimer->tcr) | 0x40, &wdttimer->tcr); in reset_cpu()
/openbmc/qemu/hw/timer/
H A Drenesas_tmr.c209 FIELD_EX8(tmr->tcr[ch], TCR, CCLR)); in tmr_read()
211 FIELD_EX8(tmr->tcr[ch], TCR, OVIE)); in tmr_read()
213 FIELD_EX8(tmr->tcr[ch], TCR, CMIEA)); in tmr_read()
215 FIELD_EX8(tmr->tcr[ch], TCR, CMIEB)); in tmr_read()
290 tmr->tcr[ch] = val; in tmr_write()
341 if (FIELD_EX8(tmr->tcr[ch], TCR, CCLR) == CCLR_A) { in issue_event()
344 if (FIELD_EX8(tmr->tcr[ch], TCR, CMIEA)) { in issue_event()
356 if (FIELD_EX8(tmr->tcr[ch], TCR, CCLR) == CCLR_B) { in issue_event()
359 if (FIELD_EX8(tmr->tcr[ch], TCR, CMIEB)) { in issue_event()
416 tmr->tcr[0] = tmr->tcr[1] = 0x00; in rtmr_reset()
[all …]
/openbmc/linux/arch/arm64/include/asm/
H A Dmmu_context.h75 unsigned long tcr = read_sysreg(tcr_el1); in __cpu_set_tcr_t0sz() local
77 if ((tcr & TCR_T0SZ_MASK) >> TCR_T0SZ_OFFSET == t0sz) in __cpu_set_tcr_t0sz()
80 tcr &= ~TCR_T0SZ_MASK; in __cpu_set_tcr_t0sz()
81 tcr |= t0sz << TCR_T0SZ_OFFSET; in __cpu_set_tcr_t0sz()
82 write_sysreg(tcr, tcr_el1); in __cpu_set_tcr_t0sz()
/openbmc/linux/arch/arm64/mm/
H A Dproc.S422 tcr .req x16
424 mov_q tcr, TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
428 tcr_clear_errata_bits tcr, x9, x5
433 tcr_set_t1sz tcr, x9
437 tcr_set_t0sz tcr, x9
442 tcr_compute_pa_size tcr, #TCR_IPS_SHIFT, x5, x6
452 orr tcr, tcr, #TCR_HA // hardware Access flag update
456 msr tcr_el1, tcr
479 .unreq tcr
/openbmc/linux/drivers/iommu/
H A Dio-pgtable-arm.c801 typeof(&cfg->arm_lpae_s1_cfg.tcr) tcr = &cfg->arm_lpae_s1_cfg.tcr; in arm_64_lpae_alloc_pgtable_s1()
815 tcr->sh = ARM_LPAE_TCR_SH_IS; in arm_64_lpae_alloc_pgtable_s1()
816 tcr->irgn = ARM_LPAE_TCR_RGN_WBWA; in arm_64_lpae_alloc_pgtable_s1()
817 tcr->orgn = ARM_LPAE_TCR_RGN_WBWA; in arm_64_lpae_alloc_pgtable_s1()
821 tcr->sh = ARM_LPAE_TCR_SH_OS; in arm_64_lpae_alloc_pgtable_s1()
822 tcr->irgn = ARM_LPAE_TCR_RGN_NC; in arm_64_lpae_alloc_pgtable_s1()
824 tcr->orgn = ARM_LPAE_TCR_RGN_NC; in arm_64_lpae_alloc_pgtable_s1()
844 tcr->ips = ARM_LPAE_TCR_PS_32_BIT; in arm_64_lpae_alloc_pgtable_s1()
847 tcr->ips = ARM_LPAE_TCR_PS_36_BIT; in arm_64_lpae_alloc_pgtable_s1()
850 tcr->ips = ARM_LPAE_TCR_PS_40_BIT; in arm_64_lpae_alloc_pgtable_s1()
[all …]
/openbmc/qemu/hw/net/
H A Dsmc91c111.c35 uint16_t tcr; member
66 VMSTATE_UINT16(tcr, smc91c111_state),
228 if ((s->tcr & TCR_TXEN) == 0) in smc91c111_do_tx()
246 if (len < 64 && (s->tcr & TCR_PAD_EN)) { in smc91c111_do_tx()
258 add_crc = (control & 0x10) || (s->tcr & TCR_NOCRC) == 0; in smc91c111_do_tx()
299 s->tcr = 0; in smc91c111_reset()
329 SET_LOW(tcr, value); in smc91c111_writeb()
332 SET_HIGH(tcr, value); in smc91c111_writeb()
511 return s->tcr & 0xff; in smc91c111_readb()
513 return s->tcr >> 8; in smc91c111_readb()
/openbmc/linux/arch/arm64/kvm/hyp/nvhe/
H A Dtlb.c14 u64 tcr; member
53 val = cxt->tcr = read_sysreg_el1(SYS_TCR); in __tlb_switch_to_guest()
77 write_sysreg_el1(cxt->tcr, SYS_TCR); in __tlb_switch_to_host()
/openbmc/linux/drivers/iommu/arm/arm-smmu-v3/
H A Darm-smmu-v3-sva.c96 u64 tcr, par, reg; in arm_smmu_alloc_shared_cd() local
130 tcr = FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, 64ULL - vabits_actual) | in arm_smmu_alloc_shared_cd()
138 tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_4K); in arm_smmu_alloc_shared_cd()
141 tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_16K); in arm_smmu_alloc_shared_cd()
144 tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_TG0, ARM_LPAE_TCR_TG0_64K); in arm_smmu_alloc_shared_cd()
154 tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_IPS, par); in arm_smmu_alloc_shared_cd()
157 cd->tcr = tcr; in arm_smmu_alloc_shared_cd()
/openbmc/u-boot/drivers/net/
H A Dfsl_mcdmafec.c121 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); in dbg_fec_regs()
158 fecp->tcr = FEC_TCR_FDEN; in set_fec_duplex_speed()
163 fecp->tcr &= ~FEC_TCR_FDEN; in set_fec_duplex_speed()
263 fecp->tcr |= FEC_TCR_GTS; in fec_recv()
268 if (fecp->tcr & FEC_TCR_GTS) { in fec_recv()
271 fecp->tcr &= ~FEC_TCR_GTS; in fec_recv()
469 fecp->tcr |= FEC_TCR_GTS; in fec_halt()
/openbmc/linux/arch/arm64/kvm/hyp/vhe/
H A Dtlb.c15 u64 tcr; member
36 val = cxt->tcr = read_sysreg_el1(SYS_TCR); in __tlb_switch_to_guest()
75 write_sysreg_el1(cxt->tcr, SYS_TCR); in __tlb_switch_to_host()
/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dcache_v8.c41 u64 tcr; in get_tcr() local
70 tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE; in get_tcr()
72 tcr = TCR_EL2_RSVD | (ips << 16); in get_tcr()
74 tcr = TCR_EL3_RSVD | (ips << 16); in get_tcr()
78 tcr |= TCR_TG0_4K | TCR_SHARED_INNER | TCR_ORGN_WBWA | TCR_IRGN_WBWA; in get_tcr()
79 tcr |= TCR_T0SZ(va_bits); in get_tcr()
86 return tcr; in get_tcr()
/openbmc/u-boot/arch/m68k/include/asm/
H A Dtimer.h25 u16 tcr; /* 0x08 Capture register */ member
37 u32 tcr; /* 0x08 Capture register */
/openbmc/linux/drivers/watchdog/
H A Dtxx9wdt.c58 &txx9wdt_reg->tcr); in txx9wdt_start()
68 __raw_writel(__raw_readl(&txx9wdt_reg->tcr) & ~TXx9_TMTCR_TCE, in txx9wdt_stop()
69 &txx9wdt_reg->tcr); in txx9wdt_stop()

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