Home
last modified time | relevance | path

Searched refs:taddr (Results 1 – 16 of 16) sorted by relevance

/openbmc/qemu/hw/virtio/
H A Dvhost-iova-tree.c97 int vhost_iova_tree_map_alloc(VhostIOVATree *tree, DMAMap *map, hwaddr taddr) in vhost_iova_tree_map_alloc() argument
104 if (taddr + map->size < taddr || map->perm == IOMMU_NONE) { in vhost_iova_tree_map_alloc()
115 map->translated_addr = taddr; in vhost_iova_tree_map_alloc()
159 int vhost_iova_tree_map_alloc_gpa(VhostIOVATree *tree, DMAMap *map, hwaddr taddr) in vhost_iova_tree_map_alloc_gpa() argument
166 if (taddr + map->size < taddr || map->perm == IOMMU_NONE) { in vhost_iova_tree_map_alloc_gpa()
177 map->translated_addr = taddr; in vhost_iova_tree_map_alloc_gpa()
H A Dvhost-iova-tree.h25 hwaddr taddr);
30 hwaddr taddr);
H A Dvhost-vdpa.c1167 hwaddr taddr, Error **errp) in vhost_vdpa_svq_map_ring() argument
1171 r = vhost_iova_tree_map_alloc(v->shared->iova_tree, needle, taddr); in vhost_vdpa_svq_map_ring()
1175 if (needle->translated_addr == taddr) { in vhost_vdpa_svq_map_ring()
/openbmc/qemu/include/hw/ppc/
H A Dspapr_vio.h91 static inline bool spapr_vio_dma_valid(SpaprVioDevice *dev, uint64_t taddr, in spapr_vio_dma_valid() argument
94 return dma_memory_valid(&dev->as, taddr, size, dir, MEMTXATTRS_UNSPECIFIED); in spapr_vio_dma_valid()
97 static inline int spapr_vio_dma_read(SpaprVioDevice *dev, uint64_t taddr, in spapr_vio_dma_read() argument
100 return (dma_memory_read(&dev->as, taddr, in spapr_vio_dma_read()
105 static inline int spapr_vio_dma_write(SpaprVioDevice *dev, uint64_t taddr, in spapr_vio_dma_write() argument
108 return (dma_memory_write(&dev->as, taddr, in spapr_vio_dma_write()
113 static inline int spapr_vio_dma_set(SpaprVioDevice *dev, uint64_t taddr, in spapr_vio_dma_set() argument
116 return (dma_memory_set(&dev->as, taddr, in spapr_vio_dma_set()
/openbmc/openbmc/poky/meta/recipes-extended/rpcbind/rpcbind/
H A Drpcbind_add_option_to_fix_port_number.patch64 + struct t_bind taddr;
75 + memset(&taddr, 0, sizeof(taddr));
76 + taddr.addr.maxlen = taddr.addr.len = si.si_alen;
77 + taddr.addr.buf = malloc(si.si_alen);
78 + if (taddr.addr.buf == NULL) {
81 + *(unsigned short *)(&(taddr.addr.buf[0])) = si.si_af;
82 + *(unsigned short *)(&(taddr.addr.buf[2])) = htons(fixed_port);
83 + xprt = svc_tli_create(fd, nconf, &taddr, RPC_MAXDATASIZE, RPC_MAXDATASIZE);
/openbmc/qemu/tcg/
H A Dtci.c278 static uint64_t tci_qemu_ld(CPUArchState *env, uint64_t taddr, in tci_qemu_ld() argument
286 return helper_ldub_mmu(env, taddr, oi, ra); in tci_qemu_ld()
288 return helper_ldsb_mmu(env, taddr, oi, ra); in tci_qemu_ld()
290 return helper_lduw_mmu(env, taddr, oi, ra); in tci_qemu_ld()
292 return helper_ldsw_mmu(env, taddr, oi, ra); in tci_qemu_ld()
294 return helper_ldul_mmu(env, taddr, oi, ra); in tci_qemu_ld()
296 return helper_ldsl_mmu(env, taddr, oi, ra); in tci_qemu_ld()
298 return helper_ldq_mmu(env, taddr, oi, ra); in tci_qemu_ld()
304 static void tci_qemu_st(CPUArchState *env, uint64_t taddr, uint64_t val, in tci_qemu_st() argument
312 helper_stb_mmu(env, taddr, va in tci_qemu_st()
355 uint64_t tmp64, taddr; tcg_qemu_tb_exec() local
[all...]
/openbmc/u-boot/drivers/core/
H A Dof_addr.c326 u64 taddr; in __of_address_to_resource() local
330 taddr = of_translate_address(dev, addrp); in __of_address_to_resource()
331 if (taddr == OF_BAD_ADDR) in __of_address_to_resource()
334 r->start = taddr; in __of_address_to_resource()
335 r->end = taddr + size - 1; in __of_address_to_resource()
/openbmc/qemu/hw/pci-host/
H A Dpnv_phb3.c776 uint64_t base, taddr, tce, tce_mask; in pnv_phb3_translate_tve() local
801 taddr = base | (((addr >> sh) & ((1ul << tbl_shift) - 1)) << 3); in pnv_phb3_translate_tve()
802 if (dma_memory_read(&address_space_memory, taddr, &tce, in pnv_phb3_translate_tve()
804 phb3_error(phb, "Failed to read TCE at 0x%"PRIx64, taddr); in pnv_phb3_translate_tve()
811 phb3_error(phb, "Invalid indirect TCE at 0x%"PRIx64, taddr); in pnv_phb3_translate_tve()
824 phb3_error(phb, "TCE access fault at 0x%"PRIx64, taddr); in pnv_phb3_translate_tve()
H A Dpnv_phb4.c1255 uint64_t base, taddr, tce, tce_mask; in pnv_phb4_translate_tve() local
1276 taddr = base | (((addr >> sh) & ((1ul << tbl_shift) - 1)) << 3); in pnv_phb4_translate_tve()
1277 if (dma_memory_read(&address_space_memory, taddr, &tce, in pnv_phb4_translate_tve()
1279 phb_error(ds->phb, "Failed to read TCE at 0x%"PRIx64, taddr); in pnv_phb4_translate_tve()
1286 phb_error(ds->phb, "Invalid indirect TCE at 0x%"PRIx64, taddr); in pnv_phb4_translate_tve()
1299 phb_error(ds->phb, "TCE access fault at 0x%"PRIx64, taddr); in pnv_phb4_translate_tve()
/openbmc/qemu/target/mips/tcg/
H A Dmsa_translate.c764 TCGv taddr; in trans_msa_ldst() local
770 taddr = tcg_temp_new(); in trans_msa_ldst()
772 gen_base_offset_addr(ctx, taddr, a->ws, a->sa << a->df); in trans_msa_ldst()
773 gen_msa_ldst(tcg_env, tcg_constant_i32(a->wd), taddr); in trans_msa_ldst()
H A Dnanomips_translate.c.inc995 TCGv taddr = tcg_temp_new();
1000 gen_base_offset_addr(ctx, taddr, base, offset);
1001 tcg_gen_qemu_ld_i64(tval, taddr, ctx->mem_idx,
1011 tcg_gen_st_tl(taddr, tcg_env, offsetof(CPUMIPSState, lladdr));
1017 TCGv taddr = tcg_temp_new();
1027 gen_base_offset_addr(ctx, taddr, base, offset);
1030 tcg_gen_brcond_tl(TCG_COND_NE, taddr, lladdr, lab_fail);
1042 tcg_gen_atomic_cmpxchg_i64(val, taddr, llval, tval,
/openbmc/qemu/hw/alpha/
H A Dtyphoon.c610 static bool make_iommu_tlbe(hwaddr taddr, hwaddr mask, IOMMUTLBEntry *ret) in make_iommu_tlbe() argument
614 .translated_addr = taddr, in make_iommu_tlbe()
/openbmc/qemu/target/arm/tcg/
H A Dtranslate.c2037 TCGv taddr = gen_aa32_addr(s, addr, opc); in disas_iwmmxt_insn()
2039 tcg_gen_qemu_ld_i64(t64, taddr, get_mem_index(s), opc); in disas_iwmmxt_insn()
2066 TCGv taddr; in disas_iwmmxt_insn()
2083 taddr = gen_aa32_addr(s, addr, opc); in disas_iwmmxt_insn()
2107 tcg_gen_atomic_cmpxchg_i64(o64, taddr, cpu_exclusive_val, n64, in disas_iwmmxt_insn()
2115 tcg_gen_atomic_cmpxchg_i32(t0, taddr, t2, t1, get_mem_index(s), opc); in disas_iwmmxt_insn()
3777 TCGv taddr = gen_aa32_addr(s, addr, opc);
3782 tcg_gen_qemu_ld_i64(t64, taddr, mem_idx, opc); in op_s_rri_rot()
3832 TCGv taddr = gen_aa32_addr(s, addr, opc);
3842 tcg_gen_qemu_st_i64(t64, taddr, mem_id
3273 TCGv taddr = gen_aa32_addr(s, addr, opc); gen_load_exclusive() local
3302 TCGv taddr; gen_store_exclusive() local
5020 TCGv taddr = gen_aa32_addr(s, addr, opc); do_ldrd_load() local
5075 TCGv taddr = gen_aa32_addr(s, addr, opc); do_strd_store() local
5296 TCGv taddr; DO_LDST() local
[all...]
/openbmc/qemu/net/
H A Dvhost-vdpa.c532 hwaddr taddr = (hwaddr)(uintptr_t)buf; in vhost_vdpa_cvq_map_buf() local
537 r = vhost_iova_tree_map_alloc(v->shared->iova_tree, &map, taddr); in vhost_vdpa_cvq_map_buf()
541 if (map.translated_addr == taddr) { in vhost_vdpa_cvq_map_buf()
/openbmc/u-boot/drivers/qe/
H A Duec.h475 uec_82xx_enet_address_t taddr; member
/openbmc/qemu/target/riscv/
H A Dcpu_helper.c1910 target_ulong taddr) in riscv_transformed_insn()
2106 xinsn = SET_RS1(xinsn, (taddr - (env->gpr[access_rs1] + access_imm)) & in riscv_transformed_insn()
1909 riscv_transformed_insn(CPURISCVState * env,target_ulong insn,target_ulong taddr) riscv_transformed_insn() argument