Searched refs:t_wr (Results 1 – 4 of 4) sorted by relevance
| /openbmc/u-boot/arch/arm/mach-keystone/ |
| H A D | ddr3_spd.c | 119 u32 t_wr; member
216 spd->t_wr = (buf->twr_min * mtb) / spd->t_ck; in ddrtimingcalculation()
217 spd->t_wr_bin = (spd->t_wr / 2) & 0x07; in ddrtimingcalculation()
377 spd_cb->emif_cfg.sdtim1 = ((spd->t_wr - 1) & 0x1f) << 25 | in init_ddr3param()
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| /openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/ |
| H A D | dram.c | 44 writel((ck / dram->twr) & 0x0000000F, &emc->t_wr); in ddr_init()
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| /openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/ |
| H A D | emc.h | 25 u32 t_wr; /* Write recovery time */ member
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| /openbmc/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training.c | 339 u32 t_ckclk = 0, t_wr = 0, t2t = 0; in hws_ddr3_tip_init_controller() local
520 t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get in hws_ddr3_tip_init_controller()
533 MR0_REG, twr_mask_table[t_wr] << 9, in hws_ddr3_tip_init_controller()
1200 bus_cnt = 0, t_wr = 0, t_ckclk = 0, in ddr3_tip_freq_set() local
1394 t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get in ddr3_tip_freq_set()
1400 (twr_mask_table[t_wr] << 16), 0x70000)); in ddr3_tip_freq_set()
1623 u32 t_rcd = 0, t_rp = 0, t_wr = 0, t_wtr = 0, t_rrd = 0, t_rtp = 0, in ddr3_tip_set_timing() local
1678 t_wr = time_to_nclk(mv_ddr_speed_bin_timing_get(speed_bin_index, in ddr3_tip_set_timing()
1695 (((t_wr - 1) & SDRAM_TIMING_LOW_TWR_MASK) << SDRAM_TIMING_LOW_TWR_OFFS) | in ddr3_tip_set_timing()
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