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Searched refs:tZQCS (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/memory/
H A Djedec_ddr_data.c48 .tZQCS = 90000,
69 .tZQCS = 90000,
90 .tZQCS = 90000,
111 .tZQCS = 90000,
H A Djedec_ddr.h162 u32 tZQCS; member
H A Dof_memory.c81 ret |= of_property_read_u32(np, "tZQCS", &tim->tZQCS); in of_do_get_timings()
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Demif.c38 .tZQCS = 90,
62 .tZQCS = 90,
H A Dsdram_elpida.c205 .tZQCS = 90,
228 .tZQCS = 90,
251 .tZQCS = 90,
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Delpida_ecb240abacn.dtsi39 tZQCS = <90000>;
61 tZQCS = <90000>;
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c136 struct dram_sun9i_timing tZQCS; member
398 const u32 tZQCS = MAX(para->tZQCS.ck, in mctl_channel_init() local
399 PS2CYCLES_ROUNDUP(para->tZQCS.ps)); in mctl_channel_init()
600 (MCTL_DIV2(tZQCS)), &mctl_ctl->zqctrl[0]); in mctl_channel_init()
906 .tZQCS = { .ck = 64, .ps = 80000 }, in sunxi_dram_init()
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Demif.c39 .tZQCS = 90,
H A Dsdram.c627 .tZQCS = 90,
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr2-timings.yaml97 tZQCS:
133 tZQCS = <90000>;
H A Djedec,lpddr2.yaml178 tZQCS = <90000>;
199 tZQCS = <90000>;
/openbmc/u-boot/arch/arm/include/asm/
H A Demif.h1154 u8 tZQCS; member
/openbmc/u-boot/arch/arm/mach-omap2/
H A Demif-common.c754 val = ns_2_cycles(timings->tZQCS) - 1; in get_sdram_tim_3_reg()