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Searched refs:sys_pll_psc (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/drivers/clk/
H A Dclk_stm32f.c105 .sys_pll_psc = {
119 .sys_pll_psc = {
149 struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc; in configure_clocks() local
166 sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT) in configure_clocks()
167 | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT) in configure_clocks()
168 | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT))); in configure_clocks()
173 sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT); in configure_clocks()
175 sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT); in configure_clocks()
177 ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); in configure_clocks()
179 sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT); in configure_clocks()
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H A Dclk_stm32h7.c332 struct pll_psc sys_pll_psc = { variable
394 pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT; in configure_clocks()
397 pll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT; in configure_clocks()
398 pll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT; in configure_clocks()
399 pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT; in configure_clocks()
400 pll1divr |= (sys_pll_psc.divn - 1); in configure_clocks()
/openbmc/u-boot/include/
H A Dstm32_rcc.h37 struct pll_psc sys_pll_psc; member