| /openbmc/qemu/hw/ssi/ |
| H A D | ssi.c | 87 SSIPeripheralClass *ssc = dev->spc; in ssi_transfer_raw_default() local
89 if ((dev->cs && ssc->cs_polarity == SSI_CS_HIGH) || in ssi_transfer_raw_default()
90 (!dev->cs && ssc->cs_polarity == SSI_CS_LOW) || in ssi_transfer_raw_default()
91 ssc->cs_polarity == SSI_CS_NONE) { in ssi_transfer_raw_default()
92 return ssc->transfer(dev, val); in ssi_transfer_raw_default()
100 SSIPeripheralClass *ssc = SSI_PERIPHERAL_GET_CLASS(s); in ssi_peripheral_realize() local
102 if (ssc->transfer_raw == ssi_transfer_raw_default && in ssi_peripheral_realize()
103 ssc->cs_polarity != SSI_CS_NONE) { in ssi_peripheral_realize()
106 s->spc = ssc; in ssi_peripheral_realize()
108 ssc->realize(s, errp); in ssi_peripheral_realize()
[all …]
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| /openbmc/u-boot/arch/x86/lib/ |
| H A D | pmu.c | 22 u32 ssc[4]; member
54 u32 ssc; in pmu_power_lss() local
63 ssc = readl(®s->sss[offset]); in pmu_power_lss()
67 ssc &= ~(0x3 << shift); /* D0 */ in pmu_power_lss()
69 ssc |= 0x3 << shift; /* D3hot */ in pmu_power_lss()
72 writel(ssc, ®s->ssc[offset]); in pmu_power_lss()
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | at91sam9g20.dtsi | 34 ssc0: ssc@fffbc000 {
35 compatible = "atmel,at91sam9rl-ssc";
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| H A D | stih407-family.dtsi | 260 clock-names = "ssc";
275 clock-names = "ssc";
290 clock-names = "ssc";
305 clock-names = "ssc";
320 clock-names = "ssc";
335 clock-names = "ssc";
352 clock-names = "ssc";
367 clock-names = "ssc";
444 clock-names = "ssc";
458 clock-names = "ssc";
[all …]
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| H A D | at91sam9x5ek.dtsi | 134 ssc0: ssc@f0010000 {
164 atmel,ssc-controller = <&ssc0>;
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| H A D | sama5d33ek.dts | 28 ssc0: ssc@f0008000 {
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| H A D | at91sam9g20ek_common.dtsi | 93 ssc0: ssc@fffbc000 {
224 atmel,ssc-controller = <&ssc0>;
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| H A D | sama5d36ek.dts | 28 ssc0: ssc@f0008000 {
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| H A D | sama5d36ek_cmp.dts | 27 ssc0: ssc@f0008000 {
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| H A D | sama5d31ek.dts | 28 ssc0: ssc@f0008000 {
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| H A D | sama5d34ek.dts | 28 ssc0: ssc@f0008000 {
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| H A D | at91sam9261.dtsi | 200 ssc0: ssc@fffbc000 {
201 compatible = "atmel,at91rm9200-ssc";
211 ssc1: ssc@fffc0000 {
212 compatible = "atmel,at91rm9200-ssc";
222 ssc2: ssc@fffc4000 {
223 compatible = "atmel,at91rm9200-ssc";
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| H A D | sama5d3xmb_cmp.dtsi | 41 ssc0: ssc@f0008000 {
213 atmel,ssc-controller = <&ssc0>;
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| H A D | at91sam9n12ek.dts | 43 ssc0: ssc@f0010000 {
262 atmel,ssc-controller = <&ssc0>;
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| H A D | sama5d3xmb.dtsi | 45 ssc0: ssc@f0008000 {
229 atmel,ssc-controller = <&ssc0>;
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| H A D | at91sam9260-smartweb.dts | 81 ssc0: ssc@fffbc000 {
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| H A D | at91sam9g20-taurus.dts | 81 ssc0: ssc@fffbc000 {
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| H A D | at91sam9g45-gurnard.dts | 111 ssc0: ssc@fff9c000 {
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| H A D | at91-sama5d4ek.dts | 130 ssc0: ssc@f8008000 {
364 atmel,ssc-controller = <&ssc0>;
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| H A D | at91sam9rl.dtsi | 211 ssc0: ssc@fffc0000 {
212 compatible = "atmel,at91sam9rl-ssc";
220 ssc1: ssc@fffc4000 {
221 compatible = "atmel,at91sam9rl-ssc";
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| /openbmc/qemu/hw/arm/ |
| H A D | stm32l4x5_soc.c | 451 Stm32l4x5SocClass *ssc = STM32L4X5_SOC_CLASS(oc); in stm32l4x5xc_soc_class_init() local
453 ssc->flash_size = 256 * KiB; in stm32l4x5xc_soc_class_init()
458 Stm32l4x5SocClass *ssc = STM32L4X5_SOC_CLASS(oc); in stm32l4x5xe_soc_class_init() local
460 ssc->flash_size = 512 * KiB; in stm32l4x5xe_soc_class_init()
465 Stm32l4x5SocClass *ssc = STM32L4X5_SOC_CLASS(oc); in stm32l4x5xg_soc_class_init() local
467 ssc->flash_size = 1 * MiB; in stm32l4x5xg_soc_class_init()
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| /openbmc/qemu/hw/net/ |
| H A D | xilinx_axienet.c | 1022 StreamSinkClass *ssc = STREAM_SINK_CLASS(klass); in xilinx_enet_control_stream_class_init() local
1024 ssc->push = xilinx_axienet_control_stream_push; in xilinx_enet_control_stream_class_init()
1030 StreamSinkClass *ssc = STREAM_SINK_CLASS(klass); in xilinx_enet_data_stream_class_init() local
1032 ssc->push = xilinx_axienet_data_stream_push; in xilinx_enet_data_stream_class_init()
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| /openbmc/qemu/hw/dma/ |
| H A D | xilinx_axidma.c | 645 StreamSinkClass *ssc = STREAM_SINK_CLASS(klass); in xilinx_axidma_stream_class_init() local
647 ssc->push = ((StreamSinkClass *)data)->push; in xilinx_axidma_stream_class_init()
648 ssc->can_push = ((StreamSinkClass *)data)->can_push; in xilinx_axidma_stream_class_init()
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| H A D | xlnx_csu_dma.c | 718 StreamSinkClass *ssc = STREAM_SINK_CLASS(klass); in xlnx_csu_dma_class_init() local
726 ssc->push = xlnx_csu_dma_stream_push; in xlnx_csu_dma_class_init()
727 ssc->can_push = xlnx_csu_dma_stream_can_push; in xlnx_csu_dma_class_init()
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| /openbmc/qemu/target/arm/ |
| H A D | debug_helper.c | 262 int pac, hmc, ssc, wt, lbn; in bp_wp_matches() local
308 ssc = FIELD_EX64(cr, DBGWCR, SSC); in bp_wp_matches()
310 switch (ssc) { in bp_wp_matches()
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