Home
last modified time | relevance | path

Searched refs:sr (Results 1 – 25 of 448) sorted by relevance

12345678910>>...18

/openbmc/u-boot/arch/m68k/lib/
H A Dinterrupts.c29 unsigned short sr; in get_sr() local
31 asm volatile ("move.w %%sr,%0":"=r" (sr):); in get_sr()
33 return sr; in get_sr()
36 static __inline__ void set_sr (unsigned short sr) in set_sr() argument
38 asm volatile ("move.w %0,%%sr"::"r" (sr)); in set_sr()
69 unsigned short sr; in enable_interrupts() local
71 sr = get_sr (); in enable_interrupts()
72 set_sr (sr & ~0x0700); in enable_interrupts()
77 unsigned short sr; in disable_interrupts() local
79 sr = get_sr (); in disable_interrupts()
[all …]
/openbmc/ipmitool/lib/
H A Dipmi_sensor.c163 struct sensor_reading *sr; in ipmi_sensor_print_fc_discrete() local
165 sr = ipmi_sdr_read_sensor_value(intf, sensor, sdr_record_type, 3); in ipmi_sensor_print_fc_discrete()
167 if (sr == NULL) { in ipmi_sensor_print_fc_discrete()
178 printf("%-16s ", sr->s_id); in ipmi_sensor_print_fc_discrete()
179 if (sr->s_reading_valid) { in ipmi_sensor_print_fc_discrete()
180 if (sr->s_has_analog_value) { in ipmi_sensor_print_fc_discrete()
183 sr->s_a_str, sr->s_a_units, "ok"); in ipmi_sensor_print_fc_discrete()
186 sr->s_reading, "discrete", in ipmi_sensor_print_fc_discrete()
187 sr->s_data2, sr->s_data3); in ipmi_sensor_print_fc_discrete()
199 sr->s_id, sensor->keys.sensor_num); in ipmi_sensor_print_fc_discrete()
[all …]
H A Dipmi_sdr.c122 struct sensor_reading *sr) in sdr_sensor_has_analog_reading() argument
125 if (!sr->full) { in sdr_sensor_has_analog_reading()
144 if ( UNITS_ARE_DISCRETE(&sr->full->cmn) ) { in sdr_sensor_has_analog_reading()
147 if ( !IS_THRESHOLD_SENSOR(&sr->full->cmn) ) { in sdr_sensor_has_analog_reading()
150 if ( (sr->full->cmn.unit.pct | sr->full->cmn.unit.modifier | in sdr_sensor_has_analog_reading()
151 sr->full->cmn.unit.type.base | in sdr_sensor_has_analog_reading()
152 sr->full->cmn.unit.type.modifier)) { in sdr_sensor_has_analog_reading()
166 if (sr->full->linearization >= SDR_SENSOR_L_NONLINEAR && in sdr_sensor_has_analog_reading()
167 sr->full->linearization <= 0x7F) { in sdr_sensor_has_analog_reading()
168 if (ipmi_sensor_get_sensor_reading_factors(intf, sr->full, sr->s_reading) < 0){ in sdr_sensor_has_analog_reading()
[all …]
/openbmc/qemu/target/hppa/
H A Dgdbstub.c73 val = env->sr[4] >> 32; in hppa_cpu_gdb_read_register()
76 val = env->sr[0] >> 32; in hppa_cpu_gdb_read_register()
79 val = env->sr[1] >> 32; in hppa_cpu_gdb_read_register()
82 val = env->sr[2] >> 32; in hppa_cpu_gdb_read_register()
85 val = env->sr[3] >> 32; in hppa_cpu_gdb_read_register()
88 val = env->sr[5] >> 32; in hppa_cpu_gdb_read_register()
91 val = env->sr[6] >> 32; in hppa_cpu_gdb_read_register()
94 val = env->sr[7] >> 32; in hppa_cpu_gdb_read_register()
199 env->sr[4] = (uint64_t)val << 32; in hppa_cpu_gdb_write_register()
202 env->sr[0] = (uint64_t)val << 32; in hppa_cpu_gdb_write_register()
[all …]
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_sr.S3 test_suite sr
17 .macro sr_op sym, op_sym, op_byte, sr argument
19 \op_sym a4, \sr
21 .byte LOW__SR, \sr, \op_byte
25 .macro test_sr_op sym, mask, op, op_byte, sr argument
29 sr_op \sym, \op, \op_byte, \sr
33 sr_op \sym, \op, \op_byte, \sr
45 .macro test_sr_mask sr, sym, mask
46 test \sr
47 test_sr_op \sym, \mask & 1, rsr, HI_RSR, \sr
[all …]
H A Dfpu.h49 .macro test_op1_rm op, fr0, fr1, v0, r, sr
54 check_res \fr1, \r, \sr
57 .macro test_op2_rm op, fr0, fr1, fr2, v0, v1, r, sr
63 check_res \fr2, \r, \sr
66 .macro test_op3_rm op, fr0, fr1, fr2, fr3, v0, v1, v2, r, sr
73 check_res \fr3, \r, \sr
76 .macro test_op1_ex op, fr0, fr1, v0, rm, r, sr
79 test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr
82 test_op1_rm \op, \fr0, \fr1, \v0, \r, \sr
85 .macro test_op2_ex op, fr0, fr1, fr2, v0, v1, rm, r, sr
[all …]
/openbmc/qemu/target/openrisc/
H A Dinterrupt.c46 env->sr &= ~SR_DME; in openrisc_cpu_do_interrupt()
47 env->sr &= ~SR_IME; in openrisc_cpu_do_interrupt()
48 env->sr |= SR_SM; in openrisc_cpu_do_interrupt()
49 env->sr &= ~SR_IEE; in openrisc_cpu_do_interrupt()
50 env->sr &= ~SR_TEE; in openrisc_cpu_do_interrupt()
58 env->sr |= SR_DSX; in openrisc_cpu_do_interrupt()
61 env->sr &= ~SR_DSX; in openrisc_cpu_do_interrupt()
93 if (env->sr & SR_EPH) { in openrisc_cpu_do_interrupt()
109 if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) { in openrisc_cpu_exec_interrupt()
112 if ((interrupt_request & CPU_INTERRUPT_TIMER) && (env->sr & SR_TEE)) { in openrisc_cpu_exec_interrupt()
H A Dmmu.c146 int prot, excp, sr = cpu->env.sr; in openrisc_cpu_get_phys_page_debug() local
149 switch (sr & (SR_DME | SR_IME)) { in openrisc_cpu_get_phys_page_debug()
154 (sr & SR_SM) != 0); in openrisc_cpu_get_phys_page_debug()
160 (sr & SR_SM) != 0); in openrisc_cpu_get_phys_page_debug()
169 (sr & SR_SM) != 0); in openrisc_cpu_get_phys_page_debug()
/openbmc/qemu/hw/i2c/
H A Dmpc_i2c.c83 uint8_t sr; member
105 return s->sr & CSR_MIF; in mpc_i2c_irq_pending()
121 i2c->sr = 0x81; in mpc_i2c_reset()
153 s->sr |= CSR_RXAK; in mpc_i2c_address_send()
156 s->sr &= ~CSR_RXAK; in mpc_i2c_address_send()
157 s->sr |= CSR_MCF; /* Set after Byte Transfer is completed */ in mpc_i2c_address_send()
158 s->sr |= CSR_MIF; /* Set after Byte Transfer is completed */ in mpc_i2c_address_send()
167 s->sr |= CSR_RXAK; in mpc_i2c_data_send()
170 s->sr &= ~CSR_RXAK; in mpc_i2c_data_send()
171 s->sr |= CSR_MCF; /* Set after Byte Transfer is completed */ in mpc_i2c_data_send()
[all …]
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dtie.h69 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
70 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
71 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
72 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
73 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
74 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
75 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dtie.h93 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
94 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
95 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
97 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
98 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
99 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0)
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dtie.h92 XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
93 XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
94 XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
95 XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
96 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
97 XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) \
98 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
/openbmc/qemu/hw/char/
H A Dmcf_uart.c27 uint8_t sr; member
74 if (s->sr & MCF_UART_TxRDY) in OBJECT_DECLARE_SIMPLE_TYPE()
76 if ((s->sr & ((s->mr[0] & MCF_UART_RxIRQ) in OBJECT_DECLARE_SIMPLE_TYPE()
91 return s->sr; in mcf_uart_read()
104 s->sr &= ~MCF_UART_FFULL; in mcf_uart_read()
106 s->sr &= ~MCF_UART_RxRDY; in mcf_uart_read()
128 if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) { in mcf_uart_do_tx()
132 s->sr |= MCF_UART_TxEMP; in mcf_uart_do_tx()
135 s->sr |= MCF_UART_TxRDY; in mcf_uart_do_tx()
137 s->sr &= ~MCF_UART_TxRDY; in mcf_uart_do_tx()
[all …]
H A Dipoctal232.c106 uint8_t sr; member
137 VMSTATE_UINT8(sr, SCC2698Channel),
211 ch->sr |= SR_TXRDY | SR_TXEMT; in write_cr()
216 ch->sr &= ~(SR_TXRDY | SR_TXEMT); in write_cr()
235 ch->sr &= ~SR_RXRDY; in write_cr()
240 ch->sr &= ~(SR_TXRDY | SR_TXEMT); in write_cr()
245 ch->sr &= ~(SR_OVERRUN | SR_PARITY | SR_FRAMING | SR_BREAK); in write_cr()
284 ret = ch->sr; in io_read()
294 ch->sr &= ~SR_RXRDY; in io_read()
300 if (ch->sr & SR_BREAK) { in io_read()
[all …]
/openbmc/openbmc/poky/meta/recipes-support/libcheck/libcheck/
H A Dautomake-output.patch24 @@ -381,6 +382,34 @@ void tap_lfun(SRunner * sr CK_ATTRIBUTE_UNUSED, FILE * file,
28 +void am_lfun(SRunner * sr CK_ATTRIBUTE_UNUSED, FILE * file,
57 void subunit_lfun(SRunner * sr, FILE * file, enum print_output printmode,
59 @@ -527,6 +556,9 @@ void srunner_init_logging(SRunner * sr, enum print_output print_mode)
61 srunner_register_lfun(sr, f, f != stdout, tap_lfun, print_mode);
64 + srunner_register_lfun(sr, stdout, 0, am_lfun, print_mode);
66 srunner_send_evt(sr, NULL, CLINITLOG_SR);
73 @@ -40,6 +40,9 @@ void xml_lfun(SRunner * sr, FILE * file, enum print_output,
74 void tap_lfun(SRunner * sr, FILE * file, enum print_output,
77 +void am_lfun(SRunner * sr, FILE * file, enum print_output,
[all …]
/openbmc/openbmc/meta-arm/meta-arm-systemready/recipes-test/arm-systemready-acs/arm-systemready-scripts/
H A D0001-check-sr-results-Return-non-zero-exit-code-on-failur.patch4 Subject: [PATCH] check-sr-results: Return non-zero exit code on failure
11 check-sr-results.py | 6 ++++++
14 diff --git a/check-sr-results.py b/check-sr-results.py
16 --- a/check-sr-results.py
17 +++ b/check-sr-results.py
H A D0002-check-sr-results-Device-tree-improvements.patch4 Subject: [PATCH] check-sr-results: Device tree improvements
6 Make check-sr-results.py accept 'extra_compat' configuration for
15 check-sr-results.py | 12 ++++++++++--
19 diff --git a/check-sr-results.py b/check-sr-results.py
21 --- a/check-sr-results.py
22 +++ b/check-sr-results.py
/openbmc/openbmc/meta-arm/meta-arm-bsp/dynamic-layers/meta-arm-systemready/recipes-test/arm-systemready-acs/files/fvp-base/
H A D0001-check-sr-results-Change-the-expected-SR-result-confi.patch4 Subject: [PATCH] [PATCH] check-sr-results: Change the expected SR result
7 Update the check-sr-results.yaml and format-sr-results.yaml files for the
12 Changes to check-sr-results.yaml:
56 Changes to format-sr-results.yaml:
58 format-sr-results.py to error).
63 check-sr-results.yaml | 34 ++++++++++++++--------------------
64 format-sr-results.yaml | 15 ---------------
67 diff --git a/check-sr-results.yaml b/check-sr-results.yaml
69 --- a/check-sr-results.yaml
70 +++ b/check-sr-results.yaml
[all …]
/openbmc/bmcweb/test/http/
H A Dhttp_response_test.cpp40 boost::beast::http::response_serializer<bmcweb::HttpBody> sr{m}; in getData() local
41 sr.split(true); in getData()
44 [&sr, &ret](const boost::system::error_code& ec2, const auto& buffer) { in getData()
47 sr.consume(ret2.size()); in getData()
53 while (!sr.is_header_done()) in getData()
55 sr.next(ec, reader); in getData()
61 while (!sr.is_done()) in getData()
63 sr.next(ec, reader); in getData()
/openbmc/qemu/target/ppc/
H A Dmmu-hash32.c113 static bool ppc_hash32_direct_store(PowerPCCPU *cpu, target_ulong sr, in ppc_hash32_direct_store() argument
181 if (ppc_hash32_key(mmuidx_pr(mmu_idx), sr)) { in ppc_hash32_direct_store()
255 target_ulong sr, target_ulong eaddr, in ppc_hash32_htab_lookup() argument
262 vsid = sr & SR32_VSID; in ppc_hash32_htab_lookup()
300 target_ulong sr; in ppc_hash32_xlate() local
345 sr = env->sr[eaddr >> 28]; in ppc_hash32_xlate()
348 if (sr & SR32_T) { in ppc_hash32_xlate()
349 return ppc_hash32_direct_store(cpu, sr, eaddr, access_type, in ppc_hash32_xlate()
354 if (access_type == MMU_INST_FETCH && (sr & SR32_NX)) { in ppc_hash32_xlate()
363 pte_offset = ppc_hash32_htab_lookup(cpu, sr, eaddr, &pte); in ppc_hash32_xlate()
[all …]
/openbmc/u-boot/arch/arc/lib/
H A Dstart.S13 sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
45 sr r5, [ARC_AUX_DC_CTRL]
48 sr r5, [ARC_AUX_DC_IVDC]
120 sr %r0, [ARC_AUX_INTR_VEC_BASE]
/openbmc/u-boot/arch/arm/mach-at91/
H A Dspl_at91.c34 if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) { in lowlevel_clock_init()
39 while (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) in lowlevel_clock_init()
51 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in lowlevel_clock_init()
57 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in lowlevel_clock_init()
/openbmc/qemu/hw/ssi/
H A Dpl022.c53 s->sr = 0; in pl022_update()
55 s->sr |= PL022_SR_TFE; in pl022_update()
57 s->sr |= PL022_SR_TNF; in pl022_update()
59 s->sr |= PL022_SR_RNE; in pl022_update()
61 s->sr |= PL022_SR_RFF; in pl022_update()
63 s->sr |= PL022_SR_BSY; in pl022_update()
143 return s->sr; in pl022_read()
225 s->sr = PL022_SR_TFE | PL022_SR_TNF; in pl022_reset()
256 VMSTATE_UINT32(sr, PL022State),
/openbmc/u-boot/arch/arm/mach-at91/arm926ejs/
H A Dclock.c207 while (!(readl(&pmc->sr) & AT91_PMC_LOCKA)) in at91_plla_init()
215 while (!(readl(&pmc->sr) & AT91_PMC_LOCKB)) in at91_pllb_init()
228 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in at91_mck_init()
235 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in at91_mck_init()
242 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in at91_mck_init()
249 while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) in at91_mck_init()
260 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) { in at91_pllb_clk_enable()
278 while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) { in at91_pllb_clk_disable()
/openbmc/qemu/target/m68k/
H A Dop_helper.c46 uint16_t sr; in m68k_rte() local
50 sr = cpu_lduw_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); in m68k_rte()
63 cpu_m68k_set_sr(env, sr); in m68k_rte()
78 cpu_m68k_set_sr(env, sr); in m68k_rte()
190 uint32_t sr; in cf_interrupt_all() local
212 sr = env->sr | cpu_m68k_get_ccr(env); in cf_interrupt_all()
217 vector, env->pc, env->aregs[7], sr); in cf_interrupt_all()
222 fmt |= sr; in cf_interrupt_all()
224 env->sr |= SR_S; in cf_interrupt_all()
226 env->sr = (env->sr & ~SR_I) | (env->pending_level << SR_I_SHIFT); in cf_interrupt_all()
[all …]

12345678910>>...18