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Searched refs:spr_cb (Results 1 – 15 of 15) sorted by relevance

/openbmc/qemu/target/ppc/
H A Dgdbstub.c312 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { in ppc_gdb_gen_spr_xml()
313 ppc_spr_t *spr = &env->spr_cb[i]; in ppc_gdb_gen_spr_xml()
339 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { in ppc_gdb_gen_spr_xml()
340 ppc_spr_t *spr = &env->spr_cb[i]; in ppc_gdb_gen_spr_xml()
376 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { in gdb_find_spr_idx()
377 ppc_spr_t *spr = &env->spr_cb[i]; in gdb_find_spr_idx()
H A Dppc-qmp-cmds.c154 for (i = 0; i < ARRAY_SIZE(env->spr_cb); ++i) { in target_get_monitor_def()
155 ppc_spr_t *spr = &env->spr_cb[i]; in target_get_monitor_def()
H A Dtranslate.c197 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ member
4728 read_cb = ctx->spr_cb[sprn].uea_read; in gen_op_mfspr()
4731 read_cb = ctx->spr_cb[sprn].uea_read; in gen_op_mfspr()
4733 read_cb = ctx->spr_cb[sprn].hea_read; in gen_op_mfspr()
4735 read_cb = ctx->spr_cb[sprn].oea_read; in gen_op_mfspr()
4912 write_cb = ctx->spr_cb[sprn].uea_write; in gen_mtspr()
4915 write_cb = ctx->spr_cb[sprn].uea_write; in gen_mtspr()
4917 write_cb = ctx->spr_cb[sprn].hea_write; in gen_mtspr()
4919 write_cb = ctx->spr_cb[sprn].oea_write; in gen_mtspr()
7326 ctx->spr_cb = env->spr_cb; in ppc_tr_init_disas_context()
H A Dhelper_regs.c364 ppc_spr_t *spr = &env->spr_cb[num]; in _spr_register()
H A Dcpu.h1265 ppc_spr_t spr_cb[1024]; member
1378 (POWERPC_CPU(cs)->env.spr_cb[SPR_PIR].default_value & ~(cs->nr_threads - 1))
2901 return cpu->env.spr_cb[spr].name != NULL; in ppc_has_spr()
H A Dmachine.c294 env->spr[SPR_PVR] = env->spr_cb[SPR_PVR].default_value; in cpu_post_load()
H A Dcpu_init.c7185 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { in ppc_cpu_reset_hold()
7186 ppc_spr_t *spr = &env->spr_cb[i]; in ppc_cpu_reset_hold()
7591 if (env->spr_cb[SPR_LPCR].name) { in ppc_cpu_dump_state()
7605 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ in ppc_cpu_dump_state()
7608 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ in ppc_cpu_dump_state()
H A Dkvm.c970 uint64_t id = env->spr_cb[i].one_reg_id; in kvm_arch_put_registers()
1270 uint64_t id = env->spr_cb[i].one_reg_id; in kvm_arch_get_registers()
H A Dexcp_helper.c3111 if (cenv->spr_cb[SPR_PIR].default_value == pir) { in book3s_msgsnd_common()
/openbmc/qemu/hw/ppc/
H A Dspapr_cpu_core.c272 env->spr_cb[SPR_PIR].default_value = cs->cpu_index; in spapr_realize_vcpu()
273 env->spr_cb[SPR_TIR].default_value = thread_index; in spapr_realize_vcpu()
H A Dpnv_core.c230 ppc_spr_t *pir = &env->spr_cb[SPR_PIR]; in pnv_core_cpu_realize()
231 ppc_spr_t *tir = &env->spr_cb[SPR_TIR]; in pnv_core_cpu_realize()
H A Dppc.c1508 return env->spr_cb[SPR_PIR].default_value; in ppc_cpu_pir()
1514 return env->spr_cb[SPR_TIR].default_value; in ppc_cpu_tir()
H A De500.c969 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; in ppce500_init()
/openbmc/qemu/hw/intc/
H A Dxive2.c189 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_save_os_ctx()
281 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_restore_os_ctx()
464 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive2_tctx_hw_cam_line()
H A Dxive.c1536 uint32_t pir = env->spr_cb[SPR_PIR].default_value; in xive_tctx_hw_cam_line()