Home
last modified time | relevance | path

Searched refs:set_wptr (Results 1 – 25 of 41) sorted by relevance

12

/openbmc/linux/drivers/gpu/drm/radeon/
H A Dradeon_asic.c194 .set_wptr = &r100_gfx_set_wptr,
344 .set_wptr = &r100_gfx_set_wptr,
358 .set_wptr = &r100_gfx_set_wptr,
915 .set_wptr = &r600_gfx_set_wptr,
928 .set_wptr = &r600_dma_set_wptr,
1013 .set_wptr = &uvd_v1_0_set_wptr,
1212 .set_wptr = &uvd_v1_0_set_wptr,
1319 .set_wptr = &r600_gfx_set_wptr,
1332 .set_wptr = &r600_dma_set_wptr,
1657 .set_wptr = &uvd_v1_0_set_wptr,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ring.h174 void (*set_wptr)(struct amdgpu_ring *ring); member
311 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
H A Djpeg_v2_5.c662 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
691 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
H A Dvce_v3_0.c928 .set_wptr = vce_v3_0_ring_set_wptr,
952 .set_wptr = vce_v3_0_ring_set_wptr,
H A Duvd_v6_0.c1551 .set_wptr = uvd_v6_0_ring_set_wptr,
1577 .set_wptr = uvd_v6_0_ring_set_wptr,
1606 .set_wptr = uvd_v6_0_enc_ring_set_wptr,
H A Djpeg_v3_0.c567 .set_wptr = jpeg_v3_0_dec_ring_set_wptr,
H A Dvce_v2_0.c641 .set_wptr = vce_v2_0_ring_set_wptr,
H A Duvd_v4_2.c775 .set_wptr = uvd_v4_2_ring_set_wptr,
H A Duvd_v3_1.c186 .set_wptr = uvd_v3_1_ring_set_wptr,
H A Duvd_v5_0.c883 .set_wptr = uvd_v5_0_ring_set_wptr,
H A Djpeg_v4_0.c727 .set_wptr = jpeg_v4_0_dec_ring_set_wptr,
H A Djpeg_v2_0.c769 .set_wptr = jpeg_v2_0_dec_ring_set_wptr,
H A Djpeg_v1_0.c563 .set_wptr = jpeg_v1_0_decode_ring_set_wptr,
H A Dvcn_v3_0.c1743 .set_wptr = vcn_v3_0_dec_ring_set_wptr,
1903 .set_wptr = vcn_v3_0_dec_ring_set_wptr,
2003 .set_wptr = vcn_v3_0_enc_ring_set_wptr,
H A Dsi_dma.c725 .set_wptr = si_dma_ring_set_wptr,
H A Duvd_v7_0.c1809 .set_wptr = uvd_v7_0_ring_set_wptr,
1841 .set_wptr = uvd_v7_0_enc_ring_set_wptr,
H A Dvcn_v2_0.c2019 .set_wptr = vcn_v2_0_dec_ring_set_wptr,
2049 .set_wptr = vcn_v2_0_enc_ring_set_wptr,
H A Dvcn_v1_0.c1984 .set_wptr = vcn_v1_0_dec_ring_set_wptr,
2018 .set_wptr = vcn_v1_0_enc_ring_set_wptr,
H A Dsdma_v4_4_2.c1824 .set_wptr = sdma_v4_4_2_ring_set_wptr,
1855 .set_wptr = sdma_v4_4_2_page_ring_set_wptr,
H A Dvcn_v2_5.c1579 .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1678 .set_wptr = vcn_v2_5_enc_ring_set_wptr,
H A Dsdma_v2_4.c1134 .set_wptr = sdma_v2_4_ring_set_wptr,
H A Dcik_sdma.c1246 .set_wptr = cik_sdma_ring_set_wptr,
H A Dvce_v4_0.c1109 .set_wptr = vce_v4_0_ring_set_wptr,
H A Dsdma_v4_0.c2324 .set_wptr = sdma_v4_0_ring_set_wptr,
2356 .set_wptr = sdma_v4_0_page_ring_set_wptr,
H A Dmes_v10_1.c85 .set_wptr = mes_v10_1_ring_set_wptr,

12