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Searched refs:set_parent (Results 1 – 25 of 140) sorted by relevance

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/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra-super-cclk.c40 return tegra_clk_super_ops.set_parent(hw, index); in cclk_super_set_parent()
120 .set_parent = cclk_super_set_parent,
128 .set_parent = cclk_super_set_parent,
H A Dclk-periph.c33 return mux_ops->set_parent(mux_hw, index); in clk_periph_set_parent()
137 .set_parent = clk_periph_set_parent,
151 .set_parent = clk_periph_set_parent,
161 .set_parent = clk_periph_set_parent,
/openbmc/linux/drivers/clk/actions/
H A Dowl-composite.c159 .set_parent = owl_comp_set_parent,
176 .set_parent = owl_comp_set_parent,
206 .set_parent = owl_comp_set_parent,
H A Dowl-mux.c58 .set_parent = owl_mux_set_parent,
/openbmc/linux/drivers/clk/
H A Dclk-composite.c30 return mux_ops->set_parent(mux_hw, index); in clk_composite_set_parent()
84 mux_hw && mux_ops && mux_ops->set_parent) { in clk_composite_determine_rate()
195 mux_ops->set_parent(mux_hw, index); in clk_composite_set_rate_and_parent()
197 mux_ops->set_parent(mux_hw, index); in clk_composite_set_rate_and_parent()
275 if (mux_ops->set_parent) in __clk_hw_register_composite()
276 clk_composite_ops->set_parent = clk_composite_set_parent; in __clk_hw_register_composite()
310 if (mux_ops->set_parent && rate_ops->set_rate) in __clk_hw_register_composite()
/openbmc/linux/drivers/clk/starfive/
H A Dclk-starfive-jh71x0.c259 .set_parent = jh71x0_clk_set_parent,
269 .set_parent = jh71x0_clk_set_parent,
278 .set_parent = jh71x0_clk_set_parent,
290 .set_parent = jh71x0_clk_set_parent,
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mux.c142 .set_parent = mtk_clk_mux_set_parent_setclr_lock,
152 .set_parent = mtk_clk_mux_set_parent_setclr_lock,
292 ret = mux_nb->ops->set_parent(hw, mux_nb->bypass_index); in mtk_clk_mux_notifier_cb()
296 ret = mux_nb->ops->set_parent(hw, mux_nb->original_index); in mtk_clk_mux_notifier_cb()
/openbmc/linux/drivers/clk/ti/
H A Ddpll.c30 .set_parent = &omap3_noncore_dpll_set_parent,
55 .set_parent = &omap3_noncore_dpll_set_parent,
68 .set_parent = &omap3_noncore_dpll_set_parent,
109 .set_parent = &omap3_noncore_dpll_set_parent,
121 .set_parent = &omap3_noncore_dpll_set_parent,
133 .set_parent = &omap3_noncore_dpll_set_parent,
/openbmc/linux/drivers/clk/versatile/
H A Dclk-sp810.c68 .set_parent = clk_sp810_timerclken_set_parent,
129 init.ops->set_parent(&sp810->timerclken[i].hw, 1); in clk_sp810_of_setup()
/openbmc/u-boot/include/
H A Dclk-uclass.h86 int (*set_parent)(struct clk *clk, struct clk *parent); member
/openbmc/linux/drivers/clk/pxa/
H A Dclk-pxa.h24 .set_parent = dummy_clk_set_parent, \
75 .set_parent = name ## _set_parent, \
/openbmc/linux/drivers/gpu/drm/mcde/
H A Dmcde_clk_div.c45 unsigned long *prate, bool set_parent) in mcde_clk_div_choose_div() argument
56 if (set_parent) in mcde_clk_div_choose_div()
/openbmc/linux/drivers/clk/qcom/
H A Dclk-rcg.c825 .set_parent = clk_rcg_set_parent,
836 .set_parent = clk_rcg_set_parent,
847 .set_parent = clk_rcg_set_parent,
858 .set_parent = clk_rcg_set_parent,
870 .set_parent = clk_rcg_set_parent,
882 .set_parent = clk_rcg_set_parent,
894 .set_parent = clk_rcg_set_parent,
906 .set_parent = clk_dyn_rcg_set_parent,
H A Dclk-rcg2.c485 .set_parent = clk_rcg2_set_parent,
498 .set_parent = clk_rcg2_set_parent,
511 .set_parent = clk_rcg2_set_parent,
634 .set_parent = clk_rcg2_set_parent,
692 .set_parent = clk_rcg2_set_parent,
762 .set_parent = clk_rcg2_set_parent,
853 .set_parent = clk_rcg2_set_parent,
967 .set_parent = clk_rcg2_set_parent,
1145 .set_parent = clk_rcg2_shared_set_parent,
1408 .set_parent = clk_rcg2_set_parent,
H A Dclk-regmap-mux.c54 .set_parent = mux_set_parent,
/openbmc/u-boot/drivers/clk/
H A Dclk-ti-sci.c148 ret = cops->set_parent(sci, clk->id, clk->data, parent->data); in ti_sci_clk_set_parent()
205 .set_parent = ti_sci_clk_set_parent,
/openbmc/linux/drivers/sh/clk/
H A Dcore.c523 if (clk->ops->set_parent) in clk_set_parent()
524 ret = clk->ops->set_parent(clk, parent); in clk_set_parent()
580 if (likely(clkp->ops->set_parent)) in clks_core_resume()
581 clkp->ops->set_parent(clkp, in clks_core_resume()
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-pll.c209 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3036_pll_set_params()
243 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3036_pll_set_params()
442 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3066_pll_set_params()
478 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3066_pll_set_params()
691 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3399_pll_set_params()
727 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3399_pll_set_params()
939 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW); in rockchip_rk3588_pll_set_params()
973 pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM); in rockchip_rk3588_pll_set_params()
/openbmc/linux/drivers/clk/socfpga/
H A Dclk-gate.c134 .set_parent = socfpga_clk_set_parent,
194 ops->set_parent = NULL; in socfpga_gate_init()
/openbmc/linux/drivers/clk/imx/
H A Dclk-busy.c143 ret = busy->mux_ops->set_parent(&busy->mux.hw, index); in clk_busy_mux_set_parent()
153 .set_parent = clk_busy_mux_set_parent,
/openbmc/linux/drivers/clk/sprd/
H A Dcomposite.c53 .set_parent = sprd_comp_set_parent,
H A Dmux.c73 .set_parent = sprd_mux_set_parent,
/openbmc/linux/sound/soc/codecs/
H A Dtlv320aic32x4-clk.c272 .set_parent = clk_aic32x4_pll_set_parent,
297 .set_parent = clk_aic32x4_codec_clkin_set_parent,
391 .set_parent = clk_aic32x4_bdiv_set_parent,
/openbmc/linux/drivers/clk/at91/
H A Dclk-i2s-mux.c47 .set_parent = clk_i2s_mux_set_parent,
/openbmc/linux/drivers/clk/uniphier/
H A Dclk-uniphier-mux.c52 .set_parent = uniphier_clk_mux_set_parent,

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