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Searched refs:se_mask (Results 1 – 25 of 43) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.c39 enc110->se_shift->field_name, enc110->se_mask->field_name
321 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN) in dce110_stream_encoder_dp_set_stream_attribute()
324 if (enc110->se_mask->DP_VID_N_MUL) in dce110_stream_encoder_dp_set_stream_attribute()
438 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) in dce110_stream_encoder_dp_set_stream_attribute()
557 if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { in dce110_stream_encoder_hdmi_set_stream_attribute()
606 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { in dce110_stream_encoder_hdmi_set_stream_attribute()
731 if (enc110->se_mask->HDMI_AVI_INFO_CONT && in dce110_stream_encoder_update_hdmi_info_packets()
732 enc110->se_mask->HDMI_AVI_INFO_SEND) { in dce110_stream_encoder_update_hdmi_info_packets()
766 if (enc110->se_mask->HDMI_AVI_INFO_CONT && in dce110_stream_encoder_update_hdmi_info_packets()
767 enc110->se_mask->HDMI_AVI_INFO_SEND) { in dce110_stream_encoder_update_hdmi_info_packets()
[all …]
H A Ddce_stream_encoder.h699 const struct dce_stream_encoder_mask *se_mask; member
709 const struct dce_stream_encoder_mask *se_mask);
/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v11.c48 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; in update_cu_mask() local
74 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); in update_cu_mask()
76 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
77 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
78 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
79 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
80 m->compute_static_thread_mgmt_se4 = se_mask[4]; in update_cu_mask()
81 m->compute_static_thread_mgmt_se5 = se_mask[5]; in update_cu_mask()
82 m->compute_static_thread_mgmt_se6 = se_mask[6]; in update_cu_mask()
83 m->compute_static_thread_mgmt_se7 = se_mask[7]; in update_cu_mask()
H A Dkfd_mqd_manager_cik.c49 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ in update_cu_mask() local
55 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); in update_cu_mask()
58 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
59 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
60 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
61 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
H A Dkfd_mqd_manager_v9.c66 uint32_t se_mask[KFD_MAX_NUM_SE] = {0}; in update_cu_mask() local
72 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, inst); in update_cu_mask()
76 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
77 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
78 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
79 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
81 m->compute_static_thread_mgmt_se4 = se_mask[4]; in update_cu_mask()
82 m->compute_static_thread_mgmt_se5 = se_mask[5]; in update_cu_mask()
83 m->compute_static_thread_mgmt_se6 = se_mask[6]; in update_cu_mask()
84 m->compute_static_thread_mgmt_se7 = se_mask[7]; in update_cu_mask()
H A Dkfd_mqd_manager_vi.c52 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ in update_cu_mask() local
58 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); in update_cu_mask()
61 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
62 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
63 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
64 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
H A Dkfd_mqd_manager_v10.c49 uint32_t se_mask[4] = {0}; /* 4 is the max # of SEs */ in update_cu_mask() local
55 minfo->cu_mask.ptr, minfo->cu_mask.count, se_mask, 0); in update_cu_mask()
58 m->compute_static_thread_mgmt_se0 = se_mask[0]; in update_cu_mask()
59 m->compute_static_thread_mgmt_se1 = se_mask[1]; in update_cu_mask()
60 m->compute_static_thread_mgmt_se2 = se_mask[2]; in update_cu_mask()
61 m->compute_static_thread_mgmt_se3 = se_mask[3]; in update_cu_mask()
H A Dkfd_mqd_manager.c100 uint32_t *se_mask, uint32_t inst) in mqd_symmetrically_map_cu_mask() argument
190 se_mask[i] = 0; in mqd_symmetrically_map_cu_mask()
198 se_mask[se] |= en_mask << (cu + sh * 16); in mqd_symmetrically_map_cu_mask()
H A Dkfd_mqd_manager.h141 uint32_t *se_mask, uint32_t inst);
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dio_stream_encoder.c44 enc1->se_shift->field_name, enc1->se_mask->field_name
483 const struct dcn10_stream_encoder_mask *se_mask) in dcn314_dio_stream_encoder_construct() argument
493 enc1->se_mask = se_mask; in dcn314_dio_stream_encoder_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dio_stream_encoder.c43 enc1->se_shift->field_name, enc1->se_mask->field_name
514 const struct dcn10_stream_encoder_mask *se_mask) in dcn32_dio_stream_encoder_construct() argument
524 enc1->se_mask = se_mask; in dcn32_dio_stream_encoder_construct()
H A Ddcn32_dio_stream_encoder.h195 const struct dcn10_stream_encoder_mask *se_mask);
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_stream_encoder.c43 enc1->se_shift->field_name, enc1->se_mask->field_name
650 const struct dcn10_stream_encoder_mask *se_mask) in dcn20_stream_encoder_construct() argument
658 enc1->se_mask = se_mask; in dcn20_stream_encoder_construct()
H A Ddcn20_stream_encoder.h97 const struct dcn10_stream_encoder_mask *se_mask);
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dio_stream_encoder.c44 enc1->se_shift->field_name, enc1->se_mask->field_name
889 const struct dcn10_stream_encoder_mask *se_mask) in dcn30_dio_stream_encoder_construct() argument
899 enc1->se_mask = se_mask; in dcn30_dio_stream_encoder_construct()
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v7_0.c1643 unsigned se_mask[4]; in gfx_v7_0_write_harvested_raster_configs() local
1646 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; in gfx_v7_0_write_harvested_raster_configs()
1647 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; in gfx_v7_0_write_harvested_raster_configs()
1648 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; in gfx_v7_0_write_harvested_raster_configs()
1649 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; in gfx_v7_0_write_harvested_raster_configs()
1655 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || in gfx_v7_0_write_harvested_raster_configs()
1656 (!se_mask[2] && !se_mask[3]))) { in gfx_v7_0_write_harvested_raster_configs()
1659 if (!se_mask[0] && !se_mask[1]) { in gfx_v7_0_write_harvested_raster_configs()
1674 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { in gfx_v7_0_write_harvested_raster_configs()
1677 if (!se_mask[idx]) { in gfx_v7_0_write_harvested_raster_configs()
H A Dgfx_v6_0.c1367 unsigned se_mask[4]; in gfx_v6_0_write_harvested_raster_configs() local
1370 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; in gfx_v6_0_write_harvested_raster_configs()
1371 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; in gfx_v6_0_write_harvested_raster_configs()
1372 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; in gfx_v6_0_write_harvested_raster_configs()
1373 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; in gfx_v6_0_write_harvested_raster_configs()
1385 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { in gfx_v6_0_write_harvested_raster_configs()
1388 if (!se_mask[idx]) in gfx_v6_0_write_harvested_raster_configs()
H A Dgfx_v8_0.c3492 unsigned se_mask[4]; in gfx_v8_0_write_harvested_raster_configs() local
3495 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3496 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3497 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3498 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask; in gfx_v8_0_write_harvested_raster_configs()
3504 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || in gfx_v8_0_write_harvested_raster_configs()
3505 (!se_mask[2] && !se_mask[3]))) { in gfx_v8_0_write_harvested_raster_configs()
3508 if (!se_mask[0] && !se_mask[1]) { in gfx_v8_0_write_harvested_raster_configs()
3523 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) { in gfx_v8_0_write_harvested_raster_configs()
3526 if (!se_mask[idx]) { in gfx_v8_0_write_harvested_raster_configs()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_stream_encoder.c43 enc1->se_shift->field_name, enc1->se_mask->field_name
1617 const struct dcn10_stream_encoder_mask *se_mask) in dcn10_stream_encoder_construct() argument
1625 enc1->se_mask = se_mask; in dcn10_stream_encoder_construct()
H A Ddcn10_stream_encoder.h601 const struct dcn10_stream_encoder_mask *se_mask; member
611 const struct dcn10_stream_encoder_mask *se_mask);
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce100/
H A Ddce100_resource.c249 static const struct dce_stream_encoder_mask se_mask = { variable
487 &stream_enc_regs[eng_id], &se_shift, &se_mask); in dce100_stream_encoder_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce120/
H A Ddce120_resource.c291 static const struct dce_stream_encoder_mask se_mask = { variable
769 &se_shift, &se_mask); in dce120_stream_encoder_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_resource.c360 static const struct dcn10_stream_encoder_mask se_mask = { variable
862 &se_shift, &se_mask); in dcn201_stream_encoder_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce80/
H A Ddce80_resource.c266 static const struct dce_stream_encoder_mask se_mask = { variable
610 &se_shift, &se_mask); in dce80_stream_encoder_create()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce112/
H A Ddce112_resource.c302 static const struct dce_stream_encoder_mask se_mask = { variable
517 &se_shift, &se_mask); in dce112_stream_encoder_create()

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