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Searched refs:sdr_pll (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_gen5.c94 writel(0, &clock_manager_base->sdr_pll.en); in cm_basic_init()
112 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
129 readl(&clock_manager_base->sdr_pll.vco); in cm_basic_init()
201 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
225 &clock_manager_base->sdr_pll.ddrdqclk); in cm_basic_init()
249 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
261 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
268 &clock_manager_base->sdr_pll.ddrdqsclk, in cm_basic_init()
275 &clock_manager_base->sdr_pll.ddr2xdqsclk, in cm_basic_init()
281 &clock_manager_base->sdr_pll.ddrdqclk, in cm_basic_init()
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/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h109 struct socfpga_clock_manager_sdr_pll sdr_pll; member