Lines Matching refs:sdr_pll
94 writel(0, &clock_manager_base->sdr_pll.en); in cm_basic_init()
112 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
129 readl(&clock_manager_base->sdr_pll.vco); in cm_basic_init()
138 writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); in cm_basic_init()
201 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
219 &clock_manager_base->sdr_pll.ddrdqsclk); in cm_basic_init()
222 &clock_manager_base->sdr_pll.ddr2xdqsclk); in cm_basic_init()
225 &clock_manager_base->sdr_pll.ddrdqclk); in cm_basic_init()
228 &clock_manager_base->sdr_pll.s2fuser2clk); in cm_basic_init()
249 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
261 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
268 &clock_manager_base->sdr_pll.ddrdqsclk, in cm_basic_init()
275 &clock_manager_base->sdr_pll.ddr2xdqsclk, in cm_basic_init()
281 &clock_manager_base->sdr_pll.ddrdqclk, in cm_basic_init()
287 &clock_manager_base->sdr_pll.s2fuser2clk, in cm_basic_init()
308 writel(~0, &clock_manager_base->sdr_pll.en); in cm_basic_init()
377 reg = readl(&clock_manager_base->sdr_pll.vco); in cm_get_sdram_clk_hz()
388 reg = readl(&clock_manager_base->sdr_pll.vco); in cm_get_sdram_clk_hz()
395 reg = readl(&clock_manager_base->sdr_pll.ddrdqsclk); in cm_get_sdram_clk_hz()