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Searched refs:sar (Results 1 – 25 of 190) sorted by relevance

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/openbmc/linux/drivers/clk/mvebu/
H A Dorion.c30 u32 opt = (readl(sar) >> SAR_MV88F5181_TCLK_FREQ) & in mv88f5181_get_tclk_freq()
47 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & in mv88f5181_get_cpu_freq()
62 u32 opt = (readl(sar) >> SAR_MV88F5181_CPU_FREQ) & in mv88f5181_get_clk_ratio()
100 u32 opt = (readl(sar) >> SAR_MV88F5182_TCLK_FREQ) & in mv88f5182_get_tclk_freq()
115 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) & in mv88f5182_get_cpu_freq()
130 u32 opt = (readl(sar) >> SAR_MV88F5182_CPU_FREQ) & in mv88f5182_get_clk_ratio()
174 u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) & in mv88f5281_get_cpu_freq()
187 u32 opt = (readl(sar) >> SAR_MV88F5281_CPU_FREQ) & in mv88f5281_get_clk_ratio()
225 u32 opt = (readl(sar) >> SAR_MV88F6183_TCLK_FREQ) & in mv88f6183_get_tclk_freq()
240 u32 opt = (readl(sar) >> SAR_MV88F6183_CPU_FREQ) & in mv88f6183_get_cpu_freq()
[all …]
H A Darmada-370.c45 static u32 __init a370_get_tclk_freq(void __iomem *sar) in a370_get_tclk_freq() argument
49 tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) & in a370_get_tclk_freq()
64 static u32 __init a370_get_cpu_freq(void __iomem *sar) in a370_get_cpu_freq() argument
69 cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) & in a370_get_cpu_freq()
114 void __iomem *sar, int id, int *mult, int *div) in a370_get_clk_ratio() argument
116 u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) & in a370_get_clk_ratio()
135 static bool a370_is_sscg_enabled(void __iomem *sar) in a370_is_sscg_enabled() argument
137 return !(readl(sar) & SARL_A370_SSCG_ENABLE); in a370_is_sscg_enabled()
H A Darmada-39x.c45 static u32 __init armada_39x_get_tclk_freq(void __iomem *sar) in armada_39x_get_tclk_freq() argument
49 tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) & in armada_39x_get_tclk_freq()
68 static u32 __init armada_39x_get_cpu_freq(void __iomem *sar) in armada_39x_get_cpu_freq() argument
72 cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) & in armada_39x_get_cpu_freq()
92 void __iomem *sar, int id, int *mult, int *div) in armada_39x_get_clk_ratio() argument
110 static u32 __init armada_39x_refclk_ratio(void __iomem *sar) in armada_39x_refclk_ratio() argument
112 if (readl(sar + SARH) & SARH_A390_REFCLK_FREQ) in armada_39x_refclk_ratio()
H A Dkirkwood.c86 static u32 __init kirkwood_get_tclk_freq(void __iomem *sar) in kirkwood_get_tclk_freq() argument
88 u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) & in kirkwood_get_tclk_freq()
108 static u32 __init kirkwood_get_cpu_freq(void __iomem *sar) in kirkwood_get_cpu_freq() argument
110 u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar)); in kirkwood_get_cpu_freq()
127 void __iomem *sar, int id, int *mult, int *div) in kirkwood_get_clk_ratio() argument
132 u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar)); in kirkwood_get_clk_ratio()
139 u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) & in kirkwood_get_clk_ratio()
155 static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar) in mv88f6180_get_cpu_freq() argument
167 void __iomem *sar, int id, int *mult, int *div) in mv88f6180_get_clk_ratio() argument
179 u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & in mv88f6180_get_clk_ratio()
[all …]
H A Ddove.c87 static u32 __init dove_get_tclk_freq(void __iomem *sar) in dove_get_tclk_freq() argument
89 u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) & in dove_get_tclk_freq()
106 static u32 __init dove_get_cpu_freq(void __iomem *sar) in dove_get_cpu_freq() argument
108 u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) & in dove_get_cpu_freq()
126 void __iomem *sar, int id, int *mult, int *div) in dove_get_clk_ratio() argument
131 u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) & in dove_get_clk_ratio()
139 u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) & in dove_get_clk_ratio()
H A Dcommon.h28 u32 (*get_tclk_freq)(void __iomem *sar);
29 u32 (*get_cpu_freq)(void __iomem *sar);
30 void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
31 u32 (*get_refclk_freq)(void __iomem *sar);
32 bool (*is_sscg_enabled)(void __iomem *sar);
H A Darmada-xp.c48 static u32 __init axp_get_tclk_freq(void __iomem *sar) in axp_get_tclk_freq() argument
68 static u32 __init axp_get_cpu_freq(void __iomem *sar) in axp_get_cpu_freq() argument
73 cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) & in axp_get_cpu_freq()
79 cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) & in axp_get_cpu_freq()
124 void __iomem *sar, int id, int *mult, int *div) in axp_get_clk_ratio() argument
126 u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) & in axp_get_clk_ratio()
132 opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) & in axp_get_clk_ratio()
H A Darmada-375.c50 static u32 __init armada_375_get_tclk_freq(void __iomem *sar) in armada_375_get_tclk_freq() argument
54 tclk_freq_select = ((readl(sar) >> SAR1_A375_TCLK_FREQ_OPT) & in armada_375_get_tclk_freq()
71 static u32 __init armada_375_get_cpu_freq(void __iomem *sar) in armada_375_get_cpu_freq() argument
75 cpu_freq_select = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) & in armada_375_get_cpu_freq()
115 void __iomem *sar, int id, int *mult, int *div) in armada_375_get_clk_ratio() argument
117 u32 opt = ((readl(sar) >> SAR1_A375_CPU_DDR_L2_FREQ_OPT) & in armada_375_get_clk_ratio()
H A Darmada-38x.c37 static u32 __init armada_38x_get_tclk_freq(void __iomem *sar) in armada_38x_get_tclk_freq() argument
41 tclk_freq_select = ((readl(sar) >> SAR_A380_TCLK_FREQ_OPT) & in armada_38x_get_tclk_freq()
54 static u32 __init armada_38x_get_cpu_freq(void __iomem *sar) in armada_38x_get_cpu_freq() argument
58 cpu_freq_select = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) & in armada_38x_get_cpu_freq()
99 void __iomem *sar, int id, int *mult, int *div) in armada_38x_get_clk_ratio() argument
101 u32 opt = ((readl(sar) >> SAR_A380_CPU_DDR_L2_FREQ_OPT) & in armada_38x_get_clk_ratio()
H A Dmv98dx3236.c44 static u32 __init mv98dx3236_get_tclk_freq(void __iomem *sar) in mv98dx3236_get_tclk_freq() argument
68 static u32 __init mv98dx3236_get_cpu_freq(void __iomem *sar) in mv98dx3236_get_cpu_freq() argument
73 cpu_freq_select = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) & in mv98dx3236_get_cpu_freq()
118 void __iomem *sar, int id, int *mult, int *div) in mv98dx3236_get_clk_ratio() argument
120 u32 opt = ((readl(sar) >> SAR1_MV98DX3236_CPU_DDR_MPLL_FREQ_OPT) & in mv98dx3236_get_clk_ratio()
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Dsar.c12 const struct rtw_sar *sar = &hal->sar; in rtw_query_sar() local
14 switch (sar->src) { in rtw_query_sar()
28 struct rtw_sar *sar = &hal->sar; in rtw_apply_sar() local
30 if (sar->src != RTW_SAR_SOURCE_NONE && new->src != sar->src) { in rtw_apply_sar()
35 *sar = *new; in rtw_apply_sar()
50 tmp = fct > txgi ? sar >> (fct - txgi) : sar << (txgi - fct); in rtw_sar_to_phy()
74 const struct cfg80211_sar_specs *sar) in rtw_set_sar_specs() argument
82 if (sar->type != NL80211_SAR_TYPE_POWER) in rtw_set_sar_specs()
88 for (i = 0; i < sar->num_sub_specs; i++) { in rtw_set_sar_specs()
89 idx = sar->sub_specs[i].freq_range_index; in rtw_set_sar_specs()
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/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_sar.S3 test_suite sar
24 wsr a2, sar
28 rsr a3, sar
33 test sar
34 tests_sar sar
43 rsr a3, sar
58 rsr a3, sar
73 rsr a3, sar
88 rsr a3, sar
102 rsr a3, sar
H A Dtest_shift.S96 wsr a2, sar
124 wsr a2, sar
154 wsr a2, sar
185 wsr a2, sar
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dnuvoton,nau8824.yaml64 nuvoton,sar-threshold-num:
72 nuvoton,sar-threshold:
88 nuvoton,sar-hysteresis:
94 nuvoton,sar-voltage:
109 nuvoton,sar-compare-time:
120 nuvoton,sar-sampling-time:
172 nuvoton,sar-threshold-num = <4>;
175 nuvoton,sar-hysteresis = <0>;
176 nuvoton,sar-voltage = <6>;
177 nuvoton,sar-compare-time = <1>;
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H A Dnuvoton,nau8825.yaml78 nuvoton,sar-threshold-num:
86 nuvoton,sar-threshold:
102 nuvoton,sar-hysteresis:
108 nuvoton,sar-voltage:
123 nuvoton,sar-compare-time:
134 nuvoton,sar-sampling-time:
225 nuvoton,sar-threshold-num = <4>;
227 nuvoton,sar-hysteresis = <1>;
228 nuvoton,sar-voltage = <0>;
229 nuvoton,sar-compare-time = <0>;
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/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Dsar.c148 _d->sar._cfg_name = *(_cfg_data); \
149 _d->sar.src = _s; \
189 const enum rtw89_sar_sources src = rtwdev->sar.src; in rtw89_query_sar()
228 const enum rtw89_sar_sources src = rtwdev->sar.src; in rtw89_print_sar()
272 const struct rtw89_sar_cfg_common *sar) in rtw89_apply_sar_common() argument
279 src = rtwdev->sar.src; in rtw89_apply_sar_common()
317 const struct cfg80211_sar_specs *sar) in rtw89_ops_set_sar_specs() argument
327 if (sar->type != NL80211_SAR_TYPE_POWER) in rtw89_ops_set_sar_specs()
332 for (i = 0; i < sar->num_sub_specs; i++) { in rtw89_ops_set_sar_specs()
333 idx = sar->sub_specs[i].freq_range_index; in rtw89_ops_set_sar_specs()
[all …]
/openbmc/linux/arch/sh/drivers/dma/
H A Ddma-g2.c97 if (chan->sar & 31) { in g2_xfer_dma()
98 printk("g2dma: unaligned source 0x%lx\n", chan->sar); in g2_xfer_dma()
117 flush_icache_range((unsigned long)chan->sar, chan->count); in g2_xfer_dma()
122 g2_dma->channel[chan_nr].root_addr = chan->sar & 0x1fffffe0; in g2_xfer_dma()
/openbmc/linux/arch/parisc/include/uapi/asm/
H A Dptrace.h35 unsigned long sar; /* CR11 */ member
56 unsigned long sar; /* CR11 */ member
/openbmc/linux/drivers/dma/dw-edma/
H A Ddw-hdma-v0-core.c156 u32 control, u32 size, u64 sar, u64 dar) in dw_hdma_v0_write_ll_data() argument
165 lli->sar.reg = sar; in dw_hdma_v0_write_ll_data()
172 writeq(sar, &lli->sar.reg); in dw_hdma_v0_write_ll_data()
205 child->sar, child->dar); in dw_hdma_v0_core_write_chunk()
H A Ddw-hdma-v0-regs.h47 } sar; member
107 } sar; member
/openbmc/linux/arch/parisc/kernel/
H A Dkgdb.c81 gr->sar = regs->sar; in pt_regs_to_gdb_regs()
112 regs->sar = gr->sar; in gdb_regs_to_pt_regs()
H A Dperf_asm.S154 shrpd ret0,%r0,%sar,%r1
178 shrpd ret0,%r0,%sar,%r1
274 shrpd ret0,%r0,%sar,%r1
286 shrpd ret0,%r0,%sar,%r1
322 shrpd ret0,%r0,%sar,%r1
358 shrpd ret0,%r0,%sar,%r1
370 shrpd ret0,%r0,%sar,%r1
466 shrpd ret0,%r0,%sar,%r1
478 shrpd ret0,%r0,%sar,%r1
514 shrpd ret0,%r0,%sar,%r1
H A Dsignal32.c100 regs->sar = ((u64)compat_regt << 32) | (u64)compat_reg; in restore_sigcontext32()
102 DBG(2,"restore_sigcontext32: sar is %#lx\n", regs->sar); in restore_sigcontext32()
238 compat_reg = (compat_uint_t)(regs->sar); in setup_sigcontext32()
242 compat_reg = (compat_uint_t)(regs->sar >> 32); in setup_sigcontext32()
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_dma.h38 uint sar; /* DMA source address register */ member
90 uint sar; /* DMA source address register */ member
/openbmc/linux/arch/parisc/lib/
H A Dlusercopy.S295 shrpw a2, a3, %sar, t0
301 shrpw a3, a0, %sar, t0
307 shrpw a0, a1, %sar, t0
313 shrpw a1, a2, %sar, t0
320 shrpw a2, a3, %sar, t0

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