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Searched refs:rtl8xxxu_write32 (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A Drtl8xxxu_8192e.c543 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8192e_set_tx_power()
548 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8192e_set_tx_power()
554 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); in rtl8192e_set_tx_power()
555 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); in rtl8192e_set_tx_power()
564 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); in rtl8192e_set_tx_power()
565 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); in rtl8192e_set_tx_power()
566 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); in rtl8192e_set_tx_power()
567 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); in rtl8192e_set_tx_power()
575 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); in rtl8192e_set_tx_power()
580 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8192e_set_tx_power()
[all …]
H A Drtl8xxxu_8723b.c418 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8723b_set_tx_power()
423 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8723b_set_tx_power()
429 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); in rtl8723b_set_tx_power()
430 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); in rtl8723b_set_tx_power()
439 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); in rtl8723b_set_tx_power()
440 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); in rtl8723b_set_tx_power()
523 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); in rtl8723bu_init_phy_bb()
559 rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32); in rtl8723bu_phy_init_antenna_selection()
563 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); in rtl8723bu_phy_init_antenna_selection()
567 rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); in rtl8723bu_phy_init_antenna_selection()
[all …]
H A Drtl8xxxu_8192f.c513 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xf8fe0001); in rtl8192f_revise_cck_tx_psf()
515 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C); in rtl8192f_revise_cck_tx_psf()
517 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667); in rtl8192f_revise_cck_tx_psf()
520 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001); in rtl8192f_revise_cck_tx_psf()
522 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x0000B81C); in rtl8192f_revise_cck_tx_psf()
524 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x00003667); in rtl8192f_revise_cck_tx_psf()
527 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001); in rtl8192f_revise_cck_tx_psf()
528 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C); in rtl8192f_revise_cck_tx_psf()
530 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667); in rtl8192f_revise_cck_tx_psf()
695 rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); in rtl8192fu_init_aggregation()
[all …]
H A Drtl8xxxu_8188f.c387 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); in rtl8188f_set_tx_power()
392 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); in rtl8188f_set_tx_power()
398 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); in rtl8188f_set_tx_power()
399 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); in rtl8188f_set_tx_power()
409 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); in rtl8188f_set_tx_power()
410 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); in rtl8188f_set_tx_power()
411 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); in rtl8188f_set_tx_power()
412 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); in rtl8188f_set_tx_power()
450 rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); in rtl8188f_spur_calibration()
455 rtl8xxxu_write32(priv, REG_OFDM0_RX_D_SYNC_PATH, val32); in rtl8188f_spur_calibration()
[all …]
H A Drtl8xxxu_8710b.c493 rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_ADDR_8710B, addr); in rtl8710b_indirect_read32()
494 rtl8xxxu_write32(priv, REG_EFUSE_INDIRECT_CTRL_8710B, NORMAL_REG_READ_OFFSET); in rtl8710b_indirect_read32()
528 rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_ADDR_8710B, addr); in rtl8710b_indirect_write32()
529 rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_DATA_8710B, val); in rtl8710b_indirect_write32()
530 rtl8xxxu_write32(priv, REG_EFUSE_INDIRECT_CTRL_8710B, NORMAL_REG_WRITE_OFFSET); in rtl8710b_indirect_write32()
562 rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_ADDR_8710B, offset); in rtl8710b_read_efuse8()
564 rtl8xxxu_write32(priv, REG_EFUSE_INDIRECT_CTRL_8710B, EFUSE_READ_OFFSET); in rtl8710b_read_efuse8()
673 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C); in rtl8710b_revise_cck_tx_psf()
674 rtl8xxxu_write32(priv, REG_CCK0_DEBUG_PORT, 0x00008810); in rtl8710b_revise_cck_tx_psf()
675 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667); in rtl8710b_revise_cck_tx_psf()
[all …]
H A Drtl8xxxu_8188e.c459 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188eu_config_channel()
463 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); in rtl8188eu_config_channel()
482 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); in rtl8188eu_config_channel()
486 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); in rtl8188eu_config_channel()
490 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); in rtl8188eu_config_channel()
500 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); in rtl8188eu_config_channel()
508 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); in rtl8188eu_config_channel()
516 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); in rtl8188eu_config_channel()
632 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1c); in rtl8188eu_iqk_path_a()
633 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x30008c1c); in rtl8188eu_iqk_path_a()
[all …]
H A Drtl8xxxu_core.c768 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val) in rtl8xxxu_write32() function
832 return rtl8xxxu_write32(priv, addr, val32); in rtl8xxxu_write32_set()
841 return rtl8xxxu_write32(priv, addr, val32); in rtl8xxxu_write32_clear()
853 return rtl8xxxu_write32(priv, addr, new); in rtl8xxxu_write32_mask()
924 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); in rtl8xxxu_read_rfreg()
928 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32); in rtl8xxxu_read_rfreg()
932 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); in rtl8xxxu_read_rfreg()
970 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); in rtl8xxxu_write_rfreg()
974 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr); in rtl8xxxu_write_rfreg()
985 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); in rtl8xxxu_write_rfreg()
[all …]
H A Drtl8xxxu_8723a.c259 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d); in rtl8723au_init_phy_rf()
260 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); in rtl8723au_init_phy_rf()
261 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82); in rtl8723au_init_phy_rf()
262 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); in rtl8723au_init_phy_rf()
329 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); in rtl8723a_emu_to_active()
400 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32); in rtl8723au_power_on()
429 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32); in rtl8723a_set_crystal_cap()
H A Drtl8xxxu_8192c.c581 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); in rtl8192cu_power_on()
H A Drtl8xxxu.h2027 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val);