| /openbmc/qemu/target/mips/tcg/ |
| H A D | dsp_helper.c | 1257 uint8_t rt3, rt2, rt1, rt0; \
1261 MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \
1264 tempC = ((uint16_t)rs2 - (uint16_t)rt2 + var) >> 1; \
1430 uint8_t rt6, rt4, rt2, rt0; in helper_precr_ob_qh() local
1439 rt2 = (rt >> 16) & MIPSDSP_Q0; in helper_precr_ob_qh()
1445 ((uint64_t)rt2 << 8) | (uint64_t)rt0; in helper_precr_ob_qh()
1461 uint16_t rt3, rt2, rt1, rt0; \
1465 MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \
1468 tempD = rt2 << var; \
1490 uint8_t rt6, rt4, rt2, rt0; in helper_precrq_ob_qh() local
[all …]
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| /openbmc/qemu/target/arm/tcg/ |
| H A D | t32.decode | 41 &strex !extern rn rd rt rt2 imm
42 &ldrex !extern rn rt rt2 imm
49 &mcrr !extern cp opc1 crm rt rt2
550 &ldst_ri2 p w u rn rt rt2 imm
551 @ldstd_ri8 .... .... u:1 ... rn:4 rt:4 rt2:4 ........ \
569 &strex rt2=15 imm=%imm8x4
571 &strex rt2=15 imm=0
572 @strex_d .... .... .... rn:4 rt:4 rt2:4 .... rd:4 \
576 &ldrex rt2=15 imm=%imm8x4
578 &ldrex rt2=15 imm=0
[all …]
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| H A D | a32.decode | 44 &strex rn rd rt rt2 imm
45 &ldrex rn rt rt2 imm
51 &mcrr cp opc1 crm rt rt2
368 @swp ---- .... .... rn:4 rt:4 .... .... rt2:4
375 # Note rt2 for STREXD/LDREXD is set by the helper after checking rt is even.
378 &strex imm=0 rt2=15
380 &ldrex imm=0 rt2=15
382 &ldrex imm=0 rt2=15
547 @mcrr ---- .... .... rt2:4 rt:4 cp:4 opc1:4 crm:4 &mcrr
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| H A D | translate.c | 2924 bool isread, int rt, int rt2) in do_coproc_insn() argument
2944 syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, in do_coproc_insn()
2953 syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, in do_coproc_insn()
3120 store_reg(s, rt2, tmp); in do_coproc_insn()
3154 tmphi = load_reg(s, rt2); in do_coproc_insn()
3253 static void gen_load_exclusive(DisasContext *s, int rt, int rt2, in gen_load_exclusive() argument
3282 store_reg(s, rt2, tmp2); in gen_load_exclusive()
3297 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, in gen_store_exclusive() argument
3326 t2 = load_reg(s, rt2); in gen_store_exclusive()
3613 false, a->rt, a->rt2); in trans_MCRR()
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| H A D | vfp.decode | 80 VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=%vm_sp
81 VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... vm=%vm_dp
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| H A D | translate-mve.c | 2193 a->rt == 13 || a->rt == 15 || a->rt2 == 13 || a->rt2 == 15 || in DO_VABAV()
2194 a->rt == a->rt2) { in DO_VABAV()
2213 store_reg(s, a->rt2, tmp); in DO_VABAV()
2236 a->rt == 13 || a->rt == 15 || a->rt2 == 13 || a->rt2 == 15) { in trans_VMOV_from_2gp()
2252 tmp = load_reg(s, a->rt2); in trans_VMOV_from_2gp()
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| H A D | a64.decode | 314 &stxr rn rt rt2 rs sz lasr
316 @stxr sz:2 ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr
319 @stxp .. ...... ... rs:5 lasr:1 rt2:5 rn:5 rt:5 &stxr sz=%imm1_30_p2
347 &ldstpair rt2 rt rn imm sz sign w p
348 @ldstpair .. ... . ... . imm:s7 rt2:5 rn:5 rt:5 &ldstpair
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| H A D | mve.decode | 207 VMOV_to_2gp 1110 1100 0 . 00 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=%qd
208 VMOV_from_2gp 1110 1100 0 . 01 rt2:4 ... 0 1111 000 idx:1 rt:4 qd=%qd
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| H A D | translate-a64.c | 2880 static void gen_load_exclusive(DisasContext *s, int rt, int rt2, int rn, in gen_load_exclusive() argument
2898 tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 32, 32); in gen_load_exclusive()
2901 tcg_gen_extract_i64(cpu_reg(s, rt2), cpu_exclusive_val, 0, 32); in gen_load_exclusive()
2916 tcg_gen_mov_i64(cpu_reg(s, rt2), cpu_exclusive_high); in gen_load_exclusive()
2925 static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, in gen_store_exclusive() argument
2987 tcg_gen_concat32_i64(tmp, cpu_reg(s, rt), cpu_reg(s, rt2)); in gen_store_exclusive()
2989 tcg_gen_concat32_i64(tmp, cpu_reg(s, rt2), cpu_reg(s, rt)); in gen_store_exclusive()
3001 tcg_gen_concat_i64_i128(t16, cpu_reg(s, rt), cpu_reg(s, rt2)); in gen_store_exclusive()
3005 tcg_gen_concat_i64_i128(t16, cpu_reg(s, rt2), cpu_reg(s, rt)); in gen_store_exclusive()
3149 gen_store_exclusive(s, a->rs, a->rt, a->rt2, a->rn, a->sz, false); in trans_STXR()
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| H A D | translate-vfp.c | 977 store_reg(s, a->rt2, tmp); in trans_VMOV_64_sp()
982 tmp = load_reg(s, a->rt2); in trans_VMOV_64_sp()
1018 store_reg(s, a->rt2, tmp); in trans_VMOV_64_dp()
1023 tmp = load_reg(s, a->rt2); in trans_VMOV_64_dp()
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| /openbmc/qemu/target/arm/ |
| H A D | syndrome.h | 193 int rt, int rt2, int isread, in syn_cp14_rrt_trap() argument
199 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; in syn_cp14_rrt_trap()
203 int rt, int rt2, int isread, in syn_cp15_rrt_trap() argument
209 | (rt2 << 10) | (rt << 5) | (crm << 1) | isread; in syn_cp15_rrt_trap()
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| /openbmc/qemu/docs/devel/ |
| H A D | decodetree.rst | 232 or 000010 rt2:5 r1:5 cf:4 001001 0 rt:5
237 is discarded and so the instruction has no effect. When the *rt2*
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| /openbmc/qemu/target/ppc/translate/ |
| H A D | vsx-impl.c.inc | 2184 int rt1, rt2;
2195 rt2 = rt;
2198 rt2 = rt + 1;
2206 get_vsr_full(data, rt2);
2215 set_vsr_full(rt2, data);
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| /openbmc/qemu/tcg/aarch64/ |
| H A D | tcg-target.c.inc | 677 TCGReg rt, TCGReg rt2, TCGReg rn)
679 tcg_out32(s, insn | rs << 16 | rt2 << 10 | rn << 5 | rt);
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| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-connectivity/krb5/krb5/ |
| H A D | 0001-Eliminate-old-style-function-declarations.patch | 10574 ssrt **rt1, **rt2;
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