| /openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | fsl_lsch2_serdes.c | 200 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
203 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
206 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
208 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
216 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
219 out_be32(&serdes2_base->bank[i].rstctl, reg); in setup_serdes_volt()
222 reg = in_be32(&serdes2_base->bank[i].rstctl); in setup_serdes_volt()
224 out_be32(&serdes2_base->bank[i].rstctl, reg); in setup_serdes_volt()
263 reg = in_be32(&serdes1_base->bank[i].rstctl); in setup_serdes_volt()
265 out_be32(&serdes1_base->bank[i].rstctl, reg); in setup_serdes_volt()
[all …]
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| H A D | fsl_lsch3_serdes.c | 313 clrbits_le32(&serdes_base->bank[i].rstctl, in do_pll_reset()
317 setbits_le32(&serdes_base->bank[i].rstctl, in do_pll_reset()
349 setbits_le32(&serdes_base->bank[i].rstctl, in do_pll_reset_done()
361 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_SDEN); in do_serdes_enable()
364 setbits_le32(&serdes_base->bank[i].rstctl, RSTCTL_PLLRST_B); in do_serdes_enable()
381 setbits_le32(&serdes_base->bank[i].rstctl, in do_pll_lock()
385 setbits_le32(&serdes_base->bank[i].rstctl, in do_pll_lock()
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| /openbmc/u-boot/board/freescale/b4860qds/ |
| H A D | b4860qds.c | 604 clrbits_be32(&srds_regs->bank[pll_num].rstctl, in calibrate_pll()
607 clrbits_be32(&srds_regs->bank[pll_num].rstctl, in calibrate_pll()
610 setbits_be32(&srds_regs->bank[pll_num].rstctl, in calibrate_pll()
876 clrbits_be32(&srds_regs->bank[i].rstctl, in config_serdes1_refclks()
879 clrbits_be32(&srds_regs->bank[i].rstctl, in config_serdes1_refclks()
882 setbits_be32(&srds_regs->bank[i].rstctl, in config_serdes1_refclks()
884 setbits_be32(&srds_regs->bank[i].rstctl, in config_serdes1_refclks()
960 clrbits_be32(&srds2_regs->bank[i].rstctl, in config_serdes2_refclks()
963 clrbits_be32(&srds2_regs->bank[i].rstctl, in config_serdes2_refclks()
966 setbits_be32(&srds2_regs->bank[i].rstctl, in config_serdes2_refclks()
[all …]
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| /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | fsl_corenet_serdes.c | 114 if (in_be32(®s->bank[bank].rstctl) & SRDS_RSTCTL_SDPD) in serdes_lane_enabled()
467 u32 rstctl; in wait_for_rstdone() local
472 rstctl = in_be32(&srds_regs->bank[bank].rstctl); in wait_for_rstdone()
473 if (rstctl & SRDS_RSTCTL_RSTDONE) in wait_for_rstdone()
477 if (!(rstctl & SRDS_RSTCTL_RSTDONE)) in wait_for_rstdone()
603 setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD); in fsl_serdes_init()
644 setbits_be32(&srds_regs->bank[bank].rstctl, in fsl_serdes_init()
647 setbits_be32(&srds_regs->bank[bank].rstctl, in fsl_serdes_init()
863 setbits_be32(&srds_regs->bank[FSL_SRDS_BANK_2].rstctl, in fsl_serdes_init()
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| /openbmc/u-boot/arch/arm/mach-tegra/ |
| H A D | lowlevel_init.S | 28 ldr r1, rstctl @ get addr for global reset
36 rstctl: label
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| /openbmc/linux/drivers/phy/freescale/ |
| H A D | phy-fsl-lynx-28g.c | 28 #define LYNX_28G_PLLnRSTCTL_DIS(rstctl) (((rstctl) & BIT(24)) >> 24) argument
29 #define LYNX_28G_PLLnRSTCTL_LOCK(rstctl) (((rstctl) & BIT(23)) >> 23) argument
113 u32 rstctl, cr0, cr1; member
165 if (LYNX_28G_PLLnRSTCTL_DIS(priv->pll[i].rstctl)) in lynx_28g_supports_interface()
184 if (LYNX_28G_PLLnRSTCTL_DIS(pll->rstctl)) in lynx_28g_pll_get()
482 pll->rstctl = lynx_28g_pll_read(pll, PLLnRSTCTL); in lynx_28g_pll_read_configuration()
486 if (LYNX_28G_PLLnRSTCTL_DIS(pll->rstctl)) in lynx_28g_pll_read_configuration()
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| /openbmc/linux/drivers/gpu/drm/i915/ |
| H A D | vlv_suspend.c | 46 u32 rstctl; member
147 s->rstctl = intel_uncore_read(uncore, GEN6_RSTCTL); in vlv_save_gunit_s0ix_state()
232 intel_uncore_write(uncore, GEN6_RSTCTL, s->rstctl); in vlv_restore_gunit_s0ix_state()
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| /openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/ |
| H A D | immap_ls102xa.h | 343 u32 rstctl; /* Reset Control Register */ member
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| /openbmc/u-boot/arch/powerpc/cpu/mpc8xxx/ |
| H A D | srio.c | 92 if (in_be32((void *)&srds_regs->bank[0].rstctl) in srio_erratum_a004034()
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| /openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | immap_lsch3.h | 487 u32 rstctl; /* Reset Control Register */ member
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| H A D | immap_lsch2.h | 556 u32 rstctl; /* Reset Control Register */ member
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | immap_85xx.h | 2532 u32 rstctl; /* Reset Control Register */ member
2620 u32 rstctl; /* Reset Control Register */ member
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