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/openbmc/qemu/target/arm/tcg/
H A Da32.decode26 &s_rrr_shi s rd rn rm shim shty
27 &s_rrr_shr s rn rd rm rs shty
28 &s_rri_rot s rn rd imm rot
29 &s_rrrr s rd rn rm ra
30 &rrrr rd rn rm ra
31 &rrr_rot rd rn rm rot
32 &rrr rd rn rm
37 &msr_reg rn r mask
39 &msr_bank rn r sysm
41 &ldst_rr p w u rn rt rm shimm shtype
[all …]
H A Dt32.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
25 &s_rri_rot !extern s rn rd imm rot
26 &s_rrrr !extern s rd rn rm ra
27 &rrrr !extern rd rn rm ra
28 &rrr_rot !extern rd rn rm rot
29 &rrr !extern rd rn rm
34 &msr_reg !extern rn r mask
36 &msr_bank !extern rn r sysm
38 &ldst_rr !extern p w u rn rt rm shimm shtype
[all …]
H A Dt16.decode23 &s_rrr_shi !extern s rd rn rm shim shty
24 &s_rrr_shr !extern s rn rd rm rs shty
25 &s_rri_rot !extern s rn rd imm rot
26 &s_rrrr !extern s rd rn rm ra
27 &rrr_rot !extern rd rn rm rot
32 &ldst_rr !extern p w u rn rt rm shimm shtype
33 &ldst_ri !extern p w u rn rt imm
34 &ldst_block !extern rn i b u w list
47 &s_rrr_shi %s rn=%reg_0 shim=0 shty=0
48 @xll_noshr ...... .... rm:3 rn:3 \
[all …]
H A Dsve.decode71 &rr_esz rd rn esz
72 &rri rd rn imm
73 &rr_dbm rd rn dbm
74 &rrri rd rn rm imm
75 &rri_esz rd rn imm esz
76 &rrri_esz rd rn rm imm esz
77 &rrr_esz rd rn rm esz
78 &rrx_esz rd rn rm index esz
79 &rpr_esz rd pg rn esz
80 &rpr_s rd pg rn s
[all …]
H A Dcrypto_helper.c184 static inline void crypto_sha1_3reg(uint64_t *rd, uint64_t *rn, in crypto_sha1_3reg() argument
189 union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; in crypto_sha1_3reg()
302 uint64_t *rn = vn; in HELPER() local
305 union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; in HELPER()
337 uint64_t *rn = vn; in HELPER() local
340 union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; in HELPER()
382 uint64_t *rn = vn; in HELPER() local
385 union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; in HELPER()
436 uint64_t *rn = vn; in HELPER() local
441 d1 += S1_512(rm[1]) + cho512(rm[1], rn[0], rn[1]); in HELPER()
[all …]
H A Dtranslate-sve.c108 int rd, int rn, int data) in gen_gvec_ool_zz() argument
116 vec_full_reg_offset(s, rn), in gen_gvec_ool_zz()
123 int rd, int rn, int data, in gen_gvec_fpst_zz() argument
134 vec_full_reg_offset(s, rn), in gen_gvec_fpst_zz()
143 return gen_gvec_fpst_zz(s, fn, a->rd, a->rn, data, in gen_gvec_fpst_ah_arg_zz()
149 int rd, int rn, int rm, int data) in gen_gvec_ool_zzz() argument
157 vec_full_reg_offset(s, rn), in gen_gvec_ool_zzz()
167 return gen_gvec_ool_zzz(s, fn, a->rd, a->rn, a->rm, data); in gen_gvec_ool_arg_zzz()
172 int rd, int rn, int rm, in gen_gvec_fpst_zzz() argument
183 vec_full_reg_offset(s, rn), in gen_gvec_fpst_zzz()
[all …]
H A Dneon-ls.decode35 VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
40 VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
47 VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \
49 VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 . align:1 rm:4 \
51 VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 . align:2 rm:4 \
H A Dtranslate-m-nocp.c86 fptr = load_reg(s, a->rn); in trans_VLLDM_VLSTM()
640 addr = load_reg(s, a->rn); in fp_sysreg_to_memory()
645 if (s->v8m_stackcheck && a->rn == 13 && a->w) { in fp_sysreg_to_memory()
659 store_reg(s, a->rn, addr); in fp_sysreg_to_memory()
679 addr = load_reg(s, a->rn); in memory_to_fp_sysreg()
684 if (s->v8m_stackcheck && a->rn == 13 && a->w) { in memory_to_fp_sysreg()
699 store_reg(s, a->rn, addr); in memory_to_fp_sysreg()
709 if (a->rn == 15) { in trans_VLDR_sysreg()
720 if (a->rn == 15) { in trans_VSTR_sysreg()
H A Dvfp.decode83 VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8 vd=%vd_sp
84 VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp
85 VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp
95 VLDM_VSTM_sp ---- 1100 1 . w:1 l:1 rn:4 .... 1010 imm:8 \
97 VLDM_VSTM_dp ---- 1100 1 . w:1 l:1 rn:4 .... 1011 imm:8 \
100 VLDM_VSTM_sp ---- 1101 0.1 l:1 rn:4 .... 1010 imm:8 \
102 VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \
H A Dtranslate-mve.c158 if (a->rn == 15 || (a->rn == 13 && a->w)) { in do_ldst()
170 addr = load_reg(s, a->rn); in do_ldst()
186 store_reg(s, a->rn, addr); in do_ldst()
224 !fn || a->rn == 15) { in DO_VLDST_WIDE_NARROW()
233 addr = load_reg(s, a->rn); in DO_VLDST_WIDE_NARROW()
383 TCGv_i32 rn; in do_vldst_il() local
387 !fn || (a->rn == 13 && a->w) || a->rn == 15) { in do_vldst_il()
395 rn = load_reg(s, a->rn); in do_vldst_il()
400 fn(tcg_env, tcg_constant_i32(a->qd), rn); in do_vldst_il()
403 tcg_gen_addi_i32(rn, rn, addrinc); in do_vldst_il()
[all …]
H A Dm-nocp.decode41 &vldr_sysreg rn reg imm a w p
42 @vldr_sysreg .... ... . a:1 . . . rn:4 ... . ... .. ....... \
47 VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 op:1 000 0000
H A Dmve.decode40 &vldr_vstr rn qd imm p a w size l u
46 &vidup qd rn size imm
47 &viwdup qd rn rm size imm
53 &vldst_sg qd qm rn size msize os
55 &vldst_il qd rn size pat w
60 @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0
62 @vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr
64 @vldst_sg .... .... .... rn:4 .... ... size:2 ... ... os:1 &vldst_sg \
72 @vldst_il .... .... .. w:1 . rn:4 .... ... size:2 pat:2 ..... &vldst_il \
408 qd=%qd imm=%imm_vidup rn=%vidup_rn &vidup
[all …]
/openbmc/qemu/tests/tcg/loongarch64/
H A Dtest_pcadd.c10 uint64_t rm, rn; \
18 rn = ((0x12345UL - 0x104) << a) & ~0xfff; \
20 rn = ((0x12345UL - 0x104) << a) + 4; \
22 assert(rm == rn); \
/openbmc/u-boot/drivers/w1/
H A Dw1-uclass.c32 u64 last_rn, rn = w1->search_id, tmp64; in w1_enumerate() local
43 last_rn = rn; in w1_enumerate()
44 rn = 0; in w1_enumerate()
84 rn |= (tmp64 << i); in w1_enumerate()
92 w1->search_id = rn; in w1_enumerate()
97 bus->name, rn, (u8)(rn & 0xff)); in w1_enumerate()
100 w1_eeprom_register_new_device(rn); in w1_enumerate()
/openbmc/qemu/tests/decode/
H A Dsucc_infer1.decode1 &rprr_load rd pg rn rm dtype nreg
2 @rprr_load .... .... ... rm:5 ... pg:3 rn:5 rd:5 &rprr_load
4 LD1Q 1100 0100 000 rm:5 101 pg:3 rn:5 rd:5
/openbmc/qemu/pc-bios/vof/
H A Dentry.S1 #define LOAD32(rn, name) \ argument
2 lis rn,name##@h; \
3 ori rn,rn,name##@l
/openbmc/qemu/util/
H A Drange.c83 Range *r, *rn; in range_inverse_array() local
104 rn = (Range *)l->next->data; in range_inverse_array()
108 if (range_compare(r, rn)) { in range_inverse_array()
110 MIN(range_lob(rn) - 1, high)); in range_inverse_array()
H A Dhost-utils.c44 LL rl, rm, rn, rh, a0, b0; in mul64() local
52 rn.ll = (uint64_t)a0.l.high * b0.l.low; in mul64()
55 c = (uint64_t)rl.l.high + rm.l.low + rn.l.low; in mul64()
58 c = c + rm.l.high + rn.l.high + rh.l.low; in mul64()
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/dvb-apps/files/dvb-scan-table/dvb-t/
H A Dse-Harnosand_Harnon1 # Sweden - Härnösand/Härnön
H A Dse-Seltjarn1 # Sweden - Seltjärn
H A Dse-Bjurberget_Hemtjarn1 # Sweden - Bjurberget/Hemtjärn
/openbmc/u-boot/include/linux/
H A Dmath64.h194 } rl, rm, rn, rh, a0, b0; in mul_u64_u64_shr() local
202 rn.ll = mul_u32_u32(a0.l.high, b0.l.low); in mul_u64_u64_shr()
210 rl.l.high = c = (u64)rl.l.high + rm.l.low + rn.l.low; in mul_u64_u64_shr()
211 rh.l.low = c = (c >> 32) + rm.l.high + rn.l.high + rh.l.low; in mul_u64_u64_shr()
/openbmc/qemu/disas/
H A Dsh4.c1161 print_movxy (const sh_opcode_info *op, int rn, int rm, in print_movxy() argument
1176 fprintf_fn (stream, "@r%d", rn); in print_movxy()
1183 fprintf_fn (stream, "@r%d+", rn); in print_movxy()
1187 fprintf_fn (stream, "@r%d+r8", rn); in print_movxy()
1191 fprintf_fn (stream, "@r%d+r9", rn); in print_movxy()
1624 int rn = 0; in print_insn_sh() local
1762 rn = nibs[n]; in print_insn_sh()
1770 rn = (nibs[n] & 0xc) >> 2; in print_insn_sh()
1773 rn = (nibs[n] & 0xc) >> 2; in print_insn_sh()
1781 rn = nibs[n]; in print_insn_sh()
[all …]
/openbmc/qemu/target/mips/tcg/
H A Dtrace-events4 mips_translate_c0(const char *instr, const char *rn, int reg, int sel) "%s %s (reg %d sel %d)"
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h1140 #define mfdcr(rn) ({unsigned int rval; \ argument
1141 asm volatile("mfdcr %0," stringify(rn) \
1143 #define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) argument
1149 #define mfspr(rn) ({unsigned int rval; \ argument
1150 asm volatile("mfspr %0," stringify(rn) \
1152 #define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) argument

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