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Searched refs:riscv_cpu_mxl (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/target/riscv/
H A Ddebug.c80 switch (riscv_cpu_mxl(env)) { in extract_trigger_type()
136 switch (riscv_cpu_mxl(env)) { in build_tdata1()
184 switch (riscv_cpu_mxl(env)) { in tdata1_validate()
227 switch (riscv_cpu_mxl(env)) { in textra_validate()
263 switch (riscv_cpu_mxl(env)) { in textra_validate()
378 switch (riscv_cpu_mxl(env)) { in trigger_textra_match()
423 if (riscv_cpu_mxl(env) == MXL_RV64) { in type2_breakpoint_size()
462 if (riscv_cpu_mxl(env) == MXL_RV64) { in type2_mcontrol_validate()
H A Dpmu.c296 if (riscv_cpu_mxl(env) == MXL_RV32) { in riscv_pmu_incr_ctr()
428 if (riscv_cpu_mxl(env) == MXL_RV32) { in pmu_hpmevent_is_of_set()
444 if (riscv_cpu_mxl(env) == MXL_RV32) { in pmu_hpmevent_set_of_if_clear()
497 if (riscv_cpu_mxl(env) == MXL_RV32) { in pmu_timer_trigger_irq()
H A Dmonitor.c156 if (riscv_cpu_mxl(env) == MXL_RV32) { in mem_info_svxx()
225 if (riscv_cpu_mxl(env) == MXL_RV32) { in hmp_info_mem()
H A Dcsr.c113 bool rv32 = riscv_cpu_mxl(env) == MXL_RV32 ? true : false; in ctr()
164 if (riscv_cpu_mxl(env) != MXL_RV32) { in ctr32()
214 if ((riscv_cpu_mxl(env) == MXL_RV32) && csrno >= CSR_MCYCLEH) { in mctr()
232 if (riscv_cpu_mxl(env) != MXL_RV32) { in mctr32()
250 if (riscv_cpu_mxl(env) != MXL_RV32) { in sscofpmf_32()
268 if (riscv_cpu_mxl(env) != MXL_RV32) { in smcntrpmf_32()
282 if (riscv_cpu_mxl(env) != MXL_RV32) { in any32()
319 if (riscv_cpu_mxl(env) != MXL_RV32) { in smode32()
355 if (riscv_cpu_mxl(env) != MXL_RV32) { in hmode32()
374 if (riscv_cpu_mxl(env) != MXL_RV32) { in umode32()
[all …]
H A Dcommon-semi-target.h35 return riscv_cpu_mxl(env) != MXL_RV32; in is_64bit_semihosting()
H A Dpmp.c329 pmp_size = 2 << riscv_cpu_mxl(env); in pmp_hart_has_privs()
471 int pmpcfg_nums = 2 << riscv_cpu_mxl(env); in pmpcfg_csr_write()
497 int pmpcfg_nums = 2 << riscv_cpu_mxl(env); in pmpcfg_csr_read()
H A Dcpu.h642 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) macro
644 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
649 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
H A Dcpu_helper.c928 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
936 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
946 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
1057 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
1991 mxlen = 16 << riscv_cpu_mxl(env); in riscv_cpu_do_interrupt()
H A Dcpu.c60 return riscv_cpu_mxl(&cpu->env) == MXL_RV32; in riscv_cpu_is_32bit()
416 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; in set_satp_mode_max_supported()
455 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? in riscv_max_cpu_init()
1020 env->xl = riscv_cpu_mxl(env); in riscv_cpu_reset_hold()
2170 switch (riscv_cpu_mxl(&cpu->env)) { in prop_marchid_set()
2724 switch (riscv_cpu_mxl(env)) { in riscv_gdb_arch_name()
/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c66 switch (riscv_cpu_mxl(env)) { in kvm_riscv_reg_id_ulong()
1467 if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { in kvm_riscv_handle_sbi_dbcn()