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Searched refs:riscv_cpu_mxl (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dmonitor.c156 if (riscv_cpu_mxl(env) == MXL_RV32) { in mem_info_svxx()
226 if (riscv_cpu_mxl(env) == MXL_RV32) { in hmp_info_mem()
H A Dcommon-semi-target.h35 return riscv_cpu_mxl(env) != MXL_RV32; in is_64bit_semihosting()
H A Ddebug.c80 switch (riscv_cpu_mxl(env)) { in extract_trigger_type()
136 switch (riscv_cpu_mxl(env)) { in build_tdata1()
184 switch (riscv_cpu_mxl(env)) { in tdata1_validate()
250 if (riscv_cpu_mxl(env) == MXL_RV64) { in type2_breakpoint_size()
289 if (riscv_cpu_mxl(env) == MXL_RV64) { in type2_mcontrol_validate()
H A Dcsr.c165 if (riscv_cpu_mxl(env) != MXL_RV32) { in ctr32()
211 if (riscv_cpu_mxl(env) != MXL_RV32) { in mctr32()
234 if (riscv_cpu_mxl(env) != MXL_RV32) { in any32()
271 if (riscv_cpu_mxl(env) != MXL_RV32) { in smode32()
307 if (riscv_cpu_mxl(env) != MXL_RV32) { in hmode32()
326 if (riscv_cpu_mxl(env) != MXL_RV32) { in umode32()
455 if (riscv_cpu_mxl(env) != MXL_RV32) { in sstc_32()
828 if (riscv_cpu_mxl(env) == MXL_RV32) { in write_mhpmevent()
983 if (riscv_cpu_mxl(env) == MXL_RV32) { in read_scountovf()
1316 RISCVMXL xl = riscv_cpu_mxl(env); in write_mstatus()
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H A Dpmu.c201 if (riscv_cpu_mxl(env) == MXL_RV32) { in riscv_pmu_incr_ctr()
349 if (riscv_cpu_mxl(env) == MXL_RV32) { in pmu_timer_trigger_irq()
H A Dcpu.h559 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) macro
561 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
566 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
H A Dpmp.c472 int pmpcfg_nums = 2 << riscv_cpu_mxl(env); in pmpcfg_csr_write()
498 int pmpcfg_nums = 2 << riscv_cpu_mxl(env); in pmpcfg_csr_read()
H A Dcpu.c360 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; in set_satp_mode_max_supported()
389 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? in riscv_any_cpu_init()
908 env->xl = riscv_cpu_mxl(env); in riscv_cpu_reset_hold()
949 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; in riscv_cpu_satp_mode_finalize()
1510 switch (riscv_cpu_mxl(env)) { in riscv_gdb_arch_name()
1629 switch (riscv_cpu_mxl(&cpu->env)) { in cpu_set_marchid()
H A Dcpu_helper.c839 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
847 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
857 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
964 if (riscv_cpu_mxl(env) == MXL_RV32) { in get_physical_address()
/openbmc/qemu/target/riscv/kvm/
H A Dkvm-cpu.c62 switch (riscv_cpu_mxl(env)) { in kvm_riscv_reg_id()