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Searched refs:reset_ras_error_count (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dhdp_v4_0.c163 .reset_ras_error_count = hdp_v4_0_reset_ras_error_count,
H A Dsdma_v4_4.c267 .reset_ras_error_count = sdma_v4_4_reset_ras_error_count,
H A Damdgpu_xgmi.c891 adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev); in amdgpu_xgmi_ras_late_init()
1057 adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev); in amdgpu_xgmi_query_ras_error_count()
1093 .reset_ras_error_count = amdgpu_xgmi_reset_ras_error_count,
H A Dgmc_v9_0.c1652 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) in gmc_v9_0_late_init()
1653 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev); in gmc_v9_0_late_init()
1656 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count) in gmc_v9_0_late_init()
1657 adev->hdp.ras->ras_block.hw_ops->reset_ras_error_count(adev); in gmc_v9_0_late_init()
H A Damdgpu_ras.h565 void (*reset_ras_error_count)(struct amdgpu_device *adev); member
H A Dsdma_v4_4_2.c1283 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count) in sdma_v4_4_2_late_init()
1284 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev); in sdma_v4_4_2_late_init()
2179 .reset_ras_error_count = sdma_v4_4_2_reset_ras_error_count,
H A Dsdma_v4_0.c1753 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count) in sdma_v4_0_late_init()
1754 adev->sdma.ras->ras_block.hw_ops->reset_ras_error_count(adev); in sdma_v4_0_late_init()
2616 .reset_ras_error_count = sdma_v4_0_reset_ras_error_count,
H A Dmmhub_v1_0.c782 .reset_ras_error_count = mmhub_v1_0_reset_ras_error_count,
H A Dmmhub_v1_8.c835 .reset_ras_error_count = mmhub_v1_8_reset_ras_error_count,
H A Damdgpu_device.c3374 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) in amdgpu_device_xgmi_reset_func()
3375 adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(adev); in amdgpu_device_xgmi_reset_func()
4958 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count) in amdgpu_do_asic_reset()
4959 tmp_adev->mmhub.ras->ras_block.hw_ops->reset_ras_error_count(tmp_adev); in amdgpu_do_asic_reset()
H A Damdgpu_ras.c1116 if (block_obj->hw_ops->reset_ras_error_count) in amdgpu_ras_reset_error_status()
1117 block_obj->hw_ops->reset_ras_error_count(adev); in amdgpu_ras_reset_error_status()
H A Dgfx_v9_4.c1011 .reset_ras_error_count = &gfx_v9_4_reset_ras_error_count,
H A Djpeg_v4_0_3.c1212 .reset_ras_error_count = jpeg_v4_0_3_reset_ras_error_count,
H A Dmmhub_v1_7.c1326 .reset_ras_error_count = mmhub_v1_7_reset_ras_error_count,
H A Dmmhub_v9_4.c1668 .reset_ras_error_count = mmhub_v9_4_reset_ras_error_count,
H A Dvcn_v4_0_3.c1749 .reset_ras_error_count = vcn_v4_0_3_reset_ras_error_count,
H A Dgfx_v9_4_2.c1929 .reset_ras_error_count = &gfx_v9_4_2_reset_ras_error_count,
H A Dgfx_v9_4_3.c4422 .reset_ras_error_count = &gfx_v9_4_3_reset_ras_error_count,
H A Dgfx_v9_0.c1829 .reset_ras_error_count = &gfx_v9_0_reset_ras_error_count,