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/openbmc/u-boot/doc/device-tree-bindings/reset/
H A Dreset.txt3 This binding is intended to represent the hardware reset signals present
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
17 are dictated by the binding of the reset provider, although common schemes
20 A word on where to place reset signal consumers in device tree: It is possible
[all …]
H A Dti,sci-reset.txt13 The reset controller node represents the resets of various hardware modules
19 - compatible: Must be "ti,sci-reset"
20 - #reset-cells: Must be 2. Please see the reset consumer node below for
28 k3_reset: reset-controller {
29 compatible = "ti,sci-reset";
30 #reset-cells = <2>;
36 Each of the reset consumer nodes should have the following properties,
41 - resets: A phandle and reset specifier pair, one pair for each reset signal
43 should point to the TI SCI reset controller node, and the reset
45 the device ID. The second cell should contain the reset mask value
/openbmc/u-boot/drivers/reset/
H A DMakefile6 obj-$(CONFIG_DM_RESET) += reset-uclass.o
7 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o
8 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
9 obj-$(CONFIG_STI_RESET) += sti-reset.o
10 obj-$(CONFIG_STM32_RESET) += stm32-reset.o
11 obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
12 obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
13 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
14 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
15 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
[all …]
H A DKconfig4 bool "Enable reset controllers using Driver Model"
7 Enable support for the reset controller driver class. Many hardware
8 modules are equipped with a reset signal, typically driven by some
9 reset controller hardware module within the chip. In U-Boot, reset
10 controller drivers allow control over these reset signals. In some
12 although driving such reset isgnals using GPIOs may be more
16 bool "Enable the sandbox reset test driver"
19 Enable support for a test reset controller implementation, which
20 simply accepts requests to reset various HW modules without actually
24 bool "Enable the STi reset"
[all …]
H A Dreset-sunxi.c50 const struct ccu_reset *reset = priv_to_reset(priv, reset_ctl->id); in sunxi_set_reset() local
53 if (!(reset->flags & CCU_RST_F_IS_VALID)) { in sunxi_set_reset()
59 reset_ctl->id, reset->off, ilog2(reset->bit)); in sunxi_set_reset()
61 reg = readl(priv->base + reset->off); in sunxi_set_reset()
63 reg |= reset->bit; in sunxi_set_reset()
65 reg &= ~reset->bit; in sunxi_set_reset()
67 writel(reg, priv->base + reset->off); in sunxi_set_reset()
/openbmc/qemu/hw/misc/
H A Dxlnx-versal-crl.c154 .reset = 0x1,
162 .reset = 0x1,
165 .reset = 0x24809,
168 .reset = 0x2000000,
173 .reset = R_PLL_STATUS_RPLL_STABLE_MASK |
178 .reset = 0x2000100,
181 .reset = 0x6000300,
184 .reset = 0x2000800,
187 .reset = 0xe000300,
190 .reset = 0x2000500,
[all …]
H A Dxlnx-zynqmp-crf.c84 .reset = 0x1,
92 .reset = 0x12c09,
99 .reset = 0x2c09,
106 .reset = 0x12809,
113 .reset = 0x3f,
117 .reset = 0x400,
120 .reset = 0x400,
123 .reset = 0x400,
126 .reset = 0x3000400,
129 .reset = 0x2500,
[all …]
/openbmc/qemu/tests/qtest/
H A Dstm32l4x5_gpio-test.c159 static uint32_t reset(uint32_t gpio, unsigned int offset) in reset() function
218 g_assert_cmphex(moder, ==, reset(GPIO_A, MODER)); in test_idr_reset_value()
219 g_assert_cmphex(odr, ==, reset(GPIO_A, ODR)); in test_idr_reset_value()
220 g_assert_cmphex(otyper, ==, reset(GPIO_A, OTYPER)); in test_idr_reset_value()
222 g_assert_cmphex(pupdr, ==, reset(GPIO_A, PUPDR)); in test_idr_reset_value()
224 g_assert_cmphex(idr, ==, reset(GPIO_A, IDR)); in test_idr_reset_value()
233 g_assert_cmphex(moder, ==, reset(GPIO_B, MODER)); in test_idr_reset_value()
234 g_assert_cmphex(odr, ==, reset(GPIO_B, ODR)); in test_idr_reset_value()
235 g_assert_cmphex(otyper, ==, reset(GPIO_B, OTYPER)); in test_idr_reset_value()
237 g_assert_cmphex(pupdr, ==, reset(GPIO_B, PUPDR)); in test_idr_reset_value()
[all …]
/openbmc/u-boot/drivers/sysreset/
H A DKconfig2 # System reset devices
5 menu "System reset device drivers"
8 bool "Enable support for system reset drivers"
11 Enable system reset drivers which can be used to reset the CPU or
12 board. Each driver can provide a reset method which will be called
13 to effect a reset. The uclass will try all available drivers when
19 bool "Enable support for GPIO reset driver"
22 Reset support via GPIO pin connected reset logic. This is used for
23 example on Microblaze where reset logic can be controlled via GPIO
24 pin which triggers cpu reset.
[all …]
/openbmc/u-boot/drivers/reset/aspeed/
H A DKconfig6 Support for reset controller on ASPEED SoC. This controller uses
7 watchdog to reset different peripherals and thus only supports
9 is that some reset signals, like I2C or MISC reset multiple devices.
16 Support for reset controller on ASPEED SoC. This controller uses
17 watchdog to reset different peripherals and thus only supports
19 is that some reset signals, like I2C or MISC reset multiple devices.
26 Support for reset controller on ASPEED SoC. This controller uses
27 watchdog to reset different peripherals and thus only supports
29 is that some reset signals, like I2C or MISC reset multiple devices.
/openbmc/u-boot/doc/device-tree-bindings/exynos/
H A Demmc-reset.txt1 * Samsung eMMC reset
7 - compatible: should be "samsung,emmc-reset"
8 - reset-gpio: gpio chip for eMMC reset.
12 emmc-reset {
13 compatible = "samsung,emmc-reset";
14 reset-gpio = <&gpk1 2 0>;
/openbmc/qemu/docs/devel/
H A Dreset.rst6 The reset of qemu objects is handled using the resettable interface declared
10 whole group can be reset consistently. Each individual member object does not
12 reset first) are addressed.
17 Triggering reset
24 You can apply a reset to an object using ``resettable_assert_reset()``. You need
25 to call ``resettable_release_reset()`` to release the object from reset. To
26 instantly reset an object, without keeping it in reset state, just call
28 object to reset and a reset type.
30 The Resettable interface handles reset types with an enum ``ResetType``:
33 Cold reset is supported by every resettable object. In QEMU, it means we reset
[all …]
/openbmc/openbmc-test-automation/gui/gui_test/settings_menu/
H A Dtest_factory_reset_sub_menu.robot3 Documentation Test suite for OpenBMC GUI "Factory reset" sub-menu of "Settings" menu.
14 ${xpath_factory_reset_heading} //h1[text()="Factory reset"]
25 [Documentation] Verify navigation to factory reset page.
32 [Documentation] Verify existence of all sections in factory reset page.
39 [Documentation] Verify existence of all buttons in factory reset page.
48 [Documentation] Verify existence of all radio buttons in factory reset page.
52 # Navigate to factory reset page.
53 …vigate To Required Sub Menu ${xpath_settings_menu} ${xpath_factory_reset_sub_menu} factory-reset
60 [Documentation] Verify reset server settings only option
67 # Navigate to factory reset page.
[all …]
/openbmc/u-boot/doc/device-tree-bindings/gpu/
H A Dnvidia,tegra20-host1x.txt14 - resets: Must contain an entry for each entry in reset-names.
15 See ../reset/reset.txt for details.
16 - reset-names: Must include the following entries:
30 - resets: Must contain an entry for each entry in reset-names.
31 See ../reset/reset.txt for details.
32 - reset-names: Must include the following entries:
43 - resets: Must contain an entry for each entry in reset-names.
44 See ../reset/reset.txt for details.
45 - reset-names: Must include the following entries:
56 - resets: Must contain an entry for each entry in reset-names.
[all …]
/openbmc/openpower-hw-diags/attn/
H A Dattn_config.cpp10 iv_flags.reset(dfltTi); // default value is clear in Config()
38 iv_flags.reset(i_flag); in clearFlag()
44 iv_flags.reset(enVital); in clearFlagAll()
45 iv_flags.reset(enCheckstop); in clearFlagAll()
46 iv_flags.reset(enTerminate); in clearFlagAll()
47 iv_flags.reset(enBreakpoints); in clearFlagAll()
48 iv_flags.reset(enClrAttnIntr); in clearFlagAll()
/openbmc/u-boot/arch/arm/dts/
H A Dast2400-u-boot.dtsi2 #include <dt-bindings/reset/ast2400-reset.h>
12 #reset-cells = <1>;
15 rst: reset-controller {
17 compatible = "aspeed,ast2400-reset";
19 #reset-cells = <1>;
27 #reset-cells = <1>;
H A Dast2600-u-boot.dtsi2 #include <dt-bindings/reset/ast2600-reset.h>
12 #reset-cells = <1>;
16 rst: reset-controller {
18 compatible = "aspeed,ast2600-reset";
20 #reset-cells = <1>;
29 #reset-cells = <1>;
H A Dast2500-u-boot.dtsi2 #include <dt-bindings/reset/ast2500-reset.h>
12 #reset-cells = <1>;
15 rst: reset-controller {
17 compatible = "aspeed,ast2500-reset";
19 #reset-cells = <1>;
27 #reset-cells = <1>;
/openbmc/phosphor-logging/extensions/openpower-pels/
H A Dpel_rules.cpp28 newActionFlags.reset(reportFlagBit); in check()
32 newActionFlags.reset(spCallHomeFlagBit); in check()
39 newActionFlags.reset(serviceActionFlagBit); in check()
40 newActionFlags.reset(callHomeFlagBit); in check()
64 newActionFlags.reset(serviceActionFlagBit); in check()
65 newActionFlags.reset(callHomeFlagBit); in check()
75 newActionFlags.reset(hiddenFlagBit); in check()
/openbmc/phosphor-state-manager/service_files/
H A Dphosphor-reset-chassis-on@.service2 Description=Start chassis%i on after BMC reset
3 Requires=phosphor-reset-chassis-running@%i.service
4 After=phosphor-reset-chassis-running@%i.service
5 After=obmc-power-reset-on@%i.target
6 Requires=obmc-power-reset-on@%i.target
12 SyslogIdentifier=phosphor-reset-chassis-on
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dreset_manager_s10.c21 void socfpga_per_reset(u32 reset, int set) in socfpga_per_reset() argument
25 if (RSTMGR_BANK(reset) == 0) in socfpga_per_reset()
27 else if (RSTMGR_BANK(reset) == 1) in socfpga_per_reset()
29 else if (RSTMGR_BANK(reset) == 2) in socfpga_per_reset()
31 else if (RSTMGR_BANK(reset) == 3) in socfpga_per_reset()
37 setbits_le32(reg, 1 << RSTMGR_RESET(reset)); in socfpga_per_reset()
39 clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); in socfpga_per_reset()
/openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/gpio/phosphor-gpio-monitor/
H A Dmulti-gpios-sys-init116 set_gpio reset-control-bmc 1
118 set_gpio reset-control-cpu0-p0-mux 1
120 set_gpio reset-control-cpu0-p1-mux 1
122 set_gpio reset-control-e1s-mux 1
125 set_gpio reset-control-mb-mux 1
127 set_gpio reset-control-smb-e1s-0 1
129 set_gpio reset-control-smb-e1s-1 1
131 set_gpio reset-control-srst 1
133 set_gpio reset-control-usb-hub 1
136 set_gpio reset-control 1
[all …]
/openbmc/u-boot/doc/device-tree-bindings/phy/
H A Dphy-stih407-usb.txt9 - resets : list of phandle and reset specifier pairs. There should be two entries, one
11 - reset-names : list of reset signal names. Should be "global" and "port"
12 See: Documentation/devicetree/bindings/reset/st,sti-powerdown.txt
13 See: Documentation/devicetree/bindings/reset/reset.txt
23 reset-names = "global", "port";
/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Demac.c20 u32 reset; in cpu_eth_init() local
23 reset = readl(&am35x_scm_general_regs->ip_sw_reset); in cpu_eth_init()
24 reset &= ~CPGMACSS_SW_RST; in cpu_eth_init()
25 writel(reset, &am35x_scm_general_regs->ip_sw_reset); in cpu_eth_init()
/openbmc/openbmc/meta-google/recipes-google/host-power-ctrl/
H A Dgpio-host-pwr_git.bb21 file://host-reset-cold-watchdog.service \
22 file://host-reset-cold.service \
23 file://host-reset-warm-watchdog.service \
24 file://host-reset-warm.service \
36 host-reset-cold.service \
37 host-reset-cold-watchdog.service \
38 host-reset-warm.service \
39 host-reset-warm-watchdog.service \

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