/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/ |
H A D | gaudi2_async_ids_map_extended.h | 27 int reset; member 32 { .fc_id = 0, .cpu_id = 0, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, 34 { .fc_id = 1, .cpu_id = 1, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, 36 { .fc_id = 2, .cpu_id = 2, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, 38 { .fc_id = 3, .cpu_id = 3, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, 40 { .fc_id = 4, .cpu_id = 4, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, 42 { .fc_id = 5, .cpu_id = 5, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, 44 { .fc_id = 6, .cpu_id = 6, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, 46 { .fc_id = 7, .cpu_id = 7, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, 48 { .fc_id = 8, .cpu_id = 8, .valid = 0, .msg = 0, .reset = EVENT_RESET_TYPE_NONE, [all …]
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/openbmc/linux/Documentation/devicetree/bindings/reset/ |
H A D | zynq-reset.txt | 25 0 : soft reset 26 32 : ddr reset 28 96 : dmac reset 29 128: usb0 reset 30 129: usb1 reset 31 160: gem0 reset 32 161: gem1 reset 41 224: spi0 reset 42 225: spi1 reset 58 416: smc reset [all …]
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H A D | socionext,uniphier-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-reset.yaml# 7 title: UniPhier reset controller 15 - description: System reset 17 - socionext,uniphier-ld4-reset 18 - socionext,uniphier-pro4-reset 27 - description: Media I/O (MIO) reset, SD reset 39 - description: Peripheral reset 55 "#reset-cells": 65 - "#reset-cells" 69 reset-controller { [all …]
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H A D | socionext,uniphier-glue-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/socionext,uniphier-glue-reset.yaml# 26 - socionext,uniphier-nx1-usb3-reset 34 "#reset-cells": 47 reset-names: true 70 reset-names: 82 reset-names: 90 - "#reset-cells" 94 - reset-names 98 usb_rst: reset-controller@0 { 101 #reset-cells = <1>; [all …]
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H A D | reset.txt | 10 reset consumer (the module being reset, or a module managing when a sub- 14 A reset signal is represented by the phandle of the provider, plus a reset 24 may be reset. Instead, reset signals should be represented in the DT node 35 #reset-cells: Number of cells in a reset specifier; Typically 0 for nodes 37 reset outputs. 41 rst: reset-controller { 42 #reset-cells = <1>; 55 reset-names: List of reset signal name strings sorted in the same order as 57 match reset signal names with reset specifiers. 63 reset-names = "reset"; [all …]
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H A D | xlnx,zynqmp-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml# 15 The PS reset subsystem is responsible for handling the external reset 19 Please also refer to reset.txt in this directory for common reset 22 node as specified in reset.txt. 33 - xlnx,zynqmp-reset 34 - xlnx,versal-reset 35 - xlnx,versal-net-reset 37 "#reset-cells": 42 - "#reset-cells" 48 zynqmp_reset: reset-controller { [all …]
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H A D | snps,hsdk-reset.txt | 1 Binding for the Synopsys HSDK reset controller 3 This binding uses the common reset binding[1]. 5 [1] Documentation/devicetree/bindings/reset/reset.txt 8 - compatible: should be "snps,hsdk-reset". 12 - #reset-cells: from common reset binding; Should always be set to 1. 15 reset: reset@880 { 16 compatible = "snps,hsdk-reset"; 17 #reset-cells = <1>; 21 Specifying reset lines connected to IP modules: 24 resets = <&reset HSDK_V1_ETH_RESET>; [all …]
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H A D | ti-syscon-reset.txt | 27 "ti,syscon-reset" 28 - #reset-cells : Should be 1. Please see the reset consumer node below 30 - ti,reset-bits : Contains the reset control register information 35 Cell #2 : bit position of the reset in the reset 39 Cell #4 : bit position of the reset in the reset 44 reset status register 57 to a reset specifier as defined above. 59 Please also refer to Documentation/devicetree/bindings/reset/reset.txt for 74 pscrst: reset-controller { 76 #reset-cells = <1>; [all …]
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H A D | brcm,brcmstb-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/brcm,brcmstb-reset.yaml# 12 reset lines. 14 Please also refer to reset.txt in this directory for common reset 22 const: brcm,brcmstb-reset 27 "#reset-cells": 33 - "#reset-cells" 39 reset: reset-controller@8404318 { 40 compatible = "brcm,brcmstb-reset"; 42 #reset-cells = <1>; 46 resets = <&reset 26>; [all …]
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H A D | img,pistachio-reset.txt | 13 Please refer to Documentation/devicetree/bindings/reset/reset.txt 14 for common reset controller binding usage. 18 - compatible: Contains "img,pistachio-reset" 20 - #reset-cells: Contains 1 31 pistachio_reset: reset-controller { 32 compatible = "img,pistachio-reset"; 33 #reset-cells = <1>; 37 Specifying reset control of devices 43 Documentation/devicetree/bindings/reset/reset.txt. 50 reset-names = "rst"; [all …]
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H A D | fsl,imx7-src.yaml | 4 $id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml# 13 The system reset controller can be used to reset various set of 16 specified in reset.txt. 18 For list of all valid reset indices see 19 <dt-bindings/reset/imx7-reset.h> for i.MX7, 20 <dt-bindings/reset/imx8mq-reset.h> for i.MX8MQ, i.MX8MM and i.MX8MN, 21 <dt-bindings/reset/imx8mp-reset.h> for i.MX8MP. 45 '#reset-cells': 52 - '#reset-cells' 60 reset-controller@30390000 { [all …]
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H A D | allwinner,sun6i-a31-clock-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/allwinner,sun6i-a31-clock-reset.yaml# 20 - allwinner,sun6i-a31-ahb1-reset 21 - allwinner,sun6i-a31-clock-reset 31 "#reset-cells": 40 - allwinner,sun6i-a31-ahb1-reset 41 - allwinner,sun6i-a31-clock-reset 47 - "#reset-cells" 55 ahb1_rst: reset@1c202c0 { 56 #reset-cells = <1>; 62 apbs_rst: reset@80014b0 { [all …]
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H A D | snps,axs10x-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/snps,axs10x-reset.yaml# 7 title: AXS10x reset controller 16 represents up-to 32 reset lines. 22 const: snps,axs10x-reset 27 '#reset-cells': 33 - '#reset-cells' 39 reset: reset-controller@11220 { 40 compatible = "snps,axs10x-reset"; 41 #reset-cells = <1>; 45 // Specifying reset lines connected to IP modules: [all …]
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H A D | nuvoton,npcm750-reset.yaml | 4 $id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml# 15 - nuvoton,npcm750-reset # Poleg NPCM7XX SoC 16 - nuvoton,npcm845-reset # Arbel NPCM8XX SoC 21 '#reset-cells': 28 nuvoton,sw-reset-number: 34 If not specified, software reset is disabled. 39 - '#reset-cells' 46 #include <dt-bindings/reset/nuvoton,npcm7xx-reset.h> 48 compatible = "nuvoton,npcm750-reset"; 50 #reset-cells = <2>; [all …]
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/openbmc/linux/drivers/reset/ |
H A D | Makefile | 7 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o 8 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o 9 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o 11 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o 14 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o 15 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o 17 obj-$(CONFIG_RESET_K210) += reset-k210.o 21 obj-$(CONFIG_RESET_MESON) += reset-meson.o 23 obj-$(CONFIG_RESET_NPCM) += reset-npcm.o 31 obj-$(CONFIG_RESET_SCMI) += reset-scmi.o [all …]
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H A D | reset-sunplus.c | 162 sp_reset_assert(&reset->rcdev, 0); in sp_restart() 163 sp_reset_deassert(&reset->rcdev, 0); in sp_restart() 171 struct sp_reset *reset; in sp_reset_probe() local 175 reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL); in sp_reset_probe() 176 if (!reset) in sp_reset_probe() 181 if (IS_ERR(reset->base)) in sp_reset_probe() 182 return PTR_ERR(reset->base); in sp_reset_probe() 184 reset->rcdev.ops = &sp_reset_ops; in sp_reset_probe() 185 reset->rcdev.owner = THIS_MODULE; in sp_reset_probe() 186 reset->rcdev.of_node = dev->of_node; in sp_reset_probe() [all …]
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H A D | Kconfig | 30 AR71xx SoC reset controller. 53 tristate "Broadcom STB reset controller" 92 Say Y to control the reset signals provided by reset controller. 118 bool "Microchip Sparx5 reset driver" 219 This enables a simple reset controller driver for reset lines that 228 - RCC reset controller in STM32 MCUs 293 called reset-tn48m. 321 source "drivers/reset/starfive/Kconfig" 322 source "drivers/reset/sti/Kconfig" 323 source "drivers/reset/hisilicon/Kconfig" [all …]
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/openbmc/linux/drivers/power/reset/ |
H A D | at91-reset.c | 141 : "r" (reset->ramc_base[0]), in at91_reset() 142 "r" (reset->ramc_base[1]), in at91_reset() 143 "r" (reset->rstc_base), in at91_reset() 147 "r" (reset->ramc_lpr) in at91_reset() 333 reset->rcdev.nr_resets = reset->data->n_device_reset; in at91_rcdev_init() 343 struct at91_reset *reset; in at91_reset_probe() local 347 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL); in at91_reset_probe() 348 if (!reset) in at91_reset_probe() 372 if (!reset->data) in at91_reset_probe() 376 reset->nb.priority = 192; in at91_reset_probe() [all …]
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/openbmc/linux/drivers/clk/visconti/ |
H A D | reset.c | 31 spin_lock_irqsave(reset->lock, flags); in visconti_reset_assert() 82 .reset = visconti_reset_reset, 93 struct visconti_reset *reset; in visconti_register_reset_controller() local 95 reset = devm_kzalloc(dev, sizeof(*reset), GFP_KERNEL); in visconti_register_reset_controller() 96 if (!reset) in visconti_register_reset_controller() 99 reset->regmap = regmap; in visconti_register_reset_controller() 100 reset->resets = resets; in visconti_register_reset_controller() 101 reset->rcdev.ops = reset_ops; in visconti_register_reset_controller() 102 reset->rcdev.nr_resets = num_resets; in visconti_register_reset_controller() 103 reset->rcdev.of_node = dev->of_node; in visconti_register_reset_controller() [all …]
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/openbmc/linux/Documentation/driver-api/ |
H A D | reset.rst | 15 over their reset input signals, and the `reset controller driver interface 17 <#reset-controller-driver-api>`__), which is used by drivers for reset 31 Physical reset line carrying a reset signal from a reset controller 40 reset line. 52 reset line. 61 trigger reset pulses, or to query reset line status. 64 reset inputs, which are mapped to an actual reset control on an existing reset 127 Only some reset controllers support querying the current status of a reset 130 reset line is asserted. 159 assert or deassert reset signals, to trigger a reset pulse on a reset line, or [all …]
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/openbmc/u-boot/doc/device-tree-bindings/reset/ |
H A D | reset.txt | 10 reset consumer (the module being reset, or a module managing when a sub- 14 A reset signal is represented by the phandle of the provider, plus a reset 24 may be reset. Instead, reset signals should be represented in the DT node 35 #reset-cells: Number of cells in a reset specifier; Typically 0 for nodes 37 reset outputs. 41 rst: reset-controller { 42 #reset-cells = <1>; 55 reset-names: List of reset signal name strings sorted in the same order as 57 match reset signal names with reset specifiers. 63 reset-names = "reset"; [all …]
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/openbmc/u-boot/drivers/reset/ |
H A D | Makefile | 6 obj-$(CONFIG_DM_RESET) += reset-uclass.o 7 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o 8 obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o 9 obj-$(CONFIG_STI_RESET) += sti-reset.o 10 obj-$(CONFIG_STM32_RESET) += stm32-reset.o 12 obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o 13 obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o 14 obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o 17 obj-$(CONFIG_RESET_MESON) += reset-meson.o 18 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o [all …]
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H A D | Kconfig | 4 bool "Enable reset controllers using Driver Model" 9 reset controller hardware module within the chip. In U-Boot, reset 16 bool "Enable the sandbox reset test driver" 24 bool "Enable the STi reset" 32 bool "Enable the STM32 reset" 39 bool "Enable Tegra CAR-based reset driver" 46 bool "Enable Tegra186 BPMP-based reset driver" 64 Support reset controller on BCM6345. 75 source "drivers/reset/aspeed/Kconfig" 83 though is that some reset signals, like I2C or MISC reset multiple [all …]
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/openbmc/qemu/hw/misc/ |
H A D | xlnx-versal-crl.c | 153 .reset = 0x1, 161 .reset = 0x1, 251 .reset = 0x1, 254 .reset = 0x1, 257 .reset = 0x1, 260 .reset = 0x1, 262 .reset = 0x1, 265 .reset = 0x1, 268 .reset = 0x1, 271 .reset = 0x1, [all …]
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/openbmc/linux/Documentation/devicetree/bindings/power/reset/ |
H A D | keystone-reset.txt | 3 This node is intended to allow SoC reset in case of software reset 14 - compatible: ti,keystone-reset 18 reset control registers. 26 - ti,soft-reset: Boolean option indicating soft reset. 27 By default hard reset is used. 37 Setup keystone reset so that in case software reset or 50 rstctrl: reset-controller { 51 compatible = "ti,keystone-reset"; 58 Setup keystone reset so that in case of software reset or 61 rstctrl: reset-controller { [all …]
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