| /openbmc/u-boot/drivers/ata/ |
| H A D | sata_mv.c | 254 u32 regbase; member
287 out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA); in mv_stop_edma_engine()
291 u32 reg = in_le32(priv->regbase + EDMA_CMD); in mv_stop_edma_engine()
308 tmp = in_le32(priv->regbase + SIR_SSTATUS); in mv_start_edma_engine()
314 tmp = in_le32(priv->regbase + PIO_CMD_STATUS); in mv_start_edma_engine()
321 out_le32(priv->regbase + EDMA_IECR, 0x0); in mv_start_edma_engine()
328 tmp = in_le32(priv->regbase + EDMA_CFG); in mv_start_edma_engine()
331 out_le32(priv->regbase + EDMA_CFG, tmp); in mv_start_edma_engine()
333 out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0); in mv_start_edma_engine()
336 out_le32(priv->regbase + SIR_FIS_CFG, 0x0); in mv_start_edma_engine()
[all …]
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| /openbmc/u-boot/drivers/spi/ |
| H A D | cadence_qspi_apb.c | 381 cadence_qspi_apb_controller_disable(plat->regbase); in cadence_qspi_apb_controller_init()
384 reg = readl(plat->regbase + CQSPI_REG_SIZE); in cadence_qspi_apb_controller_init()
390 writel(reg, plat->regbase + CQSPI_REG_SIZE); in cadence_qspi_apb_controller_init()
393 writel(0, plat->regbase + CQSPI_REG_REMAP); in cadence_qspi_apb_controller_init()
396 writel(plat->fifo_depth / 2, plat->regbase + CQSPI_REG_SRAMPARTITION); in cadence_qspi_apb_controller_init()
399 writel(0, plat->regbase + CQSPI_REG_IRQMASK); in cadence_qspi_apb_controller_init()
401 cadence_qspi_apb_controller_enable(plat->regbase); in cadence_qspi_apb_controller_init()
557 plat->regbase + CQSPI_REG_INDIRECTTRIGGER); in cadence_qspi_apb_indirect_read_setup()
568 writel(addr_value, plat->regbase + CQSPI_REG_INDIRECTRDSTARTADDR); in cadence_qspi_apb_indirect_read_setup()
578 writel(0x0, plat->regbase + CQSPI_REG_MODE_BIT); in cadence_qspi_apb_indirect_read_setup()
[all …]
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| H A D | cadence_qspi.c | 27 cadence_qspi_apb_config_baudrate_div(priv->regbase, in cadence_spi_write_speed()
31 cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz, in cadence_spi_write_speed()
42 void *base = priv->regbase; in spi_calibration()
128 cadence_qspi_apb_controller_disable(priv->regbase); in cadence_spi_set_speed()
146 cadence_qspi_apb_controller_enable(priv->regbase); in cadence_spi_set_speed()
158 priv->regbase = plat->regbase; in cadence_spi_probe()
174 cadence_qspi_apb_controller_disable(priv->regbase); in cadence_spi_set_mode()
177 cadence_qspi_apb_set_clk_mode(priv->regbase, mode); in cadence_spi_set_mode()
180 cadence_qspi_apb_controller_enable(priv->regbase); in cadence_spi_set_mode()
192 void *base = priv->regbase; in cadence_spi_xfer()
[all …]
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| H A D | cadence_qspi.h | 18 void *regbase; member
35 void *regbase; member
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| /openbmc/u-boot/drivers/mmc/ |
| H A D | bcmstb_sdhci.c | 45 int bcmstb_sdhci_init(phys_addr_t regbase) in bcmstb_sdhci_init() argument
57 host->ioaddr = (void *)regbase; in bcmstb_sdhci_init()
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| H A D | tmio-common.c | 26 return readq(priv->regbase + (reg << 1)); in tmio_sd_readq()
32 writeq(val, priv->regbase + (reg << 1)); in tmio_sd_writeq()
37 return readw(priv->regbase + (reg >> 1)); in tmio_sd_readw()
43 writew(val, priv->regbase + (reg >> 1)); in tmio_sd_writew()
51 return readl(priv->regbase + (reg << 1)); in tmio_sd_readl()
53 val = readw(priv->regbase + (reg >> 1)) & 0xffff; in tmio_sd_readl()
56 val |= readw(priv->regbase + (reg >> 1) + 2) << 16; in tmio_sd_readl()
60 return readl(priv->regbase + reg); in tmio_sd_readl()
67 writel(val, priv->regbase + (reg << 1)); in tmio_sd_writel()
69 writew(val & 0xffff, priv->regbase + (reg >> 1)); in tmio_sd_writel()
[all …]
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| H A D | mv_sdhci.c | 67 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) in mv_sdh_init() argument
77 host->ioaddr = (void *)regbase; in mv_sdh_init()
88 sdhci_mvebu_mbus_config((void __iomem *)regbase); in mv_sdh_init()
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| H A D | atmel_sdhci.c | 18 int atmel_sdhci_init(void *regbase, u32 id) in atmel_sdhci_init() argument
30 host->ioaddr = regbase; in atmel_sdhci_init()
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| H A D | s5p_sdhci.c | 107 int s5p_sdhci_init(u32 regbase, int index, int bus_width) in s5p_sdhci_init() argument
114 host->ioaddr = (void *)regbase; in s5p_sdhci_init()
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| H A D | meson_gx_mmc.c | 19 return pdata->regbase; in get_regbase()
230 pdata->regbase = (void *)addr; in meson_mmc_ofdata_to_platdata()
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| H A D | tmio-common.h | 119 void __iomem *regbase; member
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | vf610_nfc.c | 242 static inline void vf610_nfc_clear_status(void __iomem *regbase) in vf610_nfc_clear_status() argument
244 void __iomem *reg = regbase + NFC_IRQ_STATUS; in vf610_nfc_clear_status()
297 static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1, in vf610_nfc_send_command() argument
300 void __iomem *reg = regbase + NFC_FLASH_CMD2; in vf610_nfc_send_command()
302 vf610_nfc_clear_status(regbase); in vf610_nfc_send_command()
312 static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1, in vf610_nfc_send_commands() argument
315 void __iomem *reg = regbase + NFC_FLASH_CMD1; in vf610_nfc_send_commands()
317 vf610_nfc_send_command(regbase, cmd_byte1, cmd_code); in vf610_nfc_send_commands()
346 static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size) in vf610_nfc_transfer_size() argument
348 __raw_writel(size, regbase + NFC_SECTOR_SIZE); in vf610_nfc_transfer_size()
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| /openbmc/u-boot/arch/arm/include/asm/arch-hi6220/ |
| H A D | dwmmc.h | 7 int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
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| /openbmc/u-boot/arch/arm/mach-bcmstb/include/mach/ |
| H A D | sdhci.h | 13 int bcmstb_sdhci_init(phys_addr_t regbase);
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| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | atmel_sdhci.h | 10 int atmel_sdhci_init(void *regbase, u32 id);
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| /openbmc/u-boot/arch/arm/mach-bcm283x/include/mach/ |
| H A D | sdhci.h | 15 int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq);
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| /openbmc/qemu/target/sparc/ |
| H A D | win_helper.c | 30 memcpy(env->regbase, env->regbase + env->nwindows * 16, in cpu_set_cwp()
37 memcpy(env->regbase + env->nwindows * 16, env->regbase, in cpu_set_cwp()
40 env->regwptr = env->regbase + (new_cwp * 16); in cpu_set_cwp()
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| H A D | mmu_helper.c | 407 target_ulong fp = env->regbase[cwp * 16 + 22]; in sparc_cpu_memory_rw_debug()
458 u.v = cpu_to_be32(env->regbase[reg]); in sparc_cpu_memory_rw_debug()
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| H A D | machine.c | 196 VMSTATE_VARRAY_MULTIPLY(env.regbase, SPARCCPU, env.nwindows, 16,
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| /openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
| H A D | mmc.h | 55 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
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| /openbmc/u-boot/arch/arm/mach-exynos/include/mach/ |
| H A D | mmc.h | 57 int s5p_sdhci_init(u32 regbase, int index, int bus_width);
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| /openbmc/qemu/linux-user/sparc/ |
| H A D | target_cpu.h | 47 env->regwptr = env->regbase + (env->cwp * 16); in cpu_clone_regs_child()
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| /openbmc/u-boot/arch/arm/include/asm/arch-meson/ |
| H A D | sd_emmc.h | 84 void *regbase; member
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| /openbmc/u-boot/arch/arm/mach-mvebu/include/mach/ |
| H A D | cpu.h | 144 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
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