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Searched refs:reg_offsets (Results 1 – 25 of 28) sorted by relevance

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/openbmc/linux/drivers/i2c/busses/
H A Di2c-mv64xxx.c129 struct mv64xxx_i2c_regs reg_offsets; member
223 drv_data->reg_base + drv_data->reg_offsets.clock); in mv64xxx_i2c_hw_init()
227 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_hw_init()
382 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_do_action()
387 drv_data->reg_base + drv_data->reg_offsets.data); in mv64xxx_i2c_do_action()
389 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_do_action()
394 drv_data->reg_base + drv_data->reg_offsets.data); in mv64xxx_i2c_do_action()
396 drv_data->reg_base + drv_data->reg_offsets.control); in mv64xxx_i2c_do_action()
401 drv_data->reg_base + drv_data->reg_offsets.data); in mv64xxx_i2c_do_action()
904 memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets)); in mv64xxx_of_config()
[all …]
/openbmc/linux/arch/nios2/kernel/
H A Dmisaligned.c49 static int reg_offsets[32]; variable
53 u8 *p = ((u8 *)fp) + reg_offsets[reg]; in get_reg_val()
59 u8 *p = ((u8 *)fp) + reg_offsets[reg]; in put_reg_val()
214 reg_offsets[r] = offset; in misaligned_calc_reg_offsets()
222 reg_offsets[r] = offset; in misaligned_calc_reg_offsets()
/openbmc/linux/drivers/spi/
H A Dspi-bcm63xx.c141 const unsigned long *reg_offsets; member
157 return readb(bs->regs + bs->reg_offsets[offset]); in bcm_spi_readb()
163 writeb(value, bs->regs + bs->reg_offsets[offset]); in bcm_spi_writeb()
170 iowrite16be(value, bs->regs + bs->reg_offsets[offset]); in bcm_spi_writew()
172 writew(value, bs->regs + bs->reg_offsets[offset]); in bcm_spi_writew()
550 bs->reg_offsets = bcm63xx_spireg; in bcm63xx_spi_probe()
551 bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE]; in bcm63xx_spi_probe()
569 bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT]; in bcm63xx_spi_probe()
570 bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH]; in bcm63xx_spi_probe()
571 bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]); in bcm63xx_spi_probe()
[all …]
/openbmc/linux/drivers/net/dsa/
H A Dbcm_sf2.h74 const u16 *reg_offsets; member
196 return readl_relaxed(priv->reg + priv->reg_offsets[off]); in reg_readl()
201 writel_relaxed(val, priv->reg + priv->reg_offsets[off]); in reg_writel()
215 return readl_relaxed(priv->reg + priv->reg_offsets[off] + reg); in reg_led_readl()
220 writel_relaxed(val, priv->reg + priv->reg_offsets[off] + reg); in reg_led_writel()
H A Dbcm_sf2.c1247 const u16 *reg_offsets; member
1276 .reg_offsets = bcm_sf2_4908_reg_offsets,
1301 .reg_offsets = bcm_sf2_7445_reg_offsets,
1324 .reg_offsets = bcm_sf2_7278_reg_offsets,
1386 priv->reg_offsets = data->reg_offsets; in bcm_sf2_sw_probe()
/openbmc/linux/drivers/pci/controller/dwc/
H A Dpcie-al.c136 struct al_pcie_reg_offsets reg_offsets; member
188 pcie->reg_offsets.ob_ctrl = OB_CTRL_REV1_2_OFFSET; in al_pcie_reg_offsets_set()
192 pcie->reg_offsets.ob_ctrl = OB_CTRL_REV3_5_OFFSET; in al_pcie_reg_offsets_set()
213 pcie->reg_offsets.ob_ctrl + CFG_TARGET_BUS, in al_pcie_target_bus_set()
284 cfg_control_offset = AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl + in al_pcie_config_prepare()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce100/
H A Ddce100_hw_sequencer.c43 static const struct dce100_hw_seq_reg_offsets reg_offsets[] = { variable
65 (reg + reg_offsets[id].crtc)
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce112/
H A Ddce112_hw_sequencer.c42 static const struct dce112_hw_seq_reg_offsets reg_offsets[] = { variable
63 (reg + reg_offsets[id].crtc)
H A Ddce112_compressor.c43 static const struct dce112_compressor_reg_offsets reg_offsets[] = { variable
402 cp110->offsets = reg_offsets[params->inst]; in dce112_compressor_enable_fbc()
/openbmc/linux/arch/x86/um/
H A Dptrace_64.c23 static const int reg_offsets[] = variable
107 child->thread.regs.regs.gp[reg_offsets[regno >> 3]] = value; in putreg()
168 return mask & child->thread.regs.regs.gp[reg_offsets[regno >> 3]]; in getreg()
H A Dptrace_32.c56 static const int reg_offsets[] = { variable
121 child->thread.regs.regs.gp[reg_offsets[regno]] = value; in putreg()
173 return mask & child->thread.regs.regs.gp[reg_offsets[regno]]; in getreg()
/openbmc/linux/drivers/net/ethernet/8390/
H A Dxsurf100.c254 static u32 reg_offsets[32]; in xsurf100_probe() local
277 reg_offsets[reg] = 4 * reg; in xsurf100_probe()
284 ax88796_data.ax.reg_offsets = reg_offsets; in xsurf100_probe()
H A Dax88796.c95 u32 reg_offsets[0x20]; member
896 if (ax->plat->reg_offsets) in ax_probe()
897 ei_local->reg_offset = ax->plat->reg_offsets; in ax_probe()
899 ei_local->reg_offset = ax->reg_offsets; in ax_probe()
901 ax->reg_offsets[ret] = (mem_size / 0x18) * ret; in ax_probe()
923 if (!ax->plat->reg_offsets) { in ax_probe()
925 ax->reg_offsets[ret] = (mem_size / 0x20) * ret; in ax_probe()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce120/
H A Ddce120_hw_sequencer.c54 static const struct dce120_hw_seq_reg_offsets reg_offsets[] = {
76 (reg + reg_offsets[id].crtc)
/openbmc/linux/include/net/
H A Dax88796.h28 u32 *reg_offsets; /* register offsets */ member
/openbmc/linux/drivers/pci/controller/
H A Dpcie-iproc-msi.c95 const u16 (*reg_offsets)[IPROC_MSI_REG_SIZE]; member
134 return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_read_reg()
143 writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_write_reg()
574 msi->reg_offsets = iproc_msi_reg_paxb; in iproc_msi_init()
579 msi->reg_offsets = iproc_msi_reg_paxc; in iproc_msi_init()
H A Dpcie-iproc.h89 u16 *reg_offsets; member
H A Dpcie-iproc.c412 return pcie->reg_offsets[reg]; in iproc_pcie_reg_offset()
1441 pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG, in iproc_pcie_rev_init()
1442 sizeof(*pcie->reg_offsets), in iproc_pcie_rev_init()
1444 if (!pcie->reg_offsets) in iproc_pcie_rev_init()
1448 pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ? in iproc_pcie_rev_init()
1451 pcie->reg_offsets[reg_idx] = regs[reg_idx] ? in iproc_pcie_rev_init()
H A Dpcie-brcmstb.c181 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
182 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
183 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
258 const int *reg_offsets; member
1522 pcie->reg_offsets = data->offsets; in brcm_pcie_probe()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce80/
H A Ddce80_timing_generator.c51 static const struct dce110_timing_generator_offsets reg_offsets[] = { variable
234 tg110->derived_offsets = reg_offsets[instance]; in dce80_timing_generator_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_timing_generator.c51 static const struct dce110_timing_generator_offsets reg_offsets[] = { variable
252 tg110->derived_offsets = reg_offsets[instance]; in dce60_timing_generator_construct()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_compressor.c44 static const struct dce110_compressor_reg_offsets reg_offsets[] = { variable
78 cp110->offsets = reg_offsets[crtc_inst]; in reset_lb_on_vblank()
304 cp110->offsets = reg_offsets[params->inst]; in dce110_compressor_program_compressed_surface_address_and_pitch()
/openbmc/linux/drivers/mtd/nand/raw/brcmnand/
H A Dbrcmnand.c265 const u16 *reg_offsets; member
674 ctrl->reg_offsets = brcmnand_regs_v72; in brcmnand_revision_init()
676 ctrl->reg_offsets = brcmnand_regs_v71; in brcmnand_revision_init()
678 ctrl->reg_offsets = brcmnand_regs_v60; in brcmnand_revision_init()
680 ctrl->reg_offsets = brcmnand_regs_v50; in brcmnand_revision_init()
682 ctrl->reg_offsets = brcmnand_regs_v33; in brcmnand_revision_init()
684 ctrl->reg_offsets = brcmnand_regs_v21; in brcmnand_revision_init()
792 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_read_reg()
803 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_write_reg()
932 if (!ctrl->reg_offsets[reg]) in brcmnand_wr_corr_thresh()
[all …]
/openbmc/qemu/hw/isa/
H A Dlpc_ich9.c78 const int reg_offsets[] = { in ich9_cc_update() local
90 for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { in ich9_cc_update()
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_lrc.c682 static const u8 *reg_offsets(const struct intel_engine_cs *engine) in reg_offsets() function
947 set_offsets(regs, reg_offsets(engine), engine, inhibit); in __lrc_init_regs()
1486 set_offsets(ce->lrc_reg_state, reg_offsets(engine), engine, false); in lrc_update_offsets()

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