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Searched refs:reg_num (Results 1 – 17 of 17) sorted by relevance

/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvzacas.c.inc31 static TCGv_i64 get_gpr_pair(DisasContext *ctx, int reg_num)
37 if (reg_num == 0) {
42 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]);
46 static void gen_set_gpr_pair(DisasContext *ctx, int reg_num, TCGv_i64 t)
50 if (reg_num != 0) {
52 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t);
54 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t);
55 tcg_gen_sari_i64(cpu_gpr[reg_num
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/openbmc/qemu/target/loongarch/tcg/
H A Dtranslate.c173 static TCGv gpr_src(DisasContext *ctx, int reg_num, DisasExtend src_ext) in gpr_src() argument
177 if (reg_num == 0) { in gpr_src()
183 return cpu_gpr[reg_num]; in gpr_src()
186 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); in gpr_src()
190 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); in gpr_src()
196 static TCGv gpr_dst(DisasContext *ctx, int reg_num, DisasExtend dst_ext) in gpr_dst() argument
198 if (reg_num == 0 || dst_ext) { in gpr_dst()
201 return cpu_gpr[reg_num]; in gpr_dst()
204 static void gen_set_gpr(int reg_num, TCGv t, DisasExtend dst_ext) in gen_set_gpr() argument
206 if (reg_num ! in gen_set_gpr()
223 get_fpr(DisasContext * ctx,int reg_num) get_fpr() argument
231 set_fpr(int reg_num,TCGv val) set_fpr() argument
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/openbmc/qemu/target/riscv/
H A Dtranslate.c341 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) in get_gpr()
345 if (reg_num == 0) { in get_gpr()
356 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); in get_gpr()
360 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); in get_gpr()
372 return cpu_gpr[reg_num]; in dest_gpr()
375 static TCGv get_gprh(DisasContext *ctx, int reg_num) in dest_gpr()
378 if (reg_num == 0) {
381 return cpu_gprh[reg_num]; in dest_gprh()
384 static TCGv dest_gpr(DisasContext *ctx, int reg_num) in dest_gprh()
386 if (reg_num in dest_gprh()
328 get_gpr(DisasContext * ctx,int reg_num,DisasExtend ext) get_gpr() argument
362 get_gprh(DisasContext * ctx,int reg_num) get_gprh() argument
371 dest_gpr(DisasContext * ctx,int reg_num) dest_gpr() argument
379 dest_gprh(DisasContext * ctx,int reg_num) dest_gprh() argument
387 gen_set_gpr(DisasContext * ctx,int reg_num,TCGv t) gen_set_gpr() argument
408 gen_set_gpri(DisasContext * ctx,int reg_num,target_long imm) gen_set_gpri() argument
429 gen_set_gpr128(DisasContext * ctx,int reg_num,TCGv rl,TCGv rh) gen_set_gpr128() argument
438 get_fpr_hs(DisasContext * ctx,int reg_num) get_fpr_hs() argument
465 get_fpr_d(DisasContext * ctx,int reg_num) get_fpr_d() argument
490 dest_fpr(DisasContext * ctx,int reg_num) dest_fpr() argument
513 gen_set_fpr_hs(DisasContext * ctx,int reg_num,TCGv_i64 t) gen_set_fpr_hs() argument
537 gen_set_fpr_d(DisasContext * ctx,int reg_num,TCGv_i64 t) gen_set_fpr_d() argument
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/openbmc/qemu/tests/qtest/libqos/
H A Dahci.h517 static inline uint32_t ahci_rreg(AHCIQState *ahci, uint32_t reg_num) in ahci_rreg() argument
519 return ahci_mread(ahci, 4 * reg_num); in ahci_rreg()
522 static inline void ahci_wreg(AHCIQState *ahci, uint32_t reg_num, uint32_t value) in ahci_wreg() argument
524 ahci_mwrite(ahci, 4 * reg_num, value); in ahci_wreg()
527 static inline void ahci_set(AHCIQState *ahci, uint32_t reg_num, uint32_t mask) in ahci_set() argument
529 ahci_wreg(ahci, reg_num, ahci_rreg(ahci, reg_num) | mask); in ahci_set()
532 static inline void ahci_clr(AHCIQState *ahci, uint32_t reg_num, uint32_t mask) in ahci_clr() argument
534 ahci_wreg(ahci, reg_num, ahci_rreg(ahci, reg_num) & ~mask); in ahci_clr()
537 static inline size_t ahci_px_offset(uint8_t port, uint32_t reg_num) in ahci_px_offset() argument
539 return AHCI_PORTS + (HBA_PORT_NUM_REG * port) + reg_num; in ahci_px_offset()
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/openbmc/u-boot/drivers/qe/
H A Duccf.c38 u8 *reg_num, u8 *shift) in ucc_get_cmxucr_reg() argument
43 *reg_num = 1; in ucc_get_cmxucr_reg()
48 *reg_num = 1; in ucc_get_cmxucr_reg()
53 *reg_num = 2; in ucc_get_cmxucr_reg()
58 *reg_num = 2; in ucc_get_cmxucr_reg()
63 *reg_num = 3; in ucc_get_cmxucr_reg()
68 *reg_num = 3; in ucc_get_cmxucr_reg()
73 *reg_num = 4; in ucc_get_cmxucr_reg()
78 *reg_num = 4; in ucc_get_cmxucr_reg()
89 u8 reg_num = 0; in ucc_set_clk_src() local
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/openbmc/qemu/target/hexagon/
H A Dgenptr.c170 static inline void gen_read_ctrl_reg(DisasContext *ctx, const int reg_num, in gen_read_ctrl_reg() argument
173 if (reg_num == HEX_REG_P3_0_ALIASED) { in gen_read_ctrl_reg()
175 } else if (reg_num == HEX_REG_PC) { in gen_read_ctrl_reg()
177 } else if (reg_num == HEX_REG_QEMU_PKT_CNT) { in gen_read_ctrl_reg()
180 } else if (reg_num == HEX_REG_QEMU_INSN_CNT) { in gen_read_ctrl_reg()
183 } else if (reg_num == HEX_REG_QEMU_HVX_CNT) { in gen_read_ctrl_reg()
187 tcg_gen_mov_tl(dest, hex_gpr[reg_num]); in gen_read_ctrl_reg()
191 static inline void gen_read_ctrl_reg_pair(DisasContext *ctx, const int reg_num, in gen_read_ctrl_reg_pair() argument
194 if (reg_num == HEX_REG_P3_0_ALIASED) { in gen_read_ctrl_reg_pair()
197 tcg_gen_concat_i32_i64(dest, p3_0, hex_gpr[reg_num in gen_read_ctrl_reg_pair()
237 gen_write_ctrl_reg(DisasContext * ctx,int reg_num,TCGv val) gen_write_ctrl_reg() argument
256 gen_write_ctrl_reg_pair(DisasContext * ctx,int reg_num,TCGv_i64 val) gen_write_ctrl_reg_pair() argument
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H A Dtranslate.c578 int reg_num = ctx->reg_log[i]; in gen_reg_writes() local
580 tcg_gen_mov_tl(hex_gpr[reg_num], get_result_gpr(ctx, reg_num)); in gen_reg_writes()
586 if (reg_num == HEX_REG_SA0) { in gen_reg_writes()
H A Dhex_common.py339 self.reg_num = f"{regtype}{regid}N"
342 const int {self.reg_num} = insn->regno[{regno}];
452 TCGv {self.reg_tcg()} = get_result_gpr(ctx, {self.reg_num});
456 gen_log_reg_write(ctx, {self.reg_num}, {self.reg_tcg()});
461 ctx_log_reg_write(ctx, {self.reg_num}, {predicated});
468 TCGv {self.reg_tcg()} = hex_gpr[{self.reg_num}];
472 ctx_log_reg_read(ctx, {self.reg_num});
482 ctx_log_reg_read_new(ctx, {self.reg_num});
489 TCGv {self.reg_tcg()} = get_result_gpr(ctx, {self.reg_num});
496 tcg_gen_mov_tl({self.reg_tcg()}, hex_gpr[{self.reg_num}]);
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/openbmc/qemu/hw/net/can/
H A Dxlnx-versal-canfd.c859 uint32_t reg_num) in canfd_exit_sleep_mode()
871 /* Check that reg_num should be within TX register space. */ in regs2frame()
872 assert(reg_num <= R_TB_ID_REGISTER + (NUM_REGS_PER_MSG_SPACE * in regs2frame()
875 dlc_reg_val = s->regs[reg_num + 1]; in regs2frame()
878 id_reg_val = s->regs[reg_num]; in regs2frame()
910 frame->data[j] = extract32(s->regs[reg_num + 2 + (j / 4)], val, 8); in regs2frame()
1283 return (tx_reg_1->reg_num < tx_reg_2->reg_num) ? -1 : 1; in g_cmp_ids()
1303 uint32_t reg_num = 0; in prepare_tx_data()
1309 reg_num in prepare_tx_data()
863 regs2frame(XlnxVersalCANFDState * s,qemu_can_frame * frame,uint32_t reg_num) regs2frame() argument
1307 uint32_t reg_num = 0; prepare_tx_data() local
1895 int reg_num; canfd_create_rai() local
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/openbmc/qemu/include/hw/net/
H A Dxlnx-versal-canfd.h76 uint32_t reg_num;
84 uint32_t reg_num; global() member
/openbmc/qemu/hw/net/
H A Dcadence_gem.c1509 static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num) in gem_phy_read()
1511 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]);
1512 return s->phy_regs[reg_num]; in gem_phy_write() argument
1515 static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val) in gem_phy_write()
1517 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val); in gem_phy_write()
1519 switch (reg_num) { in gem_phy_write()
1540 s->phy_regs[reg_num] = val; in gem_handle_phy_access()
1546 uint32_t phy_addr, reg_num; in gem_handle_phy_access()
1566 reg_num in gem_handle_phy_access()
1506 gem_phy_read(CadenceGEMState * s,unsigned reg_num) gem_phy_read() argument
1543 uint32_t phy_addr, reg_num; gem_handle_phy_access() local
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/openbmc/u-boot/drivers/net/ti/
H A Ddavinci_emac.h293 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
294 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
H A Ddavinci_emac.c206 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) in davinci_eth_phy_read() argument
215 ((reg_num & 0x1f) << 21) | in davinci_eth_phy_read()
232 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) in davinci_eth_phy_write() argument
240 ((reg_num & 0x1f) << 21) | in davinci_eth_phy_write()
/openbmc/u-boot/drivers/net/phy/
H A Dmarvell.c309 u8 reg_num, u16 offset, u16 len, u16 data) in m88e1518_phy_writebits() argument
318 reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num); in m88e1518_phy_writebits()
323 phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg); in m88e1518_phy_writebits()
/openbmc/qemu/hw/ide/
H A Dcore.c1282 int reg_num = addr & 7; in ide_ioport_write() local
1284 trace_ide_ioport_write(addr, ATA_IOPORT_WR_lookup[reg_num], val, bus, s); in ide_ioport_write()
1287 if (reg_num != 7 && (s->status & (BUSY_STAT|DRQ_STAT))) { in ide_ioport_write()
1294 switch (reg_num) { in ide_ioport_write()
2225 uint32_t reg_num; in ide_ioport_read() local
2228 reg_num = addr & 7; in ide_ioport_read()
2230 switch (reg_num) { in ide_ioport_read()
2303 trace_ide_ioport_read(addr, ATA_IOPORT_RR_lookup[reg_num], ret, bus, s); in ide_ioport_read()
/openbmc/qemu/disas/
H A Driscv.c4064 int imm_mop5, imm_mop3, reg_num; in decode_inst_opcode() local
4080 reg_num = (inst >> 15) & 0b011111; in decode_inst_opcode()
4082 ((reg_num == 1) || (reg_num == 5))) { in decode_inst_opcode()
4095 reg_num = (inst >> 20) & 0b011111; in decode_inst_opcode()
4098 ((reg_num == 1) || (reg_num == 5))) { in decode_inst_opcode()
/openbmc/qemu/hw/cxl/
H A Dcxl-mailbox-utils.c3578 uint8_t reg_num; in cmd_fm_initiate_dc_add() member
3665 uint8_t reg_num; in cmd_fm_initiate_dc_release() member