/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/ |
H A D | irq_service_dcn201.c | 166 #define hpd_int_entry(reg_num)\ argument 168 IRQ_REG_ENTRY(HPD, reg_num,\ 175 #define hpd_rx_int_entry(reg_num)\ argument 177 IRQ_REG_ENTRY(HPD, reg_num,\ 183 #define pflip_int_entry(reg_num)\ argument 185 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 193 IRQ_REG_ENTRY(OTG, reg_num,\ 204 IRQ_REG_ENTRY(OTG, reg_num,\ 211 IRQ_REG_ENTRY(OTG, reg_num,\ 219 IRQ_REG_ENTRY(OTG, reg_num,\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dce120/ |
H A D | irq_service_dce120.c | 117 #define hpd_int_entry(reg_num)\ argument 119 IRQ_REG_ENTRY(HPD, reg_num,\ 126 #define hpd_rx_int_entry(reg_num)\ argument 128 IRQ_REG_ENTRY(HPD, reg_num,\ 134 #define pflip_int_entry(reg_num)\ argument 136 IRQ_REG_ENTRY(DCP, reg_num, \ 143 #define vupdate_int_entry(reg_num)\ argument 145 IRQ_REG_ENTRY(CRTC, reg_num,\ 151 #define vblank_int_entry(reg_num)\ argument 153 IRQ_REG_ENTRY(CRTC, reg_num,\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
H A D | irq_service_dcn303.c | 132 #define hpd_int_entry(reg_num)\ argument 134 IRQ_REG_ENTRY(HPD, reg_num,\ 141 #define hpd_rx_int_entry(reg_num)\ argument 143 IRQ_REG_ENTRY(HPD, reg_num,\ 149 #define pflip_int_entry(reg_num)\ argument 162 IRQ_REG_ENTRY(OTG, reg_num,\ 168 #define vblank_int_entry(reg_num)\ argument 170 IRQ_REG_ENTRY(OTG, reg_num,\ 176 #define vline0_int_entry(reg_num)\ argument 178 IRQ_REG_ENTRY(OTG, reg_num,\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dce80/ |
H A D | irq_service_dce80.c | 92 #define hpd_int_entry(reg_num)\ argument 93 [DC_IRQ_SOURCE_INVALID + reg_num] = {\ 107 #define hpd_rx_int_entry(reg_num)\ argument 108 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\ 121 #define pflip_int_entry(reg_num)\ argument 122 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 136 #define vupdate_int_entry(reg_num)\ argument 152 #define vblank_int_entry(reg_num)\ argument 174 #define i2c_int_entry(reg_num) \ argument 177 #define dp_sink_int_entry(reg_num) \ argument [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
H A D | irq_service_dcn10.c | 214 #define hpd_int_entry(reg_num)\ argument 216 IRQ_REG_ENTRY(HPD, reg_num,\ 223 #define hpd_rx_int_entry(reg_num)\ argument 225 IRQ_REG_ENTRY(HPD, reg_num,\ 231 #define pflip_int_entry(reg_num)\ argument 233 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 244 IRQ_REG_ENTRY(OTG, reg_num,\ 250 #define vblank_int_entry(reg_num)\ argument 252 IRQ_REG_ENTRY(OTG, reg_num,\ 260 IRQ_REG_ENTRY(OTG, reg_num,\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
H A D | irq_service_dcn20.c | 221 #define hpd_int_entry(reg_num)\ argument 223 IRQ_REG_ENTRY(HPD, reg_num,\ 230 #define hpd_rx_int_entry(reg_num)\ argument 232 IRQ_REG_ENTRY(HPD, reg_num,\ 238 #define pflip_int_entry(reg_num)\ argument 240 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 251 IRQ_REG_ENTRY(OTG, reg_num,\ 257 #define vblank_int_entry(reg_num)\ argument 259 IRQ_REG_ENTRY(OTG, reg_num,\ 267 IRQ_REG_ENTRY(OTG, reg_num,\ [all …]
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/openbmc/linux/arch/sparc/kernel/ |
H A D | pcr.c | 59 WARN_ON_ONCE(reg_num != 0); in direct_pcr_read() 66 WARN_ON_ONCE(reg_num != 0); in direct_pcr_write() 74 WARN_ON_ONCE(reg_num != 0); in direct_pic_read() 81 WARN_ON_ONCE(reg_num != 0); in direct_pic_write() 115 WARN_ON_ONCE(reg_num != 0); in n2_pcr_write() 119 direct_pcr_write(reg_num, val); in n2_pcr_write() 121 direct_pcr_write(reg_num, val); in n2_pcr_write() 148 (void) sun4v_vt_get_perfreg(reg_num, &val); in n4_pcr_read() 155 (void) sun4v_vt_set_perfreg(reg_num, val); in n4_pcr_write() 206 (void) sun4v_t5_set_perfreg(reg_num, val); in n5_pcr_write() [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dce60/ |
H A D | irq_service_dce60.c | 101 #define hpd_int_entry(reg_num)\ argument 102 [DC_IRQ_SOURCE_INVALID + reg_num] = {\ 116 #define hpd_rx_int_entry(reg_num)\ argument 117 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\ 130 #define pflip_int_entry(reg_num)\ argument 131 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 145 #define vupdate_int_entry(reg_num)\ argument 161 #define vblank_int_entry(reg_num)\ argument 182 #define i2c_int_entry(reg_num) \ argument 185 #define dp_sink_int_entry(reg_num) \ argument [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
H A D | irq_service_dcn302.c | 227 #define hpd_int_entry(reg_num)\ argument 229 IRQ_REG_ENTRY(HPD, reg_num,\ 236 #define hpd_rx_int_entry(reg_num)\ argument 238 IRQ_REG_ENTRY(HPD, reg_num,\ 244 #define pflip_int_entry(reg_num)\ argument 257 IRQ_REG_ENTRY(OTG, reg_num,\ 263 #define vblank_int_entry(reg_num)\ argument 265 IRQ_REG_ENTRY(OTG, reg_num,\ 271 #define vline0_int_entry(reg_num)\ argument 273 IRQ_REG_ENTRY(OTG, reg_num,\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
H A D | irq_service_dcn21.c | 243 #define hpd_int_entry(reg_num)\ argument 245 IRQ_REG_ENTRY(HPD, reg_num,\ 252 #define hpd_rx_int_entry(reg_num)\ argument 254 IRQ_REG_ENTRY(HPD, reg_num,\ 260 #define pflip_int_entry(reg_num)\ argument 262 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 273 IRQ_REG_ENTRY(OTG, reg_num,\ 279 #define vblank_int_entry(reg_num)\ argument 281 IRQ_REG_ENTRY(OTG, reg_num,\ 289 IRQ_REG_ENTRY(OTG, reg_num,\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn314/ |
H A D | irq_service_dcn314.c | 238 #define hpd_int_entry(reg_num)\ argument 240 IRQ_REG_ENTRY(HPD, reg_num,\ 247 #define hpd_rx_int_entry(reg_num)\ argument 249 IRQ_REG_ENTRY(HPD, reg_num,\ 255 #define pflip_int_entry(reg_num)\ argument 257 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 268 IRQ_REG_ENTRY(OTG, reg_num,\ 274 #define vblank_int_entry(reg_num)\ argument 276 IRQ_REG_ENTRY(OTG, reg_num,\ 284 IRQ_REG_ENTRY(OTG, reg_num,\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/ |
H A D | irq_service_dcn315.c | 243 #define hpd_int_entry(reg_num)\ argument 245 IRQ_REG_ENTRY(HPD, reg_num,\ 252 #define hpd_rx_int_entry(reg_num)\ argument 254 IRQ_REG_ENTRY(HPD, reg_num,\ 260 #define pflip_int_entry(reg_num)\ argument 262 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 273 IRQ_REG_ENTRY(OTG, reg_num,\ 279 #define vblank_int_entry(reg_num)\ argument 281 IRQ_REG_ENTRY(OTG, reg_num,\ 289 IRQ_REG_ENTRY(OTG, reg_num,\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
H A D | irq_service_dcn31.c | 236 #define hpd_int_entry(reg_num)\ argument 238 IRQ_REG_ENTRY(HPD, reg_num,\ 245 #define hpd_rx_int_entry(reg_num)\ argument 247 IRQ_REG_ENTRY(HPD, reg_num,\ 253 #define pflip_int_entry(reg_num)\ argument 255 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 266 IRQ_REG_ENTRY(OTG, reg_num,\ 272 #define vblank_int_entry(reg_num)\ argument 274 IRQ_REG_ENTRY(OTG, reg_num,\ 282 IRQ_REG_ENTRY(OTG, reg_num,\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn32/ |
H A D | irq_service_dcn32.c | 237 #define hpd_int_entry(reg_num)\ argument 239 IRQ_REG_ENTRY(HPD, reg_num,\ 246 #define hpd_rx_int_entry(reg_num)\ argument 248 IRQ_REG_ENTRY(HPD, reg_num,\ 254 #define pflip_int_entry(reg_num)\ argument 256 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 267 IRQ_REG_ENTRY(OTG, reg_num,\ 273 #define vblank_int_entry(reg_num)\ argument 275 IRQ_REG_ENTRY(OTG, reg_num,\ 283 IRQ_REG_ENTRY(OTG, reg_num,\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
H A D | irq_service_dcn30.c | 248 #define hpd_int_entry(reg_num)\ argument 250 IRQ_REG_ENTRY(HPD, reg_num,\ 257 #define hpd_rx_int_entry(reg_num)\ argument 259 IRQ_REG_ENTRY(HPD, reg_num,\ 265 #define pflip_int_entry(reg_num)\ argument 267 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 278 IRQ_REG_ENTRY(OTG, reg_num,\ 284 #define vblank_int_entry(reg_num)\ argument 286 IRQ_REG_ENTRY(OTG, reg_num,\ 301 IRQ_REG_ENTRY(OTG, reg_num,\ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dce110/ |
H A D | irq_service_dce110.c | 89 #define hpd_int_entry(reg_num)\ argument 90 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ 104 #define hpd_rx_int_entry(reg_num)\ argument 105 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ 117 #define pflip_int_entry(reg_num)\ argument 118 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 132 #define vupdate_int_entry(reg_num)\ argument 148 #define vblank_int_entry(reg_num)\ argument 170 #define i2c_int_entry(reg_num) \ argument 173 #define dp_sink_int_entry(reg_num) \ argument [all …]
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/openbmc/linux/arch/riscv/kvm/ |
H A D | vcpu_onereg.c | 132 switch (reg_num) { in kvm_riscv_vcpu_get_reg_config() 184 switch (reg_num) { in kvm_riscv_vcpu_set_reg_config() 341 unsigned long reg_num, in kvm_riscv_vcpu_general_get_csr() argument 360 unsigned long reg_num, in kvm_riscv_vcpu_general_set_csr() argument 396 reg_num &= ~KVM_REG_RISCV_SUBTYPE_MASK; in kvm_riscv_vcpu_get_reg_csr() 454 unsigned long reg_num, in riscv_vcpu_get_isa_ext_single() argument 475 unsigned long reg_num, in riscv_vcpu_set_isa_ext_single() argument 513 unsigned long reg_num, in riscv_vcpu_get_isa_ext_multi() argument 522 ext_id = i + reg_num * BITS_PER_LONG; in riscv_vcpu_get_isa_ext_multi() 536 unsigned long reg_num, in riscv_vcpu_set_isa_ext_multi() argument [all …]
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H A D | vcpu_fp.c | 93 if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr)) in kvm_riscv_vcpu_get_reg_fp() 96 reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) in kvm_riscv_vcpu_get_reg_fp() 97 reg_val = &cntx->fp.f.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp() 102 if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { in kvm_riscv_vcpu_get_reg_fp() 107 reg_num <= KVM_REG_RISCV_FP_D_REG(f[31])) { in kvm_riscv_vcpu_get_reg_fp() 110 reg_val = &cntx->fp.d.f[reg_num]; in kvm_riscv_vcpu_get_reg_fp() 138 if (reg_num == KVM_REG_RISCV_FP_F_REG(fcsr)) in kvm_riscv_vcpu_set_reg_fp() 141 reg_num <= KVM_REG_RISCV_FP_F_REG(f[31])) in kvm_riscv_vcpu_set_reg_fp() 142 reg_val = &cntx->fp.f.f[reg_num]; in kvm_riscv_vcpu_set_reg_fp() 147 if (reg_num == KVM_REG_RISCV_FP_D_REG(fcsr)) { in kvm_riscv_vcpu_set_reg_fp() [all …]
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H A D | vcpu_sbi.c | 136 unsigned long reg_num, in riscv_vcpu_set_sbi_ext_single() argument 143 if (reg_num >= KVM_RISCV_SBI_EXT_MAX) in riscv_vcpu_set_sbi_ext_single() 150 if (sbi_ext[i].ext_idx == reg_num) { in riscv_vcpu_set_sbi_ext_single() 172 unsigned long reg_num, in riscv_vcpu_get_sbi_ext_single() argument 179 if (reg_num >= KVM_RISCV_SBI_EXT_MAX) in riscv_vcpu_get_sbi_ext_single() 183 if (sbi_ext[i].ext_idx == reg_num) { in riscv_vcpu_get_sbi_ext_single() 205 unsigned long reg_num, in riscv_vcpu_set_sbi_ext_multi() argument 214 ext_id = i + reg_num * BITS_PER_LONG; in riscv_vcpu_set_sbi_ext_multi() 225 unsigned long reg_num, in riscv_vcpu_get_sbi_ext_multi() argument 234 ext_id = i + reg_num * BITS_PER_LONG; in riscv_vcpu_get_sbi_ext_multi() [all …]
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H A D | vcpu_vector.c | 95 unsigned long reg_num, in kvm_riscv_vcpu_vreg_addr() argument 102 if (reg_num < KVM_REG_RISCV_VECTOR_REG(0)) { in kvm_riscv_vcpu_vreg_addr() 105 switch (reg_num) { in kvm_riscv_vcpu_vreg_addr() 122 } else if (reg_num <= KVM_REG_RISCV_VECTOR_REG(31)) { in kvm_riscv_vcpu_vreg_addr() 126 (reg_num - KVM_REG_RISCV_VECTOR_REG(0)) * vlenb; in kvm_riscv_vcpu_vreg_addr() 140 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_get_reg_vector() local 150 rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, ®_addr); in kvm_riscv_vcpu_get_reg_vector() 166 unsigned long reg_num = reg->id & ~(KVM_REG_ARCH_MASK | in kvm_riscv_vcpu_set_reg_vector() local 176 rc = kvm_riscv_vcpu_vreg_addr(vcpu, reg_num, reg_size, ®_addr); in kvm_riscv_vcpu_set_reg_vector()
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/openbmc/linux/drivers/video/fbdev/via/ |
H A D | hw.h | 355 int reg_num; member 361 int reg_num; member 367 int reg_num; member 373 int reg_num; member 379 int reg_num; member 385 int reg_num; member 391 int reg_num; member 397 int reg_num; member 403 int reg_num; member 409 int reg_num; member [all …]
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/openbmc/qemu/target/riscv/ |
H A D | translate.c | 325 if (reg_num == 0) { in get_gpr() 358 if (reg_num == 0) { in get_gprh() 374 if (reg_num == 0) { in dest_gprh() 382 if (reg_num != 0) { in gen_set_gpr() 396 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); in gen_set_gpr() 403 if (reg_num != 0) { in gen_set_gpri() 425 if (reg_num != 0) { in gen_set_gpr128() 437 if (reg_num == 0) { in get_fpr_hs() 464 if (reg_num == 0) { in get_fpr_d() 471 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); in get_fpr_d() [all …]
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/openbmc/qemu/target/loongarch/ |
H A D | translate.c | 175 if (reg_num == 0) { in gpr_src() 181 return cpu_gpr[reg_num]; in gpr_src() 184 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); in gpr_src() 188 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); in gpr_src() 196 if (reg_num == 0 || dst_ext) { in gpr_dst() 199 return cpu_gpr[reg_num]; in gpr_dst() 204 if (reg_num != 0) { in gen_set_gpr() 207 tcg_gen_mov_tl(cpu_gpr[reg_num], t); in gen_set_gpr() 210 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); in gen_set_gpr() 213 tcg_gen_ext32u_tl(cpu_gpr[reg_num], t); in gen_set_gpr() [all …]
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/openbmc/linux/drivers/irqchip/ |
H A D | irq-imx-irqsteer.c | 35 int reg_num; member 44 return (data->reg_num - irqnum / 32 - 1); in imx_irqsteer_get_reg_index() 55 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_unmask() 129 if (hwirq >= data->reg_num * 32) in imx_irqsteer_irq_handler() 133 CHANSTATUS(idx, data->reg_num)); in imx_irqsteer_irq_handler() 178 data->reg_num = irqs_num / 32; in imx_irqsteer_probe() 182 sizeof(u32) * data->reg_num, in imx_irqsteer_probe() 255 for (i = 0; i < data->reg_num; i++) in imx_irqsteer_save_regs() 257 CHANMASK(i, data->reg_num)); in imx_irqsteer_save_regs() 265 for (i = 0; i < data->reg_num; i++) in imx_irqsteer_restore_regs() [all …]
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/openbmc/qemu/tests/qtest/libqos/ |
H A D | ahci.h | 519 return ahci_mread(ahci, 4 * reg_num); in ahci_rreg() 524 ahci_mwrite(ahci, 4 * reg_num, value); in ahci_wreg() 529 ahci_wreg(ahci, reg_num, ahci_rreg(ahci, reg_num) | mask); in ahci_set() 534 ahci_wreg(ahci, reg_num, ahci_rreg(ahci, reg_num) & ~mask); in ahci_clr() 539 return AHCI_PORTS + (HBA_PORT_NUM_REG * port) + reg_num; in ahci_px_offset() 543 uint32_t reg_num) in ahci_px_rreg() argument 545 return ahci_rreg(ahci, ahci_px_offset(port, reg_num)); in ahci_px_rreg() 551 ahci_wreg(ahci, ahci_px_offset(port, reg_num), value); in ahci_px_wreg() 557 ahci_px_wreg(ahci, port, reg_num, in ahci_px_set() 558 ahci_px_rreg(ahci, port, reg_num) | mask); in ahci_px_set() [all …]
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