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Searched refs:reg_cfg (Results 1 – 20 of 20) sorted by relevance

/openbmc/linux/drivers/clk/mediatek/
H A Dclk-fhctl.c62 readl(regs->reg_cfg), readl(regs->reg_updnlmt), in dump_hw()
73 writel((readl(regs->reg_cfg) & ~(data->frddsx_en)), regs->reg_cfg); in fhctl_set_ssc_regs()
74 writel((readl(regs->reg_cfg) & ~(data->sfstrx_en)), regs->reg_cfg); in fhctl_set_ssc_regs()
75 writel((readl(regs->reg_cfg) & ~(data->fhctlx_en)), regs->reg_cfg); in fhctl_set_ssc_regs()
79 r = readl(regs->reg_cfg); in fhctl_set_ssc_regs()
82 writel(r, regs->reg_cfg); in fhctl_set_ssc_regs()
84 r = readl(regs->reg_cfg); in fhctl_set_ssc_regs()
87 writel(r, regs->reg_cfg); in fhctl_set_ssc_regs()
101 writel(readl(regs->reg_cfg) | data->frddsx_en, regs->reg_cfg); in fhctl_set_ssc_regs()
103 writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg); in fhctl_set_ssc_regs()
[all …]
H A Dclk-pllfh.h50 void __iomem *reg_cfg; member
H A Dclk-pllfh.c132 regs->reg_cfg = fhx_base + offset->offset_cfg; in pllfh_init()
/openbmc/linux/drivers/dma/
H A Dste_dma40_ll.c137 u32 reg_cfg, in d40_phy_fill_lli() argument
172 lli->reg_cfg = reg_cfg; in d40_phy_fill_lli()
182 lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS); in d40_phy_fill_lli()
184 lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS); in d40_phy_fill_lli()
214 dma_addr_t lli_phys, dma_addr_t first_phys, u32 reg_cfg, in d40_phy_buf_to_lli() argument
250 reg_cfg, info, flags); in d40_phy_buf_to_lli()
271 u32 reg_cfg, in d40_phy_sg_to_lli() argument
299 reg_cfg, info, otherinfo, flags); in d40_phy_sg_to_lli()
364 u32 reg_cfg, in d40_log_fill_lli() argument
370 lli->lcsp13 = reg_cfg; in d40_log_fill_lli()
H A Dste_dma40_ll.h345 u32 reg_cfg; member
446 u32 reg_cfg,
H A Dste_dma40.c837 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG); in d40_phy_lli_load()
842 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG); in d40_phy_lli_load()
/openbmc/linux/drivers/gpu/drm/bridge/
H A Dlontium-lt9611.c94 const struct reg_sequence reg_cfg[] = { in lt9611_mipi_input_analog() local
106 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_analog()
112 struct reg_sequence reg_cfg[] = { in lt9611_mipi_input_digital() local
122 reg_cfg[1].def = 0x03; in lt9611_mipi_input_digital()
124 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_digital()
175 const struct reg_sequence reg_cfg[] = { in lt9611_pcr_setup() local
202 regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_pcr_setup()
225 const struct reg_sequence reg_cfg[] = { in lt9611_pll_setup() local
239 regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_pll_setup()
389 struct reg_sequence reg_cfg[] = { in lt9611_hdmi_tx_phy() local
[all …]
/openbmc/linux/drivers/regulator/
H A Drt5759-regulator.c214 struct regulator_config reg_cfg; in rt5759_regulator_register() local
246 memset(&reg_cfg, 0, sizeof(reg_cfg)); in rt5759_regulator_register()
247 reg_cfg.dev = priv->dev; in rt5759_regulator_register()
248 reg_cfg.of_node = np; in rt5759_regulator_register()
249 reg_cfg.init_data = of_get_regulator_init_data(priv->dev, np, reg_desc); in rt5759_regulator_register()
250 reg_cfg.regmap = priv->regmap; in rt5759_regulator_register()
252 rdev = devm_regulator_register(priv->dev, reg_desc, &reg_cfg); in rt5759_regulator_register()
H A Drtq6752-regulator.c222 struct regulator_config reg_cfg = {}; in rtq6752_probe() local
255 reg_cfg.dev = &i2c->dev; in rtq6752_probe()
256 reg_cfg.regmap = priv->regmap; in rtq6752_probe()
257 reg_cfg.driver_data = priv; in rtq6752_probe()
262 &reg_cfg); in rtq6752_probe()
/openbmc/linux/drivers/ata/
H A Dpata_octeon_cf.c87 union cvmx_mio_boot_reg_cfgx reg_cfg; in octeon_cf_set_boot_reg_cfg() local
105 reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); in octeon_cf_set_boot_reg_cfg()
106 reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */ in octeon_cf_set_boot_reg_cfg()
107 reg_cfg.s.tim_mult = tim_mult; /* Timing mutiplier */ in octeon_cf_set_boot_reg_cfg()
108 reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */ in octeon_cf_set_boot_reg_cfg()
109 reg_cfg.s.sam = 0; /* Don't combine write and output enable */ in octeon_cf_set_boot_reg_cfg()
110 reg_cfg.s.we_ext = 0; /* No write enable extension */ in octeon_cf_set_boot_reg_cfg()
111 reg_cfg.s.oe_ext = 0; /* No read enable extension */ in octeon_cf_set_boot_reg_cfg()
112 reg_cfg.s.en = 1; /* Enable this region */ in octeon_cf_set_boot_reg_cfg()
113 reg_cfg.s.orbit = 0; /* Don't combine with previous region */ in octeon_cf_set_boot_reg_cfg()
[all …]
/openbmc/linux/include/linux/soc/ti/
H A Domap1-mux.h306 extern int omap_cfg_reg(unsigned long reg_cfg);
308 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; } in omap_cfg_reg() argument
/openbmc/linux/drivers/iommu/
H A Dsprd-iommu.c216 unsigned int reg_cfg; in sprd_iommu_hw_en() local
220 reg_cfg = SPRD_EX_CFG; in sprd_iommu_hw_en()
222 reg_cfg = SPRD_VAU_CFG; in sprd_iommu_hw_en()
226 sprd_iommu_update_bits(sdev, reg_cfg, mask, 0, val); in sprd_iommu_hw_en()
/openbmc/linux/arch/arm/mach-davinci/
H A Dmux.h656 extern int davinci_cfg_reg(unsigned long reg_cfg);
660 static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; } in davinci_cfg_reg() argument
/openbmc/linux/drivers/clk/sprd/
H A Dpll.h13 struct reg_cfg { struct
H A Dpll.c151 struct reg_cfg *cfg; in _sprd_pll_set_rate()
/openbmc/linux/drivers/net/wireless/realtek/rtw88/
H A Dsdio.c154 u32 reg_cfg; in rtw_sdio_indirect_reg_cfg() local
158 reg_cfg = rtw_sdio_to_bus_offset(rtwdev, REG_SDIO_INDIRECT_REG_CFG); in rtw_sdio_indirect_reg_cfg()
161 reg_cfg, &ret); in rtw_sdio_indirect_reg_cfg()
166 tmp = sdio_readb(rtwsdio->sdio_func, reg_cfg + 2, &ret); in rtw_sdio_indirect_reg_cfg()
/openbmc/linux/drivers/leds/rgb/
H A Dleds-mt6370-rgb.c152 struct reg_cfg *reg_cfgs;
/openbmc/linux/drivers/net/wireless/marvell/mwifiex/
H A Dsta_cmdresp.c1129 struct host_cmd_ds_chan_region_cfg *reg = &resp->params.reg_cfg; in mwifiex_ret_chan_region_cfg()
H A Dfw.h2376 struct host_cmd_ds_chan_region_cfg reg_cfg; member
H A Dsta_cmd.c1606 struct host_cmd_ds_chan_region_cfg *reg = &cmd->params.reg_cfg; in mwifiex_cmd_chan_region_cfg()