1d7964de8SJohnson Wang // SPDX-License-Identifier: GPL-2.0-only
2d7964de8SJohnson Wang /*
3d7964de8SJohnson Wang * Copyright (c) 2022 MediaTek Inc.
4d7964de8SJohnson Wang * Author: Edward-JW Yang <edward-jw.yang@mediatek.com>
5d7964de8SJohnson Wang */
6d7964de8SJohnson Wang
7d7964de8SJohnson Wang #include <linux/io.h>
8d7964de8SJohnson Wang #include <linux/iopoll.h>
9d7964de8SJohnson Wang
10d7964de8SJohnson Wang #include "clk-mtk.h"
11d7964de8SJohnson Wang #include "clk-pllfh.h"
12d7964de8SJohnson Wang #include "clk-fhctl.h"
13d7964de8SJohnson Wang
14d7964de8SJohnson Wang #define PERCENT_TO_DDSLMT(dds, percent_m10) \
15d7964de8SJohnson Wang ((((dds) * (percent_m10)) >> 5) / 100)
16d7964de8SJohnson Wang
17*cb9eee59STom Rix static const struct fhctl_offset fhctl_offset_v1 = {
188da312d6SAngeloGioacchino Del Regno .offset_hp_en = 0x0,
198da312d6SAngeloGioacchino Del Regno .offset_clk_con = 0x4,
208da312d6SAngeloGioacchino Del Regno .offset_rst_con = 0x8,
218da312d6SAngeloGioacchino Del Regno .offset_slope0 = 0xc,
228da312d6SAngeloGioacchino Del Regno .offset_slope1 = 0x10,
238da312d6SAngeloGioacchino Del Regno .offset_cfg = 0x0,
248da312d6SAngeloGioacchino Del Regno .offset_updnlmt = 0x4,
258da312d6SAngeloGioacchino Del Regno .offset_dds = 0x8,
268da312d6SAngeloGioacchino Del Regno .offset_dvfs = 0xc,
278da312d6SAngeloGioacchino Del Regno .offset_mon = 0x10,
288da312d6SAngeloGioacchino Del Regno };
298da312d6SAngeloGioacchino Del Regno
30*cb9eee59STom Rix static const struct fhctl_offset fhctl_offset_v2 = {
31d7964de8SJohnson Wang .offset_hp_en = 0x0,
32d7964de8SJohnson Wang .offset_clk_con = 0x8,
33d7964de8SJohnson Wang .offset_rst_con = 0xc,
34d7964de8SJohnson Wang .offset_slope0 = 0x10,
35d7964de8SJohnson Wang .offset_slope1 = 0x14,
36d7964de8SJohnson Wang .offset_cfg = 0x0,
37d7964de8SJohnson Wang .offset_updnlmt = 0x4,
38d7964de8SJohnson Wang .offset_dds = 0x8,
39d7964de8SJohnson Wang .offset_dvfs = 0xc,
40d7964de8SJohnson Wang .offset_mon = 0x10,
41d7964de8SJohnson Wang };
42d7964de8SJohnson Wang
fhctl_get_offset_table(enum fhctl_variant v)438da312d6SAngeloGioacchino Del Regno const struct fhctl_offset *fhctl_get_offset_table(enum fhctl_variant v)
44d7964de8SJohnson Wang {
458da312d6SAngeloGioacchino Del Regno switch (v) {
468da312d6SAngeloGioacchino Del Regno case FHCTL_PLLFH_V1:
478da312d6SAngeloGioacchino Del Regno return &fhctl_offset_v1;
488da312d6SAngeloGioacchino Del Regno case FHCTL_PLLFH_V2:
498da312d6SAngeloGioacchino Del Regno return &fhctl_offset_v2;
508da312d6SAngeloGioacchino Del Regno default:
518da312d6SAngeloGioacchino Del Regno return ERR_PTR(-EINVAL);
528da312d6SAngeloGioacchino Del Regno };
53d7964de8SJohnson Wang }
54d7964de8SJohnson Wang
dump_hw(struct mtk_clk_pll * pll,struct fh_pll_regs * regs,const struct fh_pll_data * data)55d7964de8SJohnson Wang static void dump_hw(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
56d7964de8SJohnson Wang const struct fh_pll_data *data)
57d7964de8SJohnson Wang {
58d7964de8SJohnson Wang pr_info("hp_en<%x>,clk_con<%x>,slope0<%x>,slope1<%x>\n",
59d7964de8SJohnson Wang readl(regs->reg_hp_en), readl(regs->reg_clk_con),
60d7964de8SJohnson Wang readl(regs->reg_slope0), readl(regs->reg_slope1));
61d7964de8SJohnson Wang pr_info("cfg<%x>,lmt<%x>,dds<%x>,dvfs<%x>,mon<%x>\n",
62d7964de8SJohnson Wang readl(regs->reg_cfg), readl(regs->reg_updnlmt),
63d7964de8SJohnson Wang readl(regs->reg_dds), readl(regs->reg_dvfs),
64d7964de8SJohnson Wang readl(regs->reg_mon));
65d7964de8SJohnson Wang pr_info("pcw<%x>\n", readl(pll->pcw_addr));
66d7964de8SJohnson Wang }
67d7964de8SJohnson Wang
fhctl_set_ssc_regs(struct mtk_clk_pll * pll,struct fh_pll_regs * regs,const struct fh_pll_data * data,u32 rate)68d7964de8SJohnson Wang static int fhctl_set_ssc_regs(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
69d7964de8SJohnson Wang const struct fh_pll_data *data, u32 rate)
70d7964de8SJohnson Wang {
71d7964de8SJohnson Wang u32 updnlmt_val, r;
72d7964de8SJohnson Wang
73d7964de8SJohnson Wang writel((readl(regs->reg_cfg) & ~(data->frddsx_en)), regs->reg_cfg);
74d7964de8SJohnson Wang writel((readl(regs->reg_cfg) & ~(data->sfstrx_en)), regs->reg_cfg);
75d7964de8SJohnson Wang writel((readl(regs->reg_cfg) & ~(data->fhctlx_en)), regs->reg_cfg);
76d7964de8SJohnson Wang
77d7964de8SJohnson Wang if (rate > 0) {
78d7964de8SJohnson Wang /* Set the relative parameter registers (dt/df/upbnd/downbnd) */
79d7964de8SJohnson Wang r = readl(regs->reg_cfg);
80d7964de8SJohnson Wang r &= ~(data->msk_frddsx_dys);
81d7964de8SJohnson Wang r |= (data->df_val << (ffs(data->msk_frddsx_dys) - 1));
82d7964de8SJohnson Wang writel(r, regs->reg_cfg);
83d7964de8SJohnson Wang
84d7964de8SJohnson Wang r = readl(regs->reg_cfg);
85d7964de8SJohnson Wang r &= ~(data->msk_frddsx_dts);
86d7964de8SJohnson Wang r |= (data->dt_val << (ffs(data->msk_frddsx_dts) - 1));
87d7964de8SJohnson Wang writel(r, regs->reg_cfg);
88d7964de8SJohnson Wang
89d7964de8SJohnson Wang writel((readl(pll->pcw_addr) & data->dds_mask) | data->tgl_org,
90d7964de8SJohnson Wang regs->reg_dds);
91d7964de8SJohnson Wang
92d7964de8SJohnson Wang /* Calculate UPDNLMT */
93d7964de8SJohnson Wang updnlmt_val = PERCENT_TO_DDSLMT((readl(regs->reg_dds) &
94d7964de8SJohnson Wang data->dds_mask), rate) <<
95d7964de8SJohnson Wang data->updnlmt_shft;
96d7964de8SJohnson Wang
97d7964de8SJohnson Wang writel(updnlmt_val, regs->reg_updnlmt);
98d7964de8SJohnson Wang writel(readl(regs->reg_hp_en) | BIT(data->fh_id),
99d7964de8SJohnson Wang regs->reg_hp_en);
100d7964de8SJohnson Wang /* Enable SSC */
101d7964de8SJohnson Wang writel(readl(regs->reg_cfg) | data->frddsx_en, regs->reg_cfg);
102d7964de8SJohnson Wang /* Enable Hopping control */
103d7964de8SJohnson Wang writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);
104d7964de8SJohnson Wang
105d7964de8SJohnson Wang } else {
106d7964de8SJohnson Wang /* Switch to APMIXEDSYS control */
107d7964de8SJohnson Wang writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id),
108d7964de8SJohnson Wang regs->reg_hp_en);
109d7964de8SJohnson Wang /* Wait for DDS to be stable */
110d7964de8SJohnson Wang udelay(30);
111d7964de8SJohnson Wang }
112d7964de8SJohnson Wang
113d7964de8SJohnson Wang return 0;
114d7964de8SJohnson Wang }
115d7964de8SJohnson Wang
hopping_hw_flow(struct mtk_clk_pll * pll,struct fh_pll_regs * regs,const struct fh_pll_data * data,struct fh_pll_state * state,unsigned int new_dds)116d7964de8SJohnson Wang static int hopping_hw_flow(struct mtk_clk_pll *pll, struct fh_pll_regs *regs,
117d7964de8SJohnson Wang const struct fh_pll_data *data,
118d7964de8SJohnson Wang struct fh_pll_state *state, unsigned int new_dds)
119d7964de8SJohnson Wang {
120d7964de8SJohnson Wang u32 dds_mask = data->dds_mask;
121d7964de8SJohnson Wang u32 mon_dds = 0;
122d7964de8SJohnson Wang u32 con_pcw_tmp;
123d7964de8SJohnson Wang int ret;
124d7964de8SJohnson Wang
125d7964de8SJohnson Wang if (state->ssc_rate)
126d7964de8SJohnson Wang fhctl_set_ssc_regs(pll, regs, data, 0);
127d7964de8SJohnson Wang
128d7964de8SJohnson Wang writel((readl(pll->pcw_addr) & dds_mask) | data->tgl_org,
129d7964de8SJohnson Wang regs->reg_dds);
130d7964de8SJohnson Wang
131d7964de8SJohnson Wang writel(readl(regs->reg_cfg) | data->sfstrx_en, regs->reg_cfg);
132d7964de8SJohnson Wang writel(readl(regs->reg_cfg) | data->fhctlx_en, regs->reg_cfg);
133d7964de8SJohnson Wang writel(data->slope0_value, regs->reg_slope0);
134d7964de8SJohnson Wang writel(data->slope1_value, regs->reg_slope1);
135d7964de8SJohnson Wang
136d7964de8SJohnson Wang writel(readl(regs->reg_hp_en) | BIT(data->fh_id), regs->reg_hp_en);
137d7964de8SJohnson Wang writel((new_dds) | (data->dvfs_tri), regs->reg_dvfs);
138d7964de8SJohnson Wang
139d7964de8SJohnson Wang /* Wait 1000 us until DDS stable */
140d7964de8SJohnson Wang ret = readl_poll_timeout_atomic(regs->reg_mon, mon_dds,
141d7964de8SJohnson Wang (mon_dds & dds_mask) == new_dds,
142d7964de8SJohnson Wang 10, 1000);
143d7964de8SJohnson Wang if (ret) {
144d7964de8SJohnson Wang pr_warn("%s: FHCTL hopping timeout\n", pll->data->name);
145d7964de8SJohnson Wang dump_hw(pll, regs, data);
146d7964de8SJohnson Wang }
147d7964de8SJohnson Wang
148d7964de8SJohnson Wang con_pcw_tmp = readl(pll->pcw_addr) & (~dds_mask);
149d7964de8SJohnson Wang con_pcw_tmp = (con_pcw_tmp | (readl(regs->reg_mon) & dds_mask) |
150d7964de8SJohnson Wang data->pcwchg);
151d7964de8SJohnson Wang
152d7964de8SJohnson Wang writel(con_pcw_tmp, pll->pcw_addr);
153d7964de8SJohnson Wang writel(readl(regs->reg_hp_en) & ~BIT(data->fh_id), regs->reg_hp_en);
154d7964de8SJohnson Wang
155d7964de8SJohnson Wang if (state->ssc_rate)
156d7964de8SJohnson Wang fhctl_set_ssc_regs(pll, regs, data, state->ssc_rate);
157d7964de8SJohnson Wang
158d7964de8SJohnson Wang return ret;
159d7964de8SJohnson Wang }
160d7964de8SJohnson Wang
__get_postdiv(struct mtk_clk_pll * pll)161d7964de8SJohnson Wang static unsigned int __get_postdiv(struct mtk_clk_pll *pll)
162d7964de8SJohnson Wang {
163d7964de8SJohnson Wang unsigned int regval;
164d7964de8SJohnson Wang
165d7964de8SJohnson Wang regval = readl(pll->pd_addr) >> pll->data->pd_shift;
166d7964de8SJohnson Wang regval &= POSTDIV_MASK;
167d7964de8SJohnson Wang
168d7964de8SJohnson Wang return BIT(regval);
169d7964de8SJohnson Wang }
170d7964de8SJohnson Wang
__set_postdiv(struct mtk_clk_pll * pll,unsigned int postdiv)171d7964de8SJohnson Wang static void __set_postdiv(struct mtk_clk_pll *pll, unsigned int postdiv)
172d7964de8SJohnson Wang {
173d7964de8SJohnson Wang unsigned int regval;
174d7964de8SJohnson Wang
175d7964de8SJohnson Wang regval = readl(pll->pd_addr);
176d7964de8SJohnson Wang regval &= ~(POSTDIV_MASK << pll->data->pd_shift);
177d7964de8SJohnson Wang regval |= (ffs(postdiv) - 1) << pll->data->pd_shift;
178d7964de8SJohnson Wang writel(regval, pll->pd_addr);
179d7964de8SJohnson Wang }
180d7964de8SJohnson Wang
fhctl_hopping(struct mtk_fh * fh,unsigned int new_dds,unsigned int postdiv)181d7964de8SJohnson Wang static int fhctl_hopping(struct mtk_fh *fh, unsigned int new_dds,
182d7964de8SJohnson Wang unsigned int postdiv)
183d7964de8SJohnson Wang {
184d7964de8SJohnson Wang const struct fh_pll_data *data = &fh->pllfh_data->data;
185d7964de8SJohnson Wang struct fh_pll_state *state = &fh->pllfh_data->state;
186d7964de8SJohnson Wang struct fh_pll_regs *regs = &fh->regs;
187d7964de8SJohnson Wang struct mtk_clk_pll *pll = &fh->clk_pll;
188d7964de8SJohnson Wang spinlock_t *lock = fh->lock;
189d7964de8SJohnson Wang unsigned int pll_postdiv;
190d7964de8SJohnson Wang unsigned long flags = 0;
191d7964de8SJohnson Wang int ret;
192d7964de8SJohnson Wang
193d7964de8SJohnson Wang if (postdiv) {
194d7964de8SJohnson Wang pll_postdiv = __get_postdiv(pll);
195d7964de8SJohnson Wang
196d7964de8SJohnson Wang if (postdiv > pll_postdiv)
197d7964de8SJohnson Wang __set_postdiv(pll, postdiv);
198d7964de8SJohnson Wang }
199d7964de8SJohnson Wang
200d7964de8SJohnson Wang spin_lock_irqsave(lock, flags);
201d7964de8SJohnson Wang
202d7964de8SJohnson Wang ret = hopping_hw_flow(pll, regs, data, state, new_dds);
203d7964de8SJohnson Wang
204d7964de8SJohnson Wang spin_unlock_irqrestore(lock, flags);
205d7964de8SJohnson Wang
206d7964de8SJohnson Wang if (postdiv && postdiv < pll_postdiv)
207d7964de8SJohnson Wang __set_postdiv(pll, postdiv);
208d7964de8SJohnson Wang
209d7964de8SJohnson Wang return ret;
210d7964de8SJohnson Wang }
211d7964de8SJohnson Wang
fhctl_ssc_enable(struct mtk_fh * fh,u32 rate)212d7964de8SJohnson Wang static int fhctl_ssc_enable(struct mtk_fh *fh, u32 rate)
213d7964de8SJohnson Wang {
214d7964de8SJohnson Wang const struct fh_pll_data *data = &fh->pllfh_data->data;
215d7964de8SJohnson Wang struct fh_pll_state *state = &fh->pllfh_data->state;
216d7964de8SJohnson Wang struct fh_pll_regs *regs = &fh->regs;
217d7964de8SJohnson Wang struct mtk_clk_pll *pll = &fh->clk_pll;
218d7964de8SJohnson Wang spinlock_t *lock = fh->lock;
219d7964de8SJohnson Wang unsigned long flags = 0;
220d7964de8SJohnson Wang
221d7964de8SJohnson Wang spin_lock_irqsave(lock, flags);
222d7964de8SJohnson Wang
223d7964de8SJohnson Wang fhctl_set_ssc_regs(pll, regs, data, rate);
224d7964de8SJohnson Wang state->ssc_rate = rate;
225d7964de8SJohnson Wang
226d7964de8SJohnson Wang spin_unlock_irqrestore(lock, flags);
227d7964de8SJohnson Wang
228d7964de8SJohnson Wang return 0;
229d7964de8SJohnson Wang }
230d7964de8SJohnson Wang
231d7964de8SJohnson Wang static const struct fh_operation fhctl_ops = {
232d7964de8SJohnson Wang .hopping = fhctl_hopping,
233d7964de8SJohnson Wang .ssc_enable = fhctl_ssc_enable,
234d7964de8SJohnson Wang };
235d7964de8SJohnson Wang
fhctl_get_ops(void)236d7964de8SJohnson Wang const struct fh_operation *fhctl_get_ops(void)
237d7964de8SJohnson Wang {
238d7964de8SJohnson Wang return &fhctl_ops;
239d7964de8SJohnson Wang }
240d7964de8SJohnson Wang
fhctl_hw_init(struct mtk_fh * fh)241d7964de8SJohnson Wang void fhctl_hw_init(struct mtk_fh *fh)
242d7964de8SJohnson Wang {
243d7964de8SJohnson Wang const struct fh_pll_data data = fh->pllfh_data->data;
244d7964de8SJohnson Wang struct fh_pll_state state = fh->pllfh_data->state;
245d7964de8SJohnson Wang struct fh_pll_regs regs = fh->regs;
246d7964de8SJohnson Wang u32 val;
247d7964de8SJohnson Wang
248d7964de8SJohnson Wang /* initial hw register */
249d7964de8SJohnson Wang val = readl(regs.reg_clk_con) | BIT(data.fh_id);
250d7964de8SJohnson Wang writel(val, regs.reg_clk_con);
251d7964de8SJohnson Wang
252d7964de8SJohnson Wang val = readl(regs.reg_rst_con) & ~BIT(data.fh_id);
253d7964de8SJohnson Wang writel(val, regs.reg_rst_con);
254d7964de8SJohnson Wang val = readl(regs.reg_rst_con) | BIT(data.fh_id);
255d7964de8SJohnson Wang writel(val, regs.reg_rst_con);
256d7964de8SJohnson Wang
257d7964de8SJohnson Wang writel(0x0, regs.reg_cfg);
258d7964de8SJohnson Wang writel(0x0, regs.reg_updnlmt);
259d7964de8SJohnson Wang writel(0x0, regs.reg_dds);
260d7964de8SJohnson Wang
261d7964de8SJohnson Wang /* enable ssc if needed */
262d7964de8SJohnson Wang if (state.ssc_rate)
263d7964de8SJohnson Wang fh->ops->ssc_enable(fh, state.ssc_rate);
264d7964de8SJohnson Wang }
265