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Searched refs:regVCN_RB_ENABLE (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c827 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start_dpg_mode()
829 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start_dpg_mode()
837 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start_dpg_mode()
839 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start_dpg_mode()
1191 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start()
1193 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start()
1199 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start()
1201 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start()
H A Dvcn_v4_0.c1010 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_start_dpg_mode()
1012 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start_dpg_mode()
1021 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_start_dpg_mode()
1023 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start_dpg_mode()
1193 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_start()
1195 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start()
1204 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_start()
1206 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_4_0_0_offset.h1308 #define regVCN_RB_ENABLE … macro
H A Dvcn_4_0_3_offset.h1236 #define regVCN_RB_ENABLE … macro