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Searched refs:regVCN_RAS_CNTL (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h442 #define regVCN_RAS_CNTL … macro
H A Dvcn_4_0_0_offset.h776 #define regVCN_RAS_CNTL … macro
H A Dvcn_4_0_3_offset.h780 #define regVCN_RAS_CNTL … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c1760 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), in vcn_v4_0_3_enable_ras()
H A Dvcn_v4_0.c896 SOC15_DPG_MODE_OFFSET(VCN, 0, regVCN_RAS_CNTL), in vcn_v4_0_enable_ras()