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Searched refs:regUVD_VCPU_CNTL (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c765 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
812 VCN, 0, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_3_start_dpg_mode()
1084 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), in vcn_v4_0_3_start()
1148 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, in vcn_v4_0_3_start()
1168 regUVD_VCPU_CNTL), in vcn_v4_0_3_start()
1173 regUVD_VCPU_CNTL), in vcn_v4_0_3_start()
1315 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), in vcn_v4_0_3_stop()
1320 WREG32_P(SOC15_REG_OFFSET(VCN, vcn_inst, regUVD_VCPU_CNTL), 0, in vcn_v4_0_3_stop()
H A Dvcn_v4_0.c939 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_start_dpg_mode()
986 VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v4_0_start_dpg_mode()
1070 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), in vcn_v4_0_start()
1131 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, in vcn_v4_0_start()
1158 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), in vcn_v4_0_start()
1162 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, in vcn_v4_0_start()
1502 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), in vcn_v4_0_stop()
1507 WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0, in vcn_v4_0_stop()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h74 #define regUVD_VCPU_CNTL … macro
H A Dvcn_4_0_0_offset.h422 #define regUVD_VCPU_CNTL … macro
H A Dvcn_4_0_3_offset.h424 #define regUVD_VCPU_CNTL … macro