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Searched refs:regUVD_VCPU_CACHE_SIZE2 (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c380 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_SIZE2, in vcn_v4_0_3_mc_resume()
488 VCN, 0, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
951 regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_3_start_sriov()
H A Dvcn_v4_0.c415 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v4_0_mc_resume()
514 VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1324 regUVD_VCPU_CACHE_SIZE2), in vcn_v4_0_start_sriov()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h40 #define regUVD_VCPU_CACHE_SIZE2 … macro
H A Dvcn_4_0_0_offset.h388 #define regUVD_VCPU_CACHE_SIZE2 … macro
H A Dvcn_4_0_3_offset.h390 #define regUVD_VCPU_CACHE_SIZE2 … macro